VND5T100LAJ-E VND5T100LAS-E Double channel high-side driver with analog current sense for 24 V automotive applications Datasheet - production data PowerSSO-12 Protection - Undervoltage shutdown - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shutdown - Electrostatic discharge protection SO-16N Features Max transient supply voltage VCC 58 V Operating voltage range VCC 8 to 36 V Typ on-state resistance (per ch.) RON 100 m Current limitation (typ) ILIM 22 A Off-state supply current IS 2 A(1) 1. Typical value with all loads connected. AEC-Q100 qualified General - Very low standby current - 3.0 V CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - Compliant with European directive 2002/95/EC - Fault reset standby pin (FR_Stby) - Optimized for LED application Diagnostic functions - Proportional load current sense - High current sense precision for wide range currents - Off-state open-load detection - Output short to VCC detection - Overload and short to ground latch-off - Thermal shutdown latch-off - Very low current sense leakage August 2016 This is information on a product in full production. Application All types of resistive, inductive and capacitive loads Description The VND5T100LAJ-E and VND5T100LAS-E are monolithic devices made using STMicroelectronics(R) VIPower(R) technology, intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the devices against low energy spikes. These devices integrate an analog current sense which delivers a current proportional to the load current. Fault conditions such as overload, overtemperature or short to VCC are reported via the current sense pin. Output current limitation protects the devices in overload condition. The devices latch off in case of overload or thermal shutdown. The devices are reset by a low level pass on the fault reset standby pin. A permanent low level on the inputs and fault reset standby pin disables all outputs and sets the devices in standby mode. DocID023364 Rev 5 1/38 www.st.com Contents VND5T100LAJ-E, VND5T100LAS-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 4 5 6 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21 3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 Maximum demagnetization energy (VCC = 24 V) . . . . . . . . . . . . . . . . . . . 23 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 SO-16N thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 ECOPACK(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 SO-16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1 PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 SO-16N packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2/38 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 24 V; Tj = 25 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current sense (8 V < VCC < 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DocID023364 Rev 5 3/38 3 List of figures VND5T100LAJ-E, VND5T100LAS-E List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram PowerSSO-12 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Configuration diagram SO-16N (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Tstandby definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Treset definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10. Output stuck to VCC detection delay time at FRSTBY activation . . . . . . . . . . . . . . . . . . . . . 15 Figure 11. Delay response time between rising edge of output current and rising edge of current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13. Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 14. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 15. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17. Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 18. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 19. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 20. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 21. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 22. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 23. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 24. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 25. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 26. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 27. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 28. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24 Figure 29. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 25 Figure 30. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 25 Figure 31. SO-16N PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . . 27 Figure 33. SO-16N thermal impedance junction ambient single pulse (one channel on) . . . . . . . . . . 28 Figure 34. Thermal fitting model of a double channel HSD in SO-16N . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 35. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 36. SO-16N package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 37. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 38. PowerSSO-12 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 39. SO-16N tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 40. SO-16N tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4/38 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram 9&& 6LJQDO&ODPS &RQWURO 'LDJQRVWLF 8QGHUYROWDJH ,1 &RQWURO 'LDJQRVWLF 3RZHU &ODPS '5,9(5 ,1 &+ 921 /LPLWDWLRQ &XUUHQW /LPLWDWLRQ 2YHU 7HPSHUDWXUH 2))VWDWH 2SHQORDG )5B6WE\ 96(16(+ &6 &XUUHQW 6HQVH &+ &6 287 /2*,& 287 29(5/2$'3527(&7,21 $&7,9(32:(5/,0,7$7,21 *1' *$3*&)7 Table 1. Pin function Name VCC Function Battery connection OUTn Power output GND Ground connection INn Voltage controlled input pin with hysteresis, CMOS compatible. It controls output switch state CSn Analog current sense pin, it delivers a current proportional to the load current FR_Stby In case of latch-off for overtemperature/overcurrent condition, a low pulse on the FR_Stby pin is needed to reset the channel. The device enters in standby mode if all inputs and the FR_Stby pin are low. DocID023364 Rev 5 5/38 37 Block diagram and pin description VND5T100LAJ-E, VND5T100LAS-E Figure 2. Configuration diagram PowerSSO-12 (top view) 7$% 9&& &6 9&& ,1 287 )5B67%< 287 *1' 287 ,1 287 &6 9&& 3RZHU662 *$3*&)7 Figure 3. Configuration diagram SO-16N (top view) 7$$ 7$$ $4 7$$ */ 065 '3@4UCZ 065 (/% 065 */ 065 $4 7$$ 7$$ 7$$ *$'*60' Table 2. Suggested connections for unused and not connected pins Connection / pin Current sense N.C. Output Input FR_Stby X X Floating Not allowed X(1) X To ground Through 10 K resistor X Not allowed 1. X: do not care. 6/38 DocID023364 Rev 5 Through Through 10 Kresistor 10 Kresistor VND5T100LAJ-E, VND5T100LAS-E 2 Electrical specifications Electrical specifications Figure 4. Current and voltage conventions ,6 9&& 9&& 9)Q ,287Q ,)5B6WE\ 287Q )5B6WE\ 9)5B6WE\ 9287Q ,6(16(Q ,,1Q &6Q ,1Q ,1Q 96(16(Q *1' ,*1' 1RWH9)Q 9287Q9&&GXULQJUHYHUVHEDWWHU\FRQGLWLRQ 2.1 *$3*&)7 Absolute maximum ratings Stressing the device above the ratings listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions reported in this section for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 58 V -VCC Reverse DC supply voltage 0.3 V -IGND DC reverse ground pin current 200 mA IOUT DC output current Internally limited A -IOUT Reverse DC output current 20 A DC input current -1 to 10 mA Fault reset standby DC input current -1 to 1.5 mA 200 mA VCC - 58 to +VCC V IIN IFR_Stby -ICSENSE DC reverse CS pin current VCSENSE Current sense maximum voltage DocID023364 Rev 5 7/38 37 Electrical specifications VND5T100LAJ-E, VND5T100LAS-E Table 3. Absolute maximum ratings (continued) Symbol Value Unit 70 mJ EMAX Maximum switching energy (L = 1.9 mH; Vbat = 32 V; Tjstart = 150C; IOUT = IlimL (Typ)) VESD Electrostatic discharge (Human Body Model: R = 1.5 K C = 100 pF) - INPUT - CURRENT SENSE - FR_STBY - OUTPUT - VCC 4000 2000 4000 5000 5000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Junction operating temperature -40 to 150 C Storage temperature -55 to 150 C 40 H Tj Tstg LSmax 2.2 Parameter Maximum stray inductance in short circuit RL = 300 m, Vbat = 32 V, Tjstart = 150C, IOUT = IlimHmax Thermal data Table 4. Thermal data Maximum value Symbol Unit PowerSSO-12 SO-16N Thermal resistance junction-case (with one channel ON) 6 -- C/W Rthj-pin Thermal resistance junction-pin (with one channel ON) -- 26 C/W Rthj-amb Thermal resistance junction-ambient See Figure 28 See Figure 32 C/W Rthj-case 8/38 Parameter DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E 2.3 Electrical specifications Electrical characteristics 8 V < VCC < 36 V; -40C < Tj < 150C, unless otherwise specified. . Table 5. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit 24 36 V 5 V VCC Operating supply voltage VUSD Undervoltage shutdown 3.5 VUSDhyst Undervoltage shutdown hysteresis 0.5 RON Vclamp IS 8 IOUT = 1.5 A; Tj = 25C On-state resistance(1) VF m 200 IS = 20 mA Supply current IL(off) 100 IOUT = 1.5 A; Tj = 150C Clamp voltage Off-state output current V 58 64 70 V Off-state: VCC = 24 V; Tj = 25C; VIN = VOUT = VSENSE = 0 V 2(2) 5(2) A On-state: VCC = 24 V; VIN = 5 V; IOUT = 0 A 4.2 6 mA 0.01 3 VIN = VOUT = 0 V; VCC = 24 V; Tj = 25C 0 VIN = VOUT = 0 V; VCC = 24 V; Tj = 125C 0 A 5 Output - VCC diode voltage -IOUT = 1.5 A; Tj = 150C 0.7 V Max. Unit 1. For each channel. 2. PowerMos leakage included Table 6. Switching (VCC = 24 V; Tj = 25 C) Symbol Parameter Test conditions Min. Typ. td(on) Turn-on delay time RL = 16 27 s td(off) Turn-off delay time RL = 16 38 s dVOUT/dt(on) Turn-on voltage slope RL = 16 1 Vs dVOUT/dt(off) Turn-off voltage slope RL = 16 0.65 Vs WON Switching energy losses RL = 16 during twon 0.23 mJ WOFF Switching energy losses RL = 16 during twoff 0.26 mJ Table 7. Logic inputs Symbol Parameter VIL Input low level voltage IIL Low level input current VIH Input high level voltage Test conditions VIN = 0.9 V DocID023364 Rev 5 Min. Typ. Max. Unit 0.9 V 1 A 2.1 V 9/38 37 Electrical specifications VND5T100LAJ-E, VND5T100LAS-E Table 7. Logic inputs (continued) Symbol Parameter IIH High level input current VI(hyst) Input hysteresis voltage VICL Test conditions Min. VIN = 2.1 V IIN = 1 mA Unit 10 A VFR_Stby_L Fault_reset_standby low level voltage IFR_Stby_L Low level fault_reset_standby VFR_Stby = 0.9 V current VFR_Stby_H Fault_reset_standby high level voltage IFR_Stby_H High level fault_reset_standby VFR_Stby = 2.1 V current V 5.5 IIN = -1 mA VFR_Stby_CL Max. 0.25 Input clamp voltage VFR_Stby (hyst) Typ. 7 -0.7 V 0.9 Fault_reset_standby hysteresis voltage IFR_Stby = 15 mA (t < 10 ms) A 2.1 V 10 A V 11 IFR_Stby = -1 mA 15 -0.7 V V treset Overload latch-off reset time See Figure 5 2 24 s tstby Standby delay See Figure 6 120 1200 s Figure 5. Tstandby definition )5B6WGE\ ,1387Q ,*1' WVWE\ WVWE\ *$3*&)7 10/38 V 1 0.25 Fault_reset_standby clamp voltage V DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E Electrical specifications Figure 6. Treset definition 7BUHVHW )5B67%< ,1 287387 &6 2YHUORDG &KDQQHO *$3*&)7 Table 8. Protections and diagnostics Symbol Parameter Test conditions IlimH DC short circuit current IlimL Short circuit current during thermal cycling TTSD Shutdown temperature Reset temperature TRS Thermal reset of status VDEMAG VON Typ. Max. Unit 16 22 30 A 30 A 5 V < VCC < 36 V TR THYST VCC = 24 V Min. VCC = 24 V; TR < Tj < TTSD 6 150 175 TRS + 1 TRS + 5 A 200 135 Thermal hysteresis (TTSD - TR) Turn-off output voltage clamp IOUT = 1.5 A; VIN = 0; L = 6 mH Output voltage drop limitation IOUT = 50 mA; Tj = -40C to 150C DocID023364 Rev 5 C C C 7 C VCC - 58 VCC - 64 VCC - 70 V 25 mV 11/38 37 Electrical specifications VND5T100LAJ-E, VND5T100LAS-E Table 9. Current sense (8 V < VCC < 36 V) Symbol Test conditions Min. Typ. Max. Unit KOL IOUT/ISENSE IOUT = 12 mA; VSENSE = 0.5 V; Tj = -40C to 150C 833 KLED IOUT/ISENSE IOUT = 50 mA; VSENSE = 0.5 V; Tj = -40C to 150C 1328 2190 3332 dKLED/KLED(TOT)(1) K0 dK0/K0(1) K1 dK1/K1(1) K2 dK2/K2(1) K3 dK3/K3(1) K4 dK4/K4(1) ISENSE0 = 12 mA to 25 mA; I Current sense ratio OUT ICAL = 18 mA; VSENSE = 0.5 V; drift Tj = -40C to 150C IOUT/ISENSE -30 30 IOUT = 100 mA; VSENSE = 0.5 V; 1170 1950 2730 Tj = -40C to 150C Current sense ratio IOUT = 100 mA; VSENSE = 0.5 V; -18 drift Tj = -40C to 150C IOUT/ISENSE IOUT = 0.4 A; VSENSE = 1 V; Tj = -40C to 150C Current sense ratio IOUT = 0.4 A; VSENSE = 1 V; drift Tj = -40C to 150C IOUT/ISENSE IOUT = 0.8 A; VSENSE = 2 V; Tj = -40C to 150C Current sense ratio IOUT = 0.8 A; VSENSE = 2 V; drift Tj = -40C to 150C IOUT/ISENSE IOUT = 1.6 A; VSENSE = 2 V; Tj = -40C to 150C Current sense ratio IOUT = 1.6 A; VSENSE = 2 V; drift Tj = -40C to 150C IOUT/ISENSE IOUT = 6 A; VSENSE = 4 V; Tj = -40C to 150C Current sense ratio IOUT = 6 A; VSENSE = 4 V; drift Tj = -40C to 150C Analog sense leakage current % 18 % 1259 1740 2191 -15 15 % 1372 1730 2058 -12 12 % 1509 1720 1921 -8 8 % 1646 1720 1784 -4 4 % IOUT = 0 A; VSENSE = 0 V; VIN = 0 V; Tj = -40 C to 150 C 0 1 A IOUT = 0 A; VSENSE = 0 V; VIN = 5 V; Tj = -40 C to 150 C 0 2 A VSENSE Max analog sense output voltage IOUT = 6 A; RSENSE = 3.9 K 5 VSENSEH Analog sense output voltage in fault condition(2) VCC = 24 V; RSENSE = 3.9 K 7.5 8.5 9.5 V ISENSEH Analog sense output current in fault condition(2) VCC = 24 V; VSENSE = 5 V 4.9 9 12 mA 100 200 s tDSENSE2H 12/38 Parameter VSENSE < 4 V; Delay response 0.07 A < IOUT < 6 A; time from rising = 90 % of ISENSE max I edge of INPUT pin SENSE (see Figure 7) DocID023364 Rev 5 V VND5T100LAJ-E, VND5T100LAS-E Electrical specifications Table 9. Current sense (8 V < VCC < 36 V) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit tDSENSE2H Delay response time between rising edge of output current and rising edge of current sense VSENSE < 4 V; ISENSE = 90 % of ISENSEMAX; IOUT = 90 % of IOUTMAX; IOUTMAX = 1.5 A (see Figure 12) tDSENSE2L VSENSE < 4 V; Delay response 0.07 A < IOUT < 6 A; time from falling I = 10 % of ISENSE max edge of INPUT pin SENSE (see Figure 7) 150 s 20 s 5 1. Parameter guaranteed by design; it is not tested. 2. Fault condition includes: power limitation, overtemperature and open-load in OFF-state condition. Table 10. Open-load detection Symbol Test conditions Min. Typ. Max. Unit Open-load off-state voltage detection threshold VIN = 0 V; 8 V < VCC < 36 V; FR_STBY = 5 V 2 -- 4 V Output short circuit to VCC detection delay at turn off See Figure 7; FR_STBY = 5 V 180 -- 1800 s Output short circuit to tDFRSTK_ON VCC detection delay at FRSTBY activation See Figure 10; Input1,2 = low -- 50 s -- 0 A -- 20 s VOL tDSTKON Parameter IL(off2) Off-state output current at VOUT = 4V VIN = 0 V; VSENSE = 0 V; VOUT rising from 0 V to 4 V; FR_STBY = 5 V td_vol Delay response from output rising edge to VSENSE rising edge in open-load VOUT = 4 V; VIN = 0 V; VSENSE = 90 % of VSENSEH; RSENSE = 3.9 K FR_STBY = 5 V -120 Figure 7. Current sense delay characteristics ,1387 /2$'&855(17 6(16(&855(17 W'6(16(+ W'6(16(/ *$3*&)7 DocID023364 Rev 5 13/38 37 Electrical specifications VND5T100LAJ-E, VND5T100LAS-E Figure 8. Open-load off-state delay timing 2XWSXWVWXFNDW9&& 9287!92/ 9,1 96(16(+ 9&6 W'67.21 *$3*&)7 Figure 9. Switching characteristics 9287 W:RQ W:RII G9287GW RII G9287GW RQ WU WI W ,1387 7G RQ 7G RII W *$3*&)7 14/38 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E Electrical specifications Figure 10. Output stuck to VCC detection delay time at FRSTBY activation )567%< 9VHQVH+ 9&6 W')567.B21 ,QSXW /RZ *$3*&)7 Figure 11. Delay response time between rising edge of output current and rising edge of current sense 9,1 W'6(16(+ W ,287 ,2870$; ,2870$; W ,6(16( ,6(16(0$; ,6(16(0$; W *$3*&)7 DocID023364 Rev 5 15/38 37 Electrical specifications VND5T100LAJ-E, VND5T100LAS-E Figure 12. Output voltage drop limitation 9&&9287 7M & 7M & 7M & 921 ,287 921521 7 $*9 Figure 13. Device behavior in overload condition WBUHVHW WBUHVHW )$8/7B5(6(7 ,1Q 287387Q 9VHQVH+ &6Q RYHUORDG RYHUORDGUHVHW RYHUORDGGLDJUHVHW 29(5/2$' &+$11(/Q 287387QDQG&6QFRQWUROOHGE\,1Q )$8/7B5(6(7IURPWRQRDFWLRQRQ&6QSLQ RYHUORDGODWFKRII,QQKLJK&6QKLJK )$8/7B5(6(7ORZ$1'7HPSFKDQQHOQRYHUORDGBUHVHWRYHUORDGODWFKUHVHWDIWHUWBUHVHW WR)$8/7B5(6(7ORZ$1',1QKLJKWKHUPDOF\FOLQJ&6QKLJK )$8/7B5(6(7KLJKODWFKRIIUHVHWGLVDEOHG WRRYHUORDGHYHQWDQG)$8/7B5(6(7KLJKODWFKRIIQRWKHUPDOF\FOLQJ WRRYHUORDGGLDJQRVWLFGLVDEOHGHQDEOHGE\WKHLQSXW RYHUORDGODWFKRIIUHVHWE\)$8/7B5(6(7 29(5/2$' WKHUPDOVKXWGRZQ25SRZHUOLPLWDWLRQ *$3*&)7 16/38 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E Electrical specifications Table 11. Truth table Conditions Fault reset standby Input Output Sense Standby L L L 0 Normal operation X X L H L H 0 Nominal Overload X X L H L H 0 > Nominal Overtemperature / short to ground X L H L H H L Cycling Latched 0 VSENSEH VSENSEH Undervoltage X X L 0 Short to VBAT L H X L L H H H H 0 VSENSEH < Nominal Open-load off-state (with pull-up) L H X L L H H H H 0 VSENSEH 0 Negative output voltage clamp X L Negative 0 DocID023364 Rev 5 17/38 37 Electrical specifications VND5T100LAJ-E, VND5T100LAS-E Table 12. Electrical transient requirements (part 1) ISO 7637-2: 2004(E) Test levels (1) Test pulse III IV Number of pulses or test times 1 - 450 V - 600 V 5000 pulses 0.5 s 5s 1 ms, 50 2a + 37 V + 50 V 5000 pulses 0.2 s 5s 50 s, 2 3a - 150 V - 200 V 1h 90 ms 100 ms 0.1 s, 50 3b + 150 V + 200 V 1h 90 ms 100 ms 0.1 s, 50 4 - 12 V - 16 V 1 pulse 100 ms, 0.01 5b (2) + 123 V + 174 V 1 pulse 350 ms, 1 Burst cycle/pulse repetition time Delays and impedance Table 13. Electrical transient requirements (part 2) ISO 7637-2: 2004(E) Test level results Test pulse III IV 1 C C 2a C C 3a C C 3b(1) E E 3b(2) C C 4 C C 5b (3) C C 1. Without capacitor between VCC and GND. 2. With 10 nF between VCC and GND. 3. External load dump clamp, 58 V maximum, referred to ground. Table 14. Electrical transient requirements (part 3) 18/38 Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E 2.4 Electrical specifications Electrical characteristics curves Figure 14. Off-state output current Figure 15. High level input current ,ORII>X$@ ,LK>X$@ 9LQ 9 2IIVWDWH 9&& 9 9LQ 9RXW 7F>&@ 7F>&@ *$3*&)7 *$3*&)7 Figure 16. Input clamp voltage Figure 17. Input high level voltage 9LK>9@ 9LFO>9@ ,LQ P $ *$3*&)7 *$3*&)7 Figure 18. Input low level voltage Figure 19. Input hysteresis voltage 9LK\VW>9@ 9LO>9@ 7F>&@ 7F>&@ 7F>&@ 7F>&@ *$3*&)7 DocID023364 Rev 5 *$3*&)7 19/38 37 Electrical specifications VND5T100LAJ-E, VND5T100LAS-E Figure 20. On-state resistance vs Tcase Figure 21. On-state resistance vs VCC 5RQ>P 2KP @ 5RQ>P 2KP @ 7F & 7F & ,RXW $ 9FF 9 7F & 7F & 9FF>9@ 7F>&@ *$3*&)7 ("1($'5 Figure 22. ILIMH vs Tcase Figure 23. Turn-on voltage slope G9RXWGW 2Q>9XV@ ,OLP K>$@ 9FF 9 9FF 9 5O 7F>&@ 7F>&@ *$3*&)7 *$3*&)7 Figure 24. Turn-off voltage slope G9RXWGW 2II>9XV@ 9FF 9 5O 7F>&@ *$3*&)7 20/38 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E 3 Application information Application information Figure 25. Application schematic 9 9&& 5SURW )5B6WE\ 'OG 0&8 5SURW ,1 5SURW &6 287 *1' 56(16( &H[W 9*1' '*1' *$3*&)7 3.1 GND protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (RGND only) This solution can be used with any type of load. The following is an indication on how to select the RGND resistor. 1. RGND 600 mV / (IS(on)max). 2. RGND VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0: during reverse battery situations) is: PD = (-VCC)2 / RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests Solution 2 is used (see below). DocID023364 Rev 5 21/38 37 Application information 3.1.2 VND5T100LAJ-E, VND5T100LAS-E Solution 2: diode (DGND) in the ground line A resistor (RGND = 4.7 kshould be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and in the status output values, if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/2 table. 3.3 MCUI/Os protection If a ground protection network is used and negative transient are present on the VCC line, the control pins are pulled negative. ST suggests that a resistor (Rprot) be inserted in line to prevent the microcontroller I/O pins from latching-up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= -600 V and Ilatchup 20 mA; VOHC 4.5 V 30 k Rprot 180 k. Recommended Rprot value is 60 k 22/38 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E Maximum demagnetization energy (VCC = 24 V) Figure 26. Maximum turn-off current versus inductance A B C , $ 3.4 Application information / P+ *$3*&)7 A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t 1. Values are generated with RL =0 . In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. DocID023364 Rev 5 23/38 37 Package and PCB thermal data VND5T100LAJ-E, VND5T100LAS-E 4 Package and PCB thermal data 4.1 PowerSSO-12 thermal data Figure 27. PowerSSO-12 PC board *$3*&)7 . 1. Layout condition of Rth and Zth measurements (Board finish thickness 1.6 mm +/- 10 %; Board double layer; Board dimension 77 mm x 86 mm; Board Material FR4; Cu thickness 0.070 mm (front and back side); Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm; Footprint dimension 4.1 mm x 6.5 mm) Figure 28. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) RTHjamb 65 60 55 RTHjamb 50 45 40 35 30 0 2 4 6 8 10 GAPGCFT000124 24/38 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E Package and PCB thermal data Figure 29. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON) =7+ &: &X FP &X FP &X I RR WSULQW 7LPH V *$3*&)7 Figure 30. Thermal fitting model of a double channel HSD in PowerSSO-12 *$3*&)7 1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Equation 1: pulse calculation formula Z TH = R TH + Z THtp 1 - where = tp T DocID023364 Rev 5 25/38 37 Package and PCB thermal data VND5T100LAJ-E, VND5T100LAS-E Table 15. Thermal parameters 2 26/38 Area/island (cm ) Footprint 2 8 R1 = R7 (C/W) 0.8 R2 = R8 (C/W) 1.5 R3 (C/W) 3 R4 (C/W) 8 8 7 R5 (C/W) 22 15 10 R6 (C/W) 26 20 15 C1 = C7 (W.s/C) 0.0008 C2 = C8 (W.s/C) 0.005 C3 (W.s/C) 0.05 C4 (W.s/C) 0.2 0.1 0.1 C5 (W.s/C) 0.27 0.8 1 C6 (W.s/C) 3 6 9 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E 4.2 Package and PCB thermal data SO-16N thermal data Figure 31. SO-16N PC board ("1($'5 1. Layout condition of Rth and Zth measurements (Board finish thickness 1.6 mm +/- 10%; Board double layer; Board dimension 129 x 60; Board Material FR4; Cu thickness 0.070mm (front and back side), Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm). Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) 57+MDPE 57+MDPE ("1($'5 DocID023364 Rev 5 27/38 37 Package and PCB thermal data VND5T100LAJ-E, VND5T100LAS-E Figure 33. SO-16N thermal impedance junction ambient single pulse (one channel on) =7+ &: &X FP &X FP &X IRRWSULQW 7LPH V ("1($'5 Figure 34. Thermal fitting model of a double channel HSD in SO-16N ("1($'5 Equation 2: pulse calculation formula Z TH = R TH + Z THtp 1 - where 28/38 = tp T DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E Package and PCB thermal data Table 16. Thermal parameters 2 Area/island (cm ) Footprint 2 8 R1 = R7 (C/W) 0.8 R2 = R8(C/W) 3 R3 (C/W) 6 R4 (C/W) 10 R5 (C/W) 20 14 12 R6 (C/W) 27 23 14 C1 = C7(W.s/C) 0.0005 C2 = C8 (W.s/C) 0.005 C3 (W.s/C) 0.015 C4 (W.s/C) 0.1 C5 (W.s/C) 0.3 0.5 0.5 C6 (W.s/C) 2.5 5 7 DocID023364 Rev 5 29/38 37 Package and packing information VND5T100LAJ-E, VND5T100LAS-E 5 Package and packing information 5.1 ECOPACK(R) In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 PowerSSO-12 mechanical data Figure 35. PowerSSO-12 package dimensions ("1($'5 30/38 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E Package and packing information Table 17. PowerSSO-12 mechanical data Millimeters Symbol Min. Typ. Max. A 1.250 1.700 A1 0.000 0.100 A2 1.100 1.600 B 0.230 0.410 C 0.190 0.250 D 4.800 5.000 E 3.800 4.000 e 0.800 H 5.800 6.200 h 0.250 0.550 L 0.400 1.270 k 0 8 X 1.900 2.500 Y 3.600 4.200 ddd 0.100 DocID023364 Rev 5 31/38 37 Package and packing information 5.3 VND5T100LAJ-E, VND5T100LAS-E SO-16N package information Figure 36. SO-16N package dimensions ("1($'5 32/38 DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E Package and packing information Table 18. SO-16N mechanical data Millimeters Symbol Min. Typ. A Max. 1.75 A1 0.10 A2 1.25 b 0.31 0.51 c 017 0.25 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 0.25 1.27 h 0.25 0.50 L 0.40 1.27 k 0 8 ccc 0.10 DocID023364 Rev 5 33/38 37 Packing information VND5T100LAJ-E, VND5T100LAS-E 6 Packing information 6.1 PowerSSO-12 packing information Figure 37. PowerSSO-12 tube shipment (no suffix) All dimensions are in mm. B C Base q.ty Bulk q.ty Tube length ( 0.5) A B C ( 0.1) A 100 2000 532 1.85 6.75 0.6 GA P GC FT000123 Figure 38. PowerSSO-12 tape and reel shipment (suffix "TR") Reel dimensions Base q.ty Bulk q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 All dimensions are in mm. End Start Top cover tape No components Components Empty components pockets saled with cover tape. User direction of feed 34/38 DocID023364 Rev 5 No components 500mm min 500mm min VND5T100LAJ-E, VND5T100LAS-E 6.2 Packing information SO-16N packing information Figure 39. SO-16N tube shipment (no suffix) B Base q.ty Bulk q.ty Tube length ( 0.5) A B C ( 0.1) C A 50 1000 532 3.2 6 0.6 All dimensions are in mm. Figure 40. SO-16N tape and reel shipment (suffix "TR") .REEL DIMENSIONS Base q.ty Bulk q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 16 4 8 1.5 1.5 7.5 6.5 2 End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed DocID023364 Rev 5 35/38 37 Order code 7 VND5T100LAJ-E, VND5T100LAS-E Order code Table 19. Device summary Order codes Package 36/38 Tube Tape and reel PowerSSO-12 VND5T100LAJ-E VND5T100LAJTR-E SO-16N VND5T100LAS-E VND5T100LASTR-E DocID023364 Rev 5 VND5T100LAJ-E, VND5T100LAS-E 8 Revision history Revision history Table 20. Document revision history Date Revision Changes 25-Jun-2012 1 Initial release. 18-Sep-2013 2 Updated disclaimer. 30-Apr-2014 3 Added SO-16N package and related details. 08-Feb-2016 4 Table 4: Thermal data: - Rthj-case: updated values - Rthj-pin: added row Updated Section 5.2: PowerSSO-12 mechanical data and Section 5.3: SO-16N package information 23-Aug-2016 5 Added indication of AEC-Q100 qualification in Features. Updated Figure 3: Configuration diagram SO-16N (top view). DocID023364 Rev 5 37/38 37 VND5T100LAJ-E, VND5T100LAS-E IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved 38/38 DocID023364 Rev 5