3.3V 150 MHz Multi-Output Zero Del ay Buffer
Z9305/Z9309
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07196 Rev. *A Revised December 22, 2002
Features
• Zero input-output propagation delay
• Output-output skew less than 250 ps
• Device-device skew less than 700 ps
• One input drives nine outputs, grouped as 4/4/1 (Z9309)
• 10 MHz to 150 MHz operating range, compatible with
CPU and PCI bus frequencies
• Less than 200 ps cycle-cycle jitter, compatible with
Pentium® and Pentium Pro®–based systems
•Spread Spectrum Compatible
•Test Mode to bypass PLL (Z9309)
•Available in space-saving 16-pin 150-mil SOIC and
TSSOP package (Z9309), and 8-pin 150-Mil SOIC
package (Z9305)
PLL
REF
CLKA1
Select Input
Decoding
S2
S1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
PLL
REF
CLK1
CLK2
CLK3
CLK4
CLKOUT
Block Diagram (Z9305)
Block Diagram (Z9309)
Z9305/Z9309
Document #: 38-07196 Rev. *A Page 2 of 7
Product Description
The Z9309 is a low cost 3.3V zero delay buffer designed to
distribute high speed clocks in PC system devices and
SDRAM modules and is av ailable in a 16- pin SOIC or TSSOP
package. The Z9305 is an 8-pin version of the Z9309 and it
accepts one reference input and drives out five low skew
clocks. The devices have an on-chip PLL which locks to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
The Z9309 has two banks of four outputs each, which can be
contr olled by the Sel ect inpu ts as show n in the Tab le 1. If all
output clocks are not required, Bank B can be tri-stated. The
selec t inputs al so all ow the inpu t clock to be directl y applied to
the output for chip and system testing purposes.
The Z9305 a nd Z9 309 PLLs enter a Po wer D own m ode when
there are no rising edges on the REF input. In this state, the
outputs are tri-stated and the PLL is turned of f, resulting in less
than 50 uA of curren t draw. The Z 9309 PLL s huts down i n one
addition al case as shown in Table 1.
Multip le Z9 305 and Z9309 de vice s can ac cept th e sam e input
clock and distribute it. In this case, the skew between the
outputs of two dev ice s is gua rant eed to be less than 700 ps.
All outp uts have less than 200 ps o f cycle-cycle jitter . The inp ut
to output propagation delay is guaranteed to be less than 350
ps, and the output to ou tput skew is gu aranteed to be less than
250 ps.
Connection Diagram
CLKOU
CLK4
VDD
CLK3
1
2
3
4
8
7
6
5
REF
CLK2
CLK1
GND
Z9305
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
LKA1
LKA2
VDD
GND
LKB1
LKB2
S2
Z9309
Pin Description (Z9305)
PIN No. Pin Name I/O Description
1REF
[1] I Input reference frequency, 5.0 V tolerant input
2CLK2
[1] O Buffered clock output
3CLK1
[1] O Buffered clock output
4 GND I Ground
5CLK3
[1] O Buffered clock output
6V
DD 3.3V supply
7CLK4
[1] O Buffered clock output
8CLKOUT
[1] O Buffered clock output, internal feedback on this pin
Pin Description (9309)
PIN No. Pin Name I/O Description
1REF
[1] I Input reference frequency, 5.0 V tolerant input
2 CLKA1[1] O Clock output, bank A
3 CLKA2[1] O Clock output, bank A
4V
DD I 3.3V supply
5 GND I Ground
6 CLKB1[1] O Clock output, bank B
7 CLKB2[1] O Clock output, bank B
8S2
[2] I Select input pin, bit 2
9S1
[2] I Select input pin, bit 1
10 CLKB3[1] O Clock output, bank B
11 CLKB4[1] O Clock output, bank B
12 GND Ground
13 VDD 3.3V supply
14 CLKA3[1] O Clock output, bank A
15 CLKA4[1] O Clock output, bank A
16 CLKOUT[1] O Buffered output, internal feedback on this pin.
Notes:
1. Includes weak pull- do wn.
2. Includes weak pull- up .
Z9305/Z9309
Document #: 38-07196 Rev. *A Page 3 of 7
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve sero delay
between input and output. Since the CLKOUT pin is the
interna l feedback to the PLL, it s relative load ing can adjus t the
input-output delay. This is shown in the above graph.
For applications requiring zero I/O delay, all outputs including
CLKOUT must be equally loaded. Even if CLKOUT is not
used, it must have a load capacity equal to that of other
outputs . If input-to-o utput delay adjustment s are require d, use
the above graph to calculate loading differences between the
CLKOUT pin and other outputs. For zero output-output skew,
be sure to load all outputs equally.
Z9309 Select Input Functionality
S2 S1 CLKA1-A4 CLKB1-B4 CLK-OUT[3] Output Source PLL Shut-down
0 0 3-state 3-state Driven PLL N
0 1 Driven 3-state Driven PLL N
1 0 Driven Driven Driven REF Y
1 1 Driven Driven Driven PLL N
0-5-10-15-20-25-30 5 1015202530
1500
1000
500
0
-500
-1000
-1500
Ref - Input to CLK A/ CLK B Delay (ps)
Output Load Difference: CLKOUT Load - CLKA/CLKB Load (PF)
REF, Input T0 CLKA/CLKB Delay versus Loading Difference Between CLKOUT and CLKA/CLKB Pins
Note:
3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and outputs.
Z9305/Z9309
Document #: 38-07196 Rev. *A Page 4 of 7
Maximum Ratings[4]
Voltage Relative to VSS.................................................–0.3V
Voltage Relative to VDD ..................................................0.3V
Storage Temperature.................................–65°C to + 150°C
Operating Temperature.................................–40°C to +85°C
Maximum Power Supply....................................................7V
Reference Input Voltage ........................................–0.5 to 7V
This device contains circuitry to protect input against damage
from high static voltages or electric fields. Precautions should
be ta ken, howeve r, to av oid ap plica tions to th is c ircuit of a ny
voltage higher than the maximum rated voltages. For proper
operation, VIN and VOUT should be constrained to the range:
VSS < (VIN or VOUT) < VDD .
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Electrical Characteristics (Z9305/Z9309) (VDD = 3.0 – 3.6V, TA = –40°C to 85°C)
Parameter Description Test Conditions Min. Typ. Max. Units
VIL Input LOW Voltage4 –– 0.8 Vdc
VIH Input HIGH Voltage4 –2.0 –Vdc
IIL Input LOW Current VIN = 0V 50.0 µA
IIH Input HIGH Current VIN = VDD ±100 µA
VOL Output LOW Voltage5 IOL = 8 mA 0.4 V
VOH Output HIGH Voltage5 IOH = –8mA 2.4 V
Ioz 3-state Leakage Current S1 = S2 = GND –– 10 µA
Idd Power-Down Supply Current Ref = 0 MHz –– 50 µA
Idd Dynamic Supply Current Unload outputs, 66.66 MHz, select
inputs at VDD or GND. –– 40 mA
Switching Characteristics (Z9305/Z9309) (VDD = 3.0 – 3.6V, TA = –40°C to 85°C)
Parameter Description Test Conditions Min. Typ. Max. Units
Fin Frequency 30 pF load 10 150 MHz
–Duty Cycle (T2/T1)[7] Measu red @ 1.4V 45 50 55 %
t3Rise Time[7] Measu red betw e en 0.8 V and 2. 0V
15 pF Load –1.5 nSec
t4Fall Time[7] Measu red betw e en 0.8 V and 2.0V
15 pF Load 1.5 nSec
t5Output-to-Output Ske w[7] All output equally loaded ––250 pSec
t6Delay, REF Rising Edge to
CLKOUT Rising Edge[7] Measu red at VDD/2 –0+ 350 pSec
t7Device-to-Device Skew [7] Measured at VDD/2 on FBK pins of
devices - 0 700 pSec
tj Cycle-to-Cycle Jitter[7] Measured at 66.67 MHz, loaded
outputs, input Trise/Fall < 1 nS ––200 pSec
tLOC K Maximum PLL Lock Time[7] Stable power supply, valid clocks
presented on REF pin. 1.0 ms
Notes:
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. REF and FBK inputs have a threshold voltage of VDD/2.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
Z9305/Z9309
Document #: 38-07196 Rev. *A Page 5 of 7
Test Circuit Diagram
Package Drawing and Dimensions
Package Drawing and Dimensions (16-pi n
150-mil SOIC)
8-pin SOIC Outline Dimensions
Parameter
Inches Millimeters
Min. Nom. Max. Min. Nom. Max.
A 0.053 - 0.069 1.35 - 1.75
A10.004 - 0.010 0.10 - 0.25
A2 0.047 - 0.059 1.20 - 1.50
B 0.013 - 0.020 0.33 - 0.51
C 0.007 - 0.010 0.19 - 0.25
D 0.189 - 0.197 4.80 - 5.00
E 0.150 - 0.157 3.80 - 4.00
e 0.050 BSC 1.27 BSC
H 0.228 - 0.244 5.80 - 6.20
L 0.016 - 0.050 0.40 - 1.27
a0º-8º0º-8º
VDD
VDD
GND GND
Outputs
0.1 uF
0.1 uF
CLK out
C
LOAD
Test Circuit
a
Be
A
A1
A2
D
E
H
L
C
16-pin SOIC Outline Dimensions (150 mil)
Parameter Inches Millimeters
Min. Nom. Max. Min. Nom. Max.
A 0.053 - 0.069 1.35 - 1.75
A10.004 - 0.010 0.10 - 0.25
A2 0.047 - 0.059 1.20 - 1.50
B 0.013 - 0.020 0.33 - 0.51
C 0.007 - 0.010 0.19 - 0.25
D 0.366 - 0.394 9.80 - 10.00
E 0.150 - 0.157 3.80 - 4.00
e 0.050 BSC 1.27 BSC
H 0.228 - 0.244 5.80 - 6.20
L 0.016 - 0.050 0.40 - 1.27
a0º-8º0º-8º
16-pin T SS O P O u tl in e Dime n s i on s
Parameter Inches Millimeters
Min. Nom. Max. Min. Nom. Max.
A - - 0.047 - - 1.20
A10.002 - 0.006 0.05 - 0.15
A2 0.031 0.039 0.041 0.80 1.00 1.05
B 0.007 - 0.012 0.19 - 0.30
C 0.004 - 0.008 0.09 - 0.20
D 0.193 0.197 0.201 4.90 5.00 5.10
E 0.169 0.173 0.177 4.30 4.40 4.50
e 0.026 BSC 0.65 BSC
H 0.244 0.252 0.260 6.20 6.40 6.60
L 0.018 0.024 0.030 0.45 0.60 0.75
a0º-8º0º-8º
a
Be
A
A1
A2
D
EH
L
C
Z9305/Z9309
Document #: 38-07196 Rev. *A Page 6 of 7
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
The ordering part number is formed by a combination of device
number, device revision, package style, and screening as
shown below.
Pentium® and Pentium Pro® are registered trademarks of Intel Corporation. All product and company names mentioned in this
document are the trademarks of their respective holders.
Ordering Information
Part Number Package Type Production Flow
Z9305DZ 8-pin SOIC Commercial, –40°C to +85°C
Z9309CZ 16-pin SOIC Commercial, –40°C to +85°C
Z9309CT 16-pin TSSOP Commercial, –40°C to +85°C
Marking: Example: Date Code
Z9305DZ
Lot #
Z9305DZ
Package
Z = SOIC, 150 Mil.
T = TSSOP
Revision
Cypress Device Number
M
arking: Example: Date Code
Z9309CZ
Lot #
Z9309CZ
Package
Z = SOIC, 150 Mil.
T = TSSOP
Revision
Cypress Device Number
Z9305/Z9309
Document #: 38-07196 Rev. *A Page 7 of 7
Document Title: Z9305/Z9309 3.3V 150 MHz Multi-Output Zero Delay Buffer
Document Number:38-07196
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 111328 12/17/01 DMG New Data Sheet
*A 122825 12/22/02 RBI Add Power up Requirements to Maximum Ratings Information
