ISL28148FIZ-T7 - Intersil - Datasheet.Directory

FN6337.4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL28148, ISL28248, ISL28448

4.5MHz, Single Dual and Quad Precision

Rail-to-Rail Input-Output (RRIO) Op Amps

with Very Low Input Bias Current

The ISL28148, ISL28248 and ISL28448 are 4.5MHz

low-power single, dual and quad operational amplifiers. The

parts are optimized for single supply operation from 2.4V to

5.5V, allowing operation from one lithium cell or two Ni-Cd

batteries.

The single, dual and quad feature an Input Range

Enhancement Circuit (IREC) which enables them to maintain

CMRR performance for input voltages greater than the

positive supply. The input signal is capable of swinging

0.25V above the positive supply and to 100mV below the

negative supply with only a slight deg radation of the CMRR

performance. The output operation is rail-to-rail.

The parts draw minimal supply current (900µA per amplifier)

while meeting excellent DC accuracy, AC performance,

noise and output drive specifications. The ISL28148 features

an enable pin that can be used to turn the device off and

reduce the supply current to a maximum of 16µA. Operation

is guaranteed over -40°C to +125°C temperature range.

Features

• 4.5MHz gain bandwidth product

• 900µA supply current (per amplifier)

• 1.8mV maximum offset voltage

• 1pA typical input bias current

• Down to 2.4V single supply operation

• Rail-to-rail input and output

• Enable pin (ISL28148 SOT-23 package only)

• -40°C to +125°C operation

• Pb-free (RoHS compliant)

Applications

• Low-end audio

• 4mA to 20mA current loops

• Medical devices

• Sensor amplifiers

• ADC buffers

• DAC output amplifiers

Ordering Information

PART NUMBER

(Note) PART MARKING PACKAGE

(Pb-Free) PKG.

DWG. #

ISL28148FHZ-T7* GABT (Note 2) 6 Ld SOT-23 (Tape and Reel) P6.064A

ISL28148FHZ-T7A* GABT (Note 2) 6 Ld SOT-23 (Tape and Reel) P6.064A

ISL28248FBZ 28248 FBZ 8 Ld SOIC M8.15E

ISL28248FBZ-T7* 28248 FBZ 8 Ld S O I C (Tap e and Re el ) M8.15E

ISL28248FUZ 8248Z 8 Ld MSOP M8.118A

ISL28248FUZ-T7* 8248Z 8 Ld MSOP (Tape and Reel) M8.1 18A

Coming So on, ISL28448FVZ MXZ 14 Ld TSSOP M14.173

Coming So on, ISL28448FVZ-T7* MXZ 14 Ld TSSOP (Tape and Reel) M14.173

*Please refer to TB347 for details on reel specifications.

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die att ach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC

J STD-020.

2. The part marking is located on the bottom of the part.

Data Sheet September 21, 2010

2FN6337.4

September 21, 2010

Pinouts ISL28148

(6 LD SOT-23)

TOP VIEW

ISL28248

(8 LD SOIC)

TOP VIEW

ISL28248

(8 LD MSOP)

TOP VIEW

ISL28448

(14 LD TSSOP)

TOP VIEW

OUT

V-

IN+

V+

IN-

OUT_A

IN-_A

IN+_A

V+

OUT_B

IN-_B

V- IN+_B

OUT_A

IN-_A

IN+_A

V+

OUT_B

IN-_B

V- IN+_B

OUT_A

IN-_A

IN+_A

V+

IN+_B

IN-_B

OUT_B

OUT_D

IN-_D

IN+_D

V-

IN+_C

IN-_C

OUT_C

+- +-

ISL28148, ISL28248, ISL28448

3FN6337.4

September 21, 2010

Absolute Maximum Ratings (TA = +25°C) Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V

Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs

Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1200V

Thermal Resistance (Typical, Note 3) θJA (°C/W)

6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230

8 Ld SO Package. . . . . . . . . . . . . . . . . . . . . . . . . . . 125

8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 175

14 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 115

Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . .+125°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Electrical Specifications V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified.

Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data

established by characterization.

PARAMETER DESCRIPTION CONDITIONS MIN

(Note 4) TYP MAX

(Note 4) UNIT

VOS Input Offset Voltage ISL28148 -1.8

-2 01.8

2mV

ISL28248 and ISL28448 -1.8

-2.8 01.8

2.8 mV

Input Offset Voltage vs Temperature 0.03 µV/°C

IOS Input Offset Current TA = -40°C to +85°C -35

-80 ±535

80 pA

IBInput Bias Current TA = -40°C to +85°C -30

-80 ±130

80 pA

CMIR Common-Mode Voltage Range Guaranteed by CMRR 05V

CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 75

70 98 dB

PSRR Power Supply Rejection Ratio V+ = 2.4V to 5.5V 80

75 98 dB

AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ to VCM 200

150 580 V/mV

VO = 0.5V to 4.5V, RL = 1kΩ to VCM 50 V/mV

VOUT Maximum Output Voltage Swing Output low, RL = 100kΩ to VCM 36

8mV

Output low, RL = 1kΩ to VCM 50 70

110 mV

Output high, RL = 100kΩ to VCM 4.994

4.99 4.998 V

Output high, RL = 1kΩ to VCM 4.93

4.89 4.95 V

IS,ON Quiescent Supply Current, Enabled Per Amplifier 0.9 1.25

1.4 mA

IS,OFF Quiescent Supply Current, Disabled ISL28148 SOT-23 package only 10 14

16 µA

IO+ Short-Circuit Output Source Current RL = 10Ω to VCM 48

45 75 mA

ΔVOS

ΔT

----------------

ISL28148, ISL28248, ISL28448

4FN6337.4

September 21, 2010

IO- Short-Circuit Output Sink Current RL = 10Ω to VCM -68 -48

-45 mA

VSUPPLY Supply Operating Range V+ to V- 2.4 5.5 V

VENH EN Pin High Level ISL28148 SOT-23 package only 2V

VENL EN Pin Low Level ISL28148 SOT-23 package only 0.8 V

IENH EN Pin Input High Current V EN = V+, ISL28148 SOT-23 package

only 11.5

1.6 µA

IENL EN Pin Input Low Current V EN = V -, ISL28148 SOT-23 package only 12 25

30 nA

AC SPECIFICATIONS

GBW Gain Bandwidth Product AV = 100, RF = 100kΩ, RG = 1kΩ,

RL = 10kΩ to VCM 4.5 MHz

Unity Gain

Bandwidth -3dB Bandwidth AV =1, RF = 0Ω, VOUT = 10mVP-P,

RL = 10kΩ to VCM 13 MHz

eNInput Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 2 µVPP

Input Noise Voltage Density fO = 1kHz 28 nV/√Hz

iNInput Noise Current Density fO = 1kHz 0.016 pA/√Hz

CMRR @ 60Hz Input Common Mode Rejection Ratio VCM = 1VP-P, RL = 10kΩ to VCM 85 dB

PSRR- @

120Hz Power Supply Rejection Ratio (V-)V

+, V- = ±1.2V and ±2.5V,

VSOURCE = 1VP-P, RL = 10kΩ to VCM -82 dB

PSRR+ @

120Hz Power Supply Rejection Ratio (V+)V

+, V- = ±1.2V and ±2.5V

VSOURCE = 1VP-P, RL = 10kΩ to VCM -100 dB

TRANSIENT RESPONSE

SR Slew Rate ±4V/µs

tr, tf, Large

Signal Rise Time, 10% to 90%, VOUT AV

= +2,

VOUT = 3VP-P, RG = RF = 10kΩ

10kΩ to VCM 530 ns

Fall Time, 90% to 10%, VOUT AV

= +2,

VOUT = 3VP-P, RG = RF = 10kΩ

10kΩ to VCM 530 ns

tr, tf, Small

Signal Rise Time, 10% to 90%, VOUT AV

= +2,

VOUT = 10mVP-P,

RG = RF = R

10kΩ to VCM 50 ns

Fall Time, 90% to 10%, VOUT AV

= +2,

VOUT = 10mVP-P,

RG = RF = R

10kΩ to VCM 50 ns

tEN Enable to Output Turn-on Delay T ime, 10%

EN to 10% VOUT, (ISL28148) EN = 5V to 0V, AV

= +2,

RG = RF = R

= 1

k to VCM 5µs

Enable to Output Turn-of f Delay Time, 10%

EN to 10% VOUT, (ISL28148) VEN = 0V to 5V, AV

= +2,

RG = RF = R

= 1

to VCM 0.2 µs

NOTE:

4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization

and are not production tested.

Electrical Specifications V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified.

Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data

established by characterization. (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN

(Note 4) TYP MAX

(Note 4) UNIT

ISL28148, ISL28248, ISL28448

5FN6337.4

September 21, 2010

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open

FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR

VALUES Rf/RgFIGURE 2. GAIN vs FREQUENCY vs VOUT, RL = 1k

FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 100k

FIGURE 5. GAIN vs FREQUENCY vs RLFIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN

-15

-10

-5

100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

V+ = 5V

RL = 1k

AV = +2

VOUT = 10mVP-P

CL = 16.3pF

Rf = Rg = 100k

Rf = Rg = 1k

Rf = Rg = 10k

NORMALIZED GAIN (dB)

-9

-8

-7

-6

-5

-4

-3

-2

-1

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

VOUT = 100mV

V+ = 5V

RL = 1k

AV = +1

CL = 16.3pF

VOUT = 50mV

VOUT = 10mV

VOUT = 1V

NORMALIZED GAIN (dB)

-9

-8

-7

-6

-5

-4

-3

-2

-1

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

V+ = 5V

RL = 10k

AV = +1

CL = 16.3pF

NORMALIZED GAIN (dB)

VOUT = 100mV

VOUT = 50mV

VOUT = 10mV

VOUT = 1V

-9

-8

-7

-6

-5

-4

-3

-2

-1

NORMALIZED GAIN (dB)

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

V+ = 5V

RL = 100k

AV = +1

CL = 16.3pF

VOUT = 100mV

VOUT = 50mV

VOUT = 10mV

VOUT = 1V

-9

-8

-7

-6

-5

-4

-3

-2

-1

NORMALIZED GAIN (dB)

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

V+ = 5V

VOUT = 10mVP-P

AV = +1

CL = 16.3pF

RL = 100k

RL = 10k

RL = 1k

-10

GAIN (dB)

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

100

AV = 1001

AV = 101

AV = 10

AV = 1

V+ = 5V

VOUT = 10mVP-P

CL = 16.3pF

RL = 10k

AV = 1, Rg = INF, Rf = 0

AV = 10, Rg = 1k, Rf = 9.09k

AV = 101, Rg = 1k, Rf = 100k

AV = 1001, Rg = 1k, Rf = 1M

ISL28148, ISL28248, ISL28448

6FN6337.4

September 21, 2010

FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FIGURE 8. GAIN vs FREQUENCY vs CL

FIGURE 9. CMRR vs FREQUENCY; V+ = 2.4V AND 5V FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±1.2V

FIGURE 11. PSRR vs FREQUENCY V+, V- = ±2.5V FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)

10k 100k 1M 10M 100M

FREQUENCY (Hz)

V+ = 2.4V

V+ = 5V

-9

-8

-7

-6

-5

-4

-3

-2

-1

NORMALIZED GAIN (dB)

RL = 10k

AV = +1

VOUT = 10mVP-P

CL = 16.3pF

-8

-7

-6

-5

-4

-3

-2

-1

10k 100k 1M 10M 100M

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

CL = 51.7pF

CL = 37.7pF

CL = 26.7pF

CL = 16.7pF

CL = 4.7pF

V+ = 5V

RL = 1k

AV = +1

VOUT = 10mVP-P

CL = 43.7pF

-90

-80

-70

-60

-50

-40

-30

-20

-10

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

V+ = 2.4V, 5V

RL = 1k

AV = +1

VCM = 1VP-P

CL = 16.3pF

CMRR (dB)

-120

-100

-80

-60

-40

-20

PSRR (dB)

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

V+, V- = ±1.2V

RL = 1k

AV = +1

VCM = 1VP-P

CL = 16.3pF

PSRR-

PSRR+

-120

-100

-80

-60

-40

-20

PSRR (dB)

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

V+, V- = ±2.5V

RL = 1k

AV = +1

VCM = 1VP-P

CL = 16.3pF

PSRR-

PSRR+

FREQUENCY (Hz)

100

1000

1 10 100 1k 10k 100k

INPUT VOLTAGE NOISE (nV/√Hz)

V+ = 5V

AV = +2

Rf = 1k Rg = 1k

ISL28148, ISL28248, ISL28448

7FN6337.4

September 21, 2010

FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz

FIGURE 15. LARGE SIGNAL STEP RESPONSE FIGURE 16. SMALL SIGNAL STEP RESPONSE

FIGURE 17. ISL28148 ENABLE TO OUTPUT RESPONSE

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)

FREQUENCY (Hz)

0.01

0.1

1 10 100 1k 10k 100k

INPUT CURRENT NOISE (pA/√Hz)

V+ = 5V

AV = +2

Rf = 1k Rg = 1k

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

012345678910

TIME (s)

INPUT NOISE (µV)

V+ = 5V RL = 10k

Rg = 10 AV = 10k

CL = 16.3pF Rf = 100k

-2.0

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

0123456789

TIME (µs)

V+, V- = ±2.5V

RL = 1k

Rg = Rf = 10k

AV = 2

CL = 16.3pF

VOUT = 3VP-P

LARGE SIGNAL (V)

10 0.010

0.015

0.020

0.025

012345678910

TIME (µs)

V+, V- = ±2.5V

RL = 1k

Rg= Rf = 10k

AV = 2

CL = 16.3pF

VOUT = 10mVP-P

SMALL SIGNAL (V)

-0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 102030405060708090100

TIME (µs)

-0.2

0.2

0.4

0.6

0.8

1.0

1.2

V+ = 5V

Rg = Rf = 10k

AV = +2

VOUT = 1VP-P

CL = 16.3pF

VEN VOUT

RL = 10k

VENABLE (V)

OUTPUT (V)

ISL28148, ISL28248, ISL28448

8FN6337.4

September 21, 2010

FIGURE 18. INPUT OFFSET VOL TAGE vs COMMON MODE

INPUT VOLTAGE FIGURE 19. INPUT BIAS CURRENT vs COMMON MODE

INPUT VOLTAGE

FIGURE 20. SUPPL Y CURRENT ENABLED vs TEMPERA TURE

V+, V- = ±2.5V FIGURE 21. SUPPLY CURRENT DISABLED vs

TEMPERATURE V+, V- = ±2.5V

FIGURE 22. VOS vs TEMPERATURE VIN = 0V, V +, V- = ±2.75V FIGURE 23. VOS vs TEMPERATURE VIN = 0V, V +, V- = ±2.5V

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)

-800

-600

-400

-200

200

400

600

800

-10123456

VCM (V)

V+ = 5V

RL = OPEN

AV = +1k

Rf = 100k, Rg = 100

VOS (µV)

-100

-80

-60

-40

-20

100

-10123456

VCM (V)

IBIAS (pA)

V+ = 5V

RL = OPEN

AV = +1k

= 100k, R

= 100

0.6

0.7

0.8

0.9

1.0

1.1

1.2

-40-200 20406080100120

TEMPERATURE (°C)

CURRENT (mA)

MAX

MEDIAN

MIN

3.5

4.5

5.5

6.5

7.5

8.5

9.5

10.5

-40-200 20406080100120

TEMPERATURE (°C)

CURRENT (µA)

MAX

MEDIAN

MIN

-2.0

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

VOS (mV)

MEDIAN

MIN

MAX

-40-200 20406080100120

TEMPERATURE (°C)

MEDIAN

MIN

MAX

-2.0

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

VOS (mV)

-40-200 20406080100120

TEMPERATURE (°C)

ISL28148, ISL28248, ISL28448

9FN6337.4

September 21, 2010

FIGURE 24. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±1.2V FIGURE 25. IBIAS- vs TEMPERATURE V+, V- = ±2.5V

FIGURE 26. IBIAS- vs TEMPERATURE V+, V- = ±1.2V FIGURE 27. IOS vs TEMPERATURE V+, V- = ±2.5V

FIGURE 28. IOS vs TEMPERATURE V+, V- = ±1.2V FIGURE 29. A VOL vs TEMPERA TURE RL = 100k, V+, V- = ±2.5V ,

VO = -2V TO +2V

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)

MEDIAN

MIN

MAX

-2.0

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

VOS (mV)

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

-50

100

150

200

250

300

IBIAS- (pA)

-40-200 20406080100120

TEMPERATURE (°C)

MAX

MEDIAN

MIN

-50

100

150

200

250

IBIAS- (pA)

MAX

MEDIAN

MIN

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

-70

-60

-50

-40

-30

-20

-10

IOS (pA)

-40-200 20406080100120

TEMPERATURE (°C)

MAX

MEDIAN

MIN

-60

-50

-40

-30

-20

-10

IOS (pA)

-40-200 20406080100120

TEMPERATURE (°C)

MAX

MEDIAN

MIN

150

350

550

750

950

1150

1350

1550

1750

AVOL (V/m V )

MAX

MEDIAN

MIN

-40-200 20406080100120

TEMPERATURE (°C)

ISL28148, ISL28248, ISL28448

10 FN6337.4

September 21, 2010

FIGURE 30. A VOL vs TEMPERATURE RL = 1k, V+, V- = ±2.5V,

VO = -2V TO +2V FIGURE 31. CMRR vs TEMPERA TURE VCM = -2.5V T O +2.5V,

V+, V- = ±2.5V

FIGURE 32. PSRR vs TEMPERATURE V+, V- = ±1.2V TO ±2.75V FIGURE 33. VOUT HIGH vs TEMPERATURE RL = 1k,

V+, V- = ±2.5V

FIGURE 34. VOUT HIGH vs TEMPERA TURE RL = 100k,

V+, V- =±2.5V FIGURE 35. VOUT LOW vs TEMPERATURE RL = 1k,

V+, V- = ±2.5V

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)

MAX

MIN

MEDIAN

AVOL (V/m V )

-40-200 20406080100120

TEMPERATURE (°C) -40-200 20406080100120

TEMPERATURE (°C)

100

110

120

130

140

CMRR (dB)

MAX

MEDIAN

MIN

100

110

120

130

140

PSRR (dB)

MAX

MEDIAN

MIN

-40-200 20406080100120

TEMPERATURE (°C)

4.940

4.945

4.950

4.955

4.960

4.965

4.970

VOUT (V)

MAX

MEDIAN

MIN

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

4.9982

4.9984

4.9986

4.9988

4.9990

4.9992

4.9994

VOUT (V)

MAX

MEDIAN

MIN

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

VOUT (mV)

MAX

MEDIAN

MIN

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

ISL28148, ISL28248, ISL28448

11 FN6337.4

September 21, 2010

FIGURE 36. VOUT LOW vs TEMPERA TURE RL = 100k,

V+, V- = ±2.5V FIGURE 37. + OUTPUT SHORT CIRCUIT CURRENT vs

TEMPERATURE VIN = 2.55V, RL = 10,

V+, V- = ±2.5V

FIGURE 38. - OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE VIN = -2.55V, RL = 10, V+, V- = ±2.5V

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)

1.5

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

VOUT (mV)

MAX

MEDIAN

MIN

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

+ OUTPUT SHORT CIRCUIT

MEDIAN

MIN

MAX

-40-200 20406080100120

TEMPERATURE (°C)

CURRENT (mA)

-85

-80

-75

-70

-65

-60

-55

-50

MEDIAN

MIN

MAX

- OUTPUT SHORT CIRCUIT

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

MEDIAN

MIN

MAX

CURRENT (mA)

Pin Descriptions

ISL28148

(6 Ld SOT-23)

ISL28248

(8 Ld SO)

(8 Ld MSOP) ISL28448

(14 Ld TSSOP) PIN NAME FUNCTION EQUIVALENT CIRCUIT

42 (A)

6 (B) 2 (A)

6 (B)

9 (C)

13 (D)

IN-

IN-_A

IN-_B

IN-_C

IN-_D

inverting input

Circuit 1

33 (A)

5 (B) 3 (A)

5 (B)

10 (C)

12 (D)

IN+

IN+_A

IN+_B

IN+_C

IN+_D

Non-inverting input (See circuit 1)

IN-

V+

V-

IN+

ISL28148, ISL28248, ISL28448

12 FN6337.4

September 21, 2010

Applications Information

Introduction

The ISL28148, ISL28248 and ISL28448 are single, dual and

quad channel CMOS rail-to-rail input, output (RRIO)

micropower precision operational amplifiers. The parts are

designed to operate from single supply (2.4V to 5.5V) or dual

supply (±1.2V to ±2.7 5V). The parts have an input common

mode range that extends 0.25V above the positive rail and

100mV below the negative supply rail. The output can swing

within about 3mV of the supply rails with a 100kΩ load.

Rail-to-Rail Input

Many rail-to-rail input stages use two differential input pairs,

a long-tail PNP (or PFET) and an NPN (or NFET). Severe

penalties have to be paid for this circuit topology. As the

input signal moves from one supply rail to another, the

operational amplifier switches from one input pair to the

other causing drastic changes in input offset voltage and an

undesired change in magnitude and polarity of input offset

current.

The parts achieve input rail-to-rail operation without

sacrificing important precision specifications and degrading

distortion performance. The devices’ input offset voltage

exhibits a smooth behavior throughout the entire

common-mode input range. The input bi as current vs the

common-mode voltage range gives us an undistorted

behavior from typically 100mV below th e negative rail and

0.25V higher than the V+ rail.

Rail-to-Rail Output

A pair of complement ary MOS devi ces are used to achieve

the rail-to-rail output swing. The NMOS sinks current to swing

the output in the negative direction. The PMOS so urces

current to swing the output in the positive direction. The

devices’ with a 100kΩ load wil l swing to wi th in 3mV of the

positive supply rail and within 3mV of the ne gative supply rai l.

Results of Overdriving the Output

Caution should be used when overdriving the output for long

periods of time. Overdriving the output can occur in two ways:

1. The input voltage times the gain of the amplifier exceeds the

supply voltage by a large value or

2. The output current required is higher than the output stage

can deliver. These conditions can result in a shift in the Input

Offset V oltage (VOS) as much as 1µV/hr . of exposure under

these condition.

IN+ and IN- Input Protection

All input terminals have internal ESD protection diodes to both

positive and negative supply rails, limiting the inpu t voltage to

within one diode beyo nd the suppl y rails. They also contain

back-to-back diodes across the input terminals (“Pin

Desc riptions” table - Circuit 1 on page 11). For applications

where the input di f ferentia l vo lt age is expected to excee d

2 4 11 V- Negative supply

Circuit 2

11 (A)

7 (B) 1 (A)

7 (B)

8 (C)

14 (D)

OUT

OUT_A

OUT_B

OUT_C

OUT_D

Output

Circuit 3

6 8 4 V+ Positive supply (See circuit 2)

EN Chip enable

Circuit 4

Pin Descriptions (Continued)

ISL28148

(6 Ld SOT-23)

ISL28248

(8 Ld SO)

(8 Ld MSOP) ISL28448

(14 Ld TSSOP) PIN NAME FUNCTION EQUIVALENT CIRCUIT

V+

V-

CAPACITIVELY

COUPLED

ESD CLAMP

V-

OUT

V-

ISL28148, ISL28248, ISL28448

13 FN6337.4

September 21, 2010

0.5V, an external series resisto r must be use d to ensure th e

input currents never exceed 5 mA (Figure 39).

Enable/Disable Feature

The ISL28148 offers an EN pin that disables the device

when pulled up to at least 2.0V. In the disabled state (output

in a high impedance state), the part consumes typically 10µA

at room temperature. By disabling the part, multiple

ISL28148 parts can be connected together as a MUX. In this

configuration, the outputs are tied together in parallel and a

channel can be selected by the EN pin. The loading effects

of the feedback resistors of the disabled amplifier must be

considered when multiple amplifier outputs are connected

together. Note that feed-through from the IN+ to IN- pins

occurs on any Mux Amp disabled channel where the input

differential voltage exceeds 0.5V (e.g., active channel

VOUT = 1V, while disabled channel VIN = GND), so the mux

implementation is best suited for small signal applications. If

large signals are required, use series IN+ resistors, or large

value RF, to keep the feed-through current low enough to

minimize the impact on the active channel. See “Limitations

of the Differential Input Protection” on page 13 for more

details.The EN pin also has an internal pull-down. If left

open, the EN pin will pul l to the negative rail and the device

will be enabled by default. When not used, the EN pin should

either be left floating or connected directly to the V- pin.

Limitations of the Differential Input Protection

If the input differential voltage is expected to exceed 0.5V, an

external current limiting resistor must be used to ensure the

input current never exceeds 5mA. For non-inverting unity gain

applications the current limiting can be via a series IN+ resistor ,

or via a feedback resistor of appropriate value. For other gain

configurations, the series IN+ resistor is the best choice, unless

the feedback (RF) and gain setting (RG) resistors are both

sufficiently large to limit the input current to 5mA.

Large differential input voltages can arise from several

sources:

• During open loop (comparator) operation. Used this way,

the IN+ and IN- voltages don’t track, so differentials arise.

• When the amplifier is disabled but an inpu t signal is still

present. An RL or RG to GND keeps the IN- at GND, while

the varying IN+ signal creates a differential voltage. Mux

Amp applications are similar, except th at the active

channel VOUT determi nes the voltage on the IN- terminal.

• When the slew rate of the input pulse is considerably

faster than the op amp’s slew rate. If the VOUT can’t keep

up with the IN+ signal, a differential voltage results, and

visible distortion occurs on the input and output signals. To

avoid this issue, keep the input slew rate below 4.8V/µs, or

use appropriate current limiting resistors.

Large (>2V) differential input voltages can also cause an

increase in disabled ICC.

Using Only One Channel

If the application does not use all channels, then the user

must configure the unused channel(s) to prevent them from

oscillating. The unused chann el(s) will oscillate if the input

and output pins are floating. This will result in higher than

expected supply currents and possible noise injection in to

the channel being used. The proper way to prevent this

oscillation is to short the output to the negative input and

ground the positive input (as shown in Figure 40).

Proper Layout Maximizes Performance

To achieve the maximum performance of the high input

impedance and low offset voltage, care should be taken in

the circuit board layout. The PC board surface must remain

clean and free of moisture to avoid leakage currents

between adjacent traces. Surface coating of the circuit board

will reduce surface moisture and provide a humidity barrier,

reducing parasitic resistance on the board. When input

leakage current is a concern, the use of guard rings around

the amplifier inputs will further reduce leakage currents.

Figure 41 shows a guard ring example for a unity gain

amplifier that uses the low impedance amplifier output at the

same voltage as the high impedance input to eliminate

surface leakage. The guard ring does not need to be a

specific width, but it should form a continuous loop around

both inputs. For further reduction of leakage currents,

components can be mounted to the PC board using Teflon

standoff insulators.

Current Limiting

These devices have no internal current-limiting circuitry. If

the output is shorted, it is possible to exceed the Absolute

Maximum Rating for output current or power dissipation,

potentially resulting in the destruction of the device.

FIGURE 39. INPUT CURRENT LIMITING

RIN RL

VIN VOUT

FIGURE 40. PREVENTING OSCILLA TIONS IN UNUSED

CHANNELS

V+

FIGURE 41. GUARD RING EXAMPLE FOR UNITY GAIN

AMPLIFIER

HIGH IMPEDANCE INPUT

ISL28148, ISL28248, ISL28448

14 FN6337.4

September 21, 2010

Power Dissipation

It is possible to exceed the +150°C maximum junction

temperatures under certain load and power-supply

conditions. It is therefore important to calculate the

maximum junction temperature (TJMAX) for all applications

to determine if power supply voltages, load conditions, or

package type need to be modified to remain in the safe

operating area. These parameters are related in Equation 1:

where:

•P

DMAXTOTAL is the sum of the maximu m power

dissipation of each amplifier in the package (PDMAX)

•PD

MAX for each amplifier can be calculated as shown in

Equation 2:

where:

•T

MAX = Maximum ambient temperature

•θJA = Thermal resistance of the package

•PD

MAX = Maximum power dissipation of 1 amplifier

•V

S = Supply voltage (Magnitude of V + and V-)

•I

MAX = Maximum supply current of 1 amplifier

•V

OUTMAX = Maximum output voltage swing of the

application

•R

L = Load resistance

TJMAX TMAX θJAxPDMAXTOTAL

()+= (EQ. 1)

PDMAX 2*VSISMAX VS

( - VOUTMAX)VOUTMAX

----------------------------

×+×=(EQ. 2)

ISL28148, ISL28248, ISL28448

15 FN6337.4

September 21, 2010

ISL28148, ISL28248, ISL28448

Package Outline Drawing

P6.064A

6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE

Rev 0, 2/10

1.60

0.08-0.20

SEE DETAIL X

(0.60)

0-3°

3 5

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW END VIEW

INDEX AREA

PIN 1

SEATING PLANE GAUGE

0.45±0.1

(2 PLCS)

10° TYP

1.90

0.40 ±0.05

2.90

0.95

2.80

0.05-0.15

1.14 ±0.15

0.20 CA-B DM

(1.20)

(0.60)

(0.95)

(2.40)

0.10 C

1.45 MAX

0.20 C

(1.90)

0.15 C

2x D

0.15 C

2x A-B

(0.25)

PLANE

Dimension is exclusive of mold flash, prot rusions or gate burrs.

This dimension is measured at Datum “H”.

Package conforms to JEDEC MO-178AA.

Foot length is measured at reference to guage plane.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to ASME Y14.5M-1994.

Dimensions are in mill imeters.1.

NOTES:

16 FN6337.4

September 21, 2010

ISL28148, ISL28248, ISL28448

Package Outline Drawing

M8.15E

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 08/09

Unless otherwise specified, tolerance : Decimal ± 0.05

The pin #1 identifier may be either a mold or mark feature.

Interlead flash or protrusions shall not exceed 0.25mm per side.

Dimension does not include interlead flash or protrusions.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Dimensions are in millimeters.1.

NOTES:

DETAIL "A"

SIDE VIEW “A

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

0.25 AMC B

0.10 C

ID MARK

PIN NO.1

(0.35) x 45°

SEATING PLANE

GAUGE PLANE

0.25

(5.40)

(1.50)

4.90 ± 0.10

3.90 ± 0.10

1.27 0.43 ± 0.076

0.63 ±0.23

4° ± 4°

DETAIL "A" 0.22 ± 0.03

0.175 ± 0.075

1.45 ± 0.1

1.75 MAX

(1.27) (0.60)

6.0 ± 0.20

Reference to JEDEC MS-012.

SIDE VIEW “B”

17 FN6337.4

September 21, 2010

ISL28148, ISL28248, ISL28448

Package Outline Drawing

M8.118A

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)

Rev 0, 9/09

Plastic or metal protrusions of 0.15mm max per side are not

Dimensions “D” and “E1” are measured at Datum Plane “H”.

This replaces existing drawing # MDP0043 MSOP 8L.

Plastic interlead protrusions of 0.25mm max per side are not

Dimensioning and tolerancing conform to JEDEC MO-187-AA

Dimensions are in millimeters.1.

NOTES:

DETAIL "X"

SIDE VIEW 1

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

SIDE VIEW 2

included.

GAUGE

PLANE

3°±3°

0.25 CAB

0.10 C

0.08 CAB

0.25

0.55 ± 0.15

0.95 BSC

0.18 ± 0.05

1.10 Max

4.40

3.00

5.80

0.65

3.0±0.1 4.9±0.15

1.40

0.40

0.65 BSC

PIN# 1 ID

DETAIL "X"

0.33 +0.07/ -0.08 0.10 ± 0.05

3.0±0.1

0.86±0.09

SEATING PLANE

and AMSE Y14.5m-1994.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6337.4

September 21, 2010

ISL28148, ISL28248, ISL28448

Thin Shrink Small Outline Plastic Packages (TSSOP)

INDEX

AREA E1

123

-B-

0.10(0.004) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

E0.25(0.010) BM M

0.25

0.010

GAUGE

PLANE

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

0.05(0.002)

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.041 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.6 5 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

α0o8o0o8o-

Rev. 2 4/06