MOTOROLA SEMICONDUCTOR TECHNICAL DATA 32K x 8 Bit Fast Static RAM The MCM6206C is fabricated using Motorolas high-performance silicon-gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is avail- able in plastic dual-inline and plastic smatloutline J-leaded packages. MCM6206C P PACKAGE 300 MIL PLASTIC e Single 5 V + 10% Power Supply CASE 710B-01 Fully Static No Clock or Timing Strobes Necessary e Fast Access Times: 15, 17, 20, 25 and 35 ns e Equal Address and Chip Enable Access Times J PACKAGE Output Enable (G) Feature for Increased System Flexibility and to 300 MIL SOJ Eliminate Bus Contention Problems CASE 810B-03 * Low Power Operation: 135 165 mA Maximum AC Fully TTL Compatible Three State Output 0 PIN ASSIGNMENT BLOCK DIAGRAM wW AM te 81 Voc GS Aw 02 a7 W At ON a7 3 26 1] A13 asa_ > cO Q as 1 4 25 [] as 5 24 ca KT ww or N 6 23 ns A4 Ait A6 I= ROW A un a3 (]7 2G a7P J dECO0 RR ' MN a2 [8 211] ato ~wp O ai]? ale ao {] 10 191] pov _ => poo (] 1 181] pas Ai a oar {] 2 171) pas | | paz [ 13 16 0 pos 14 15 Deo : i? INPUT 3 COLUMN 1/0 Vss q fH pa3 DATA [J bar P21] contro. COLUMN DECODER RERRARE PIN NAMES _ AO-A14 oo. eee eee Address input E AQ AZ AB AIO A12 AI3 AI4 DQ0 - DQ? ... Data Input/Data Output ; rn Write Enable w_| : [Ce Output Enable a Bice cece een eee eee Chip Enable VCC .-ee eee . . Power Supply (+ 5 V) NGG voce eee cece eee ees Ground MOTOROLA FAST SRAM MCM6206C Qu41kTRUTH TABLE (xX = Dont Care) EIG|W Mode Vec Current Output Cycle H x x Not Selected Isp1. Ispe High-Z - L H H | Output Disabled ICCA High-Z - L L H Read loca Dout Read Cycle L xX L Write loca High-Z Write Cycle ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit This device contains circuitry to protect the | inputs against damage due to high static volt- Power Supply Voltage Voc -05to+7.0 Vv ages or electric fields; however, it is advised Voltage Relative to Vgg For Any Pin Vins Vout |-0.5toVec+0.5| V that normal precautions be taken to avoid Except Voc application of any voltage higher than maxi- mum rated voltages to this high-impedance Output Current lout +20 mA circuit. Tal at This CMOS memory circuit has been de- Power Dissipation PD 1.0 w signed to meet the dc and ac specifications Temperature Under Bias Thias - 10 to + 85 ae) shown in the tables, after thermal equilibrium 0 ing Te T 0to+70 C has been established. The circuit is in a test perating Temperature A OF socket or mounted on a printed circuit board Storage TemperaturePlastic Tstg 55 to + 125 c and transverse air flow of at least 500 linear NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are feet per minute is maintained. exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for ex- tended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V 10%, Ta = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) Voc 45 5.0 5.5 Vv Input High Voltage VIH 2.2 _- Voc + 0.3** V Input Low Voltage VIL -0.5* _ 0.8 Vv *VIL (min) = 0.5 V de; Vi_ (min) = 2.0 V ac (pulse width < 20 ns) Vin (max) = Voc + 0.3 V de; Viq (max) = Voc + 2.0 V ac (pulse width < 20 ns) DC CHARACTERISTICS Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to Voc) kg (W) _ +1 pA Output Leakage Current (E = Viq or G = ViH, Vout = 0 to Voc) ikg(O) ~ +1 pA Output High Voltage (lIoH = 4.0 mA) VOH 2.4 _ v Output Low Voltage (lo_ = 8.0 mA) VoL - 0.4 Vv POWER SUPPLY CURRENTS Parameter Symbol! -15 | -17 | +20 | -25 | -35 Unit AC Active Supply Current (lout = 0 mA, VCC = Max, f = fmax) ICCA 165 155 150 140 135 mA AC Standby Current (E = VjH, Voc = Max, f= fmax) Ispi 50 45 45 40 40 mA CMOS Standby Current (Voc = Max, f= 0 MHz, E2Voc-0.2V Isp2 20 20 20 20 20 mA Vin Vgg + 0.2 V, or 2 Voc - 0.2 V) CAPACITANCE (f = 1 MHz, dV =3 V, Ta = 25C, Periodically sampled rather than 100% tested) Characteristic Symboi Max Unit Address Input Capacitance Cin 6 ; pF Control Pin Input Capacitance (E, G, W) Cin 8 pF VO Capacitance Cyo | 8 pF MCM6206C MOTOROLA FAST SRAM 3-16nme-lUl AC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to + 70C, Unless Otherwise Noted) Input Timing Measurement Reference Lavel............... 1.5V Output Timing Measurement Reference Level ............. 1.5V Input Pulse Levels .......... 000... cece eee e ee ene 0t03.0V Output Load ................ Figure 1A Unless Otherwise Noted Input Rise/Fall Time ........ 0... cece cece enn e neces 5ns READ CYCLE (See Note 1) -15 -17 -20 -25 -35 Parameter Symbol | Min | Max | Min | Max | Min | Max | Min | Max ! Min | Max | Unit | Notes Read Cycle Time tavav 7 15 | | 17 | |] 20 | | 2 | | 35 | | ns 2 Address Access Time tavav | | 15 | |] 17 | | 20 | | 25 | | 35 | ns Enable Access Time terav | | 15 | | 17 | | 20 | | 25 | | 35 | ns 3 Output Enable Access Time teLav | 8 _ 9 | 10 | | 12 | | 15 | ns Output Hold from Address Change taxax 4 ad 4 - 4 _- 4 _ 4 | ns | 45.6 Enable Low to Output Active teLax 4 - 4 _ 4 - 4 - 4 | ns | 45,6 Enable High to Output High-Z ttHaz | 9 | 8 | Of 8B} of] 9 | co fh io | co [lh | ns | 456 Output Enable Low to Output Active tGLax 0 _ 0 ~ 0 _- 0 _ 0 | ns | 45,6 Output Enable High to Output High-Z iGHaZ 0 7 0 8 0 8 0 10 0 ab ns | 4,5,6 Power Up Time teiccH} 09 } ~ | Oo [}] o07]{]o]]0 ] | ns Power Down Time teHiccL} | 15 | | 17 | | 20 | |] 25 | | 35 | ns NOTES: _ . Wis high for read cyclo. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, teHqz (max) is less than teLQx (min), and IGHQz (max) is less than tgLQx (min), both for a given device and from devica to device. NON AC TEST LOADS Figure 1A OUTPUT # 2552 3 +5V 480 Q 5 pF Figure 1B Transition Is measured +500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. Device is continuously selected (E = Vi_, G = Vj). TIMING LIMITS The table of timing values shows either a minimum or a maximum limit for each param- eter. Input requirements are specified from the extemal system point of view. Thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never pro- vides data later than that time. MOTOROLA FAST SRAM MCM6206C aa?READ CYCLE 1 (See Note 7) taVAV A(ADDRESS} x jt laxay x Q (DATA OUT) PREVIOUS DATA VALID DATA VALID fue tavaV >| READ CYCLE 2 (See Note 3) En ; = x A (ADDRESS) c y tavav = \* tetev E (CHIP ENABLE) K teHaz >| TN I teLax [nem G (OUTPUT ENABLE) \ teLav taHoz-*| z pe fatax { ) IGH Z Q (DATA OUT) HIGH DATA VALID }_HIGHZ L_ t teLiCcH "I EHICCL oo -cscreee Voc SUPPLY CURRENT Isp MCM6206C a 446 MOTOROLA FAST SRAMWRITE CYCLE 1 (W Controlled, See Notes 1 and 2) -15 -7 -20 -25 -35 Parameter Symbol | Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | Unit | Notes Write Cycle Time tavav 15 | 17 | | 20); }] 2] |] 35 | ns 3 Address Setup Time tAVWL 0 _ 0 _ a _ 0 _ 0 _ ns Address Valid to End of Write tavwH | 12 | 147) 15 | | 20 | | 30] ns Write Pulse Width twewH, | 12 | 445 - 15 | | 20 | | 30 | ns tWLEH Write Pulse Width, twowH, | 10 | | 11 ;, 127 ] 15 | | 20 | [ ns 4 G High WLEH Data Valid to End of Write tovwH 7 8 _ 8 7,10) |] 12) ~ | ns Data Hold Time twHpx |} 9 | | O09 |}]of}]]o0f]-]o] | ns Write Low to Output High-Z tWLaz 0 7 0 8 0 8 0 10 0 11 ns | 5,6,7 Write High to Output Active twHax | 4 [ 4) 4 ], 4)/}]4 ] |] ns | 567 Write Recovery Time twHax | 9 | | Of ~ | o f]o]]o0] Ins NOTES: . Awrite occurs during the overlap of E low and W tow. . If G goes low coincident with or after W goes low, the output will remain in a high impedance state. . All timings are referenced from the last valid address to the first transitioning address. . If G > Vyy, the output will remain in a high impedance state. At any given voltage and temperature, twLqz (max) is less than tywHQx (min), bath for a given device and from device to device. . Transition is measured +500 mV from steady-state voltage with load of Figure 1B. . This parameter is sampled and not 100% tested. = NOORWN WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) r $< tv A A (ADDRESS) * x tavWH tWHAX E (CHIP ENABLE) \ t 'WLWH [* _ WLEH W (WRITE ENABLE) x x * tavwe. > pywH * tWHDX D (DATAIN) DATAVALIO XXX twLaz + bemt- tWHax HIGH Z HIGH Z Q (DATA OUT) MOTOROLA FAST SRAM MCM6206C nanWRITE CYCLE 2 (E Controlled, See Note 1) -15 -17 -20 - 25 -35 Parameter Symbol | Min | Max | Min | Max | Min | Max | Min | Max | Min | Max Unit | Notes Write Cycle Time tavav | 15 | | 177 | 20] | 28] | 95] | 4s Address Setup Time taVEL 0 _ 0 - 0 - 0 0 | ns Address Valid to End of Write taVEH w2|/ |i14],] 15 | | 201 7] 25 | {1 ns Enable to End of Write teteH. | 10 | | 11 j},12]/ ]15 | | 2 | ] As 3,4 tELWH Data Valid to End of Write tovey | 7 /[ 8 |] ] 8 | |] 10] | 114 | ns Data Hold Time tEHDX 0 _ 0 _ 0 _ 0 _ 0 | ns Write Recovery Time tEHAX 0 _ 0 _ 0 - Q _ 0 _ ns NOTES: _ _ 1. Awrite occurs during the overlap of E low and W low. 2. All timings are referenced from the last valid address to the first transitioning address. 3. If E goes low coincident with or after Ww goes low, the output will remain in a high impedance state. 4. 1f E goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controlled, See Note 1) tAVAV A (ADDRESS) 4 a tAVEH E (CHIP ENABLE) / ' teLEH AVEL T teLWH TEHAX le WLEH W (WRITE ENABLE) # (WR ) \ if tpvEH > tEHDX D (DATA IN) DATA VALID Q (DATA OUT} HIGHZ ORDERING INFORMATION (Order by Full Part Number) ue 2 X XX Motorola Memory Prefix Le Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (P = 300 mil Plastic DIP, J = 300 mil SOJ) Full Part Numbers MCM6206CP15 MCM6206CJ15 MCM6206CJ15R2 MCM6206CP17 MCM6206CJ17 MCM6206CJ17R2 MCM6206CP20 MCM6206CJ20 MCM6206CJ20R2 MCM6206CP25 MCM6206CJ25 MCM6206CJ25R2 MCM6206CP35 MCM6206CJ35 MCM6z206C/95R2 MCM6206C MOTOROLA FAST SRAM