74LVC06A
Document number: DS35259 Rev. 3 - 2 1 of 10
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74LVC07
A
HEX BUFFERS WITH OPEN DRAIN OUTPUTS
Description
The 74LVC07A provides six independent open-drain buffers. The
device is designed for operation with a power supply range of 1.65V
to 5.5V. The inputs are tolerant to 5.5V allowing this device to be
used in a mixed voltage environment. The device is fully specified for
partial power down applications using IOFF. The IOFF circuitry
disables the output preventing damaging current backflow when the
device is powered down. The outputs can be connected to imple ment
active-low wired-OR or active-high wired-AND functions.
The gates perform the positive Boolean function:
AY =
Features
• Wide Supply Voltage Range from 1.65V to 5.5V
• Sinks 24mA at VCC = 3.3V
• CMOS low power consumption
• IOFF Supports Partial-Power-Down Mode Operation
• Inputs or outputs accept up to 5.5V
• Inputs can be driven by 3.3V or 5.5V allowing for voltage
translation applications.
• ESD Protection Exceeds JESD 22
200-V Machine Model (A115-A)
2000-V Human Body Model (A114-A)
Exceeds 1000-V Charged Device Model (C101C)
• Latch-Up Exceeds 250 mA per JESD 78, Class II
• Range of Package Options SO-14 and TSSOP-14
• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
• Halogen and Antimony Free. “Green” Device (Note 3)
Pin Assignments
Applications
• Voltage Level Shifting
• General Purpose Logic
• Power Down Signal Isolation
• Wide array of products such as:
PCs, networking, notebooks, ultrabooks, netbooks
Computer peripherals, hard drives, CD/DVD ROM
TV, DVD, DVR, set top box
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com for more information about Diodes In corpor ated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
74LVC06A
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74LVC07
A
Pin Descriptions
Pin Number Pin Name Description
1 1A Data Input
2 1Y Data Output
3 2A Data Input
4 2Y Data Output
5 3A Data Input
6 3Y Data Output
7 GND Ground
8 4Y Data Output
9 4A Data Input
10 5Y Data Output
11 5A Data Input
12 6Y Data Output
13 6A Data Input
14 VCC Supply Voltage
Logic Diagram
1
1A
3
2A
5
3A
9
4A
11
5A
13
6A
21Y
42Y
63Y
84Y
10 5Y
12 6Y
Function Table
Inputs Outputs
A Y
L L
H Z
74LVC06A
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74LVC07
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Absolute Maximum Ratings (Note 4) (@TA = +25°C, unless otherwise specified.)
Symbol Description Rating Unit
ESD HBM Human Body Model ESD Protection 2 KV
ESD CDM Charged Device Model ESD Protection 1 KV
ESD MM Machine Model ESD Protection 200 V
VCC Supply Voltage Range -0.5 to +6.5 V
VI Input Voltage Range -0.5 to +6.5 V
VO Voltage applied to output in high impedance or IOFF state -0.5 to +6.5 V
VO Voltage applied to output in high or low state -0.3 to VCC +0.5 V
IIK Input Clamp Current VI < 0 -50 mA
IOK Output Clamp Current VO < 0 -50 mA
IO Continuous output current 50 mA
Continuous current through Vdd or GND ±100 mA
TJ Operating Junction Temperature -40 to +150 °C
TSTG Storage Temperature -65 to +150 °C
PTOT Total Power Dissipation 500 mW
Note: 4. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device operation should
be within recommend values.
Recommended Operating Conditions (Note 5) (@TA = +25°C, unless otherwise specified.)
Symbol Parameter Conditions Min Max Unit
VCC Supply Voltage 1.65 5.5 V
VI Input Voltage 0 5.5 V
VO Output Voltage Active Mode 0 VCC V
VCC = 0V; Power Down Mode 0 5.5 V
Δt/ΔV Input transition rise or fall rate VCC = 1.65V to 2.7V 20
ns/V
VCC = 2.7V to 5.5V 10
TA Operating free-air temperature -40 +125 ºC
Notes: 5. Unused inputs should be held at VCC or Ground.
74LVC06A
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Electrical Characteristics (@TA = +25°C, unless otherwise specified.)
Symbol Parameter Test Conditions VCC TA = -40°C to +85°C TA = -40°C to +125°C Unit
Min Max Min Max
VIH High-level Input
Voltage
1.65V to 1.95V 0.65 X VCC 0.65 X VCC
V
2.3V to 2.7V 1.7 1.6
2.7V to 3.6V 2.0 2.0
4.5V to 5.5V 0.7 X VCC 2.0
VIL Low-level input
voltage
1.65V to 1.95V 0.35 X VCC 0.35 X VCC
V
2.3V to 2.7V 0.7 0.7
2.7V to 3.6V 0.8 0.8
4.5V to 5.5V 0.3 X VCC 0.3 X VCC
VOL Low-level Output
Voltage
IOL = 100μA 1.65V to 5.5V 0.2 0.3
V
IOL = 4mA 1.65V 0.45 0.6
IOL = 8mA 2.3V 0.70 0.85
IOL = 12mA 2.7V 0.40 0.6
3.0V 0.55 0.6
IOL = 24mA 3.0V 0.55 0.6
IOL= 32mA 4.5V 0.55 0.6
II Input Current VI = GND to 5.5V 3.6V ± 5 ± 20 μA
IOZ Z State Leakage
Current VO = GND or
5.5V 3.6V ±10 ±20 μA
IOFF Power Down
Leakage Current VI or VO = 0V to
3.6V 0 10 20 μA
ICC Supply Current VI = GND or VCC
IO = 0 3.6V 10
40 μA
74LVC06A
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74LVC07
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Switching Characteristics
Symbol Parameter Test
Conditions VCC TA = +25°C -40°C to +85°C -40°C to +125°C Unit
Min Typ Max Min Max Min Max
tPLZ /tPZL Propagation
Delay AN to YN Figure 1
1.65V to1.95V 0.3 2.9 5.7 0.3 5.8 0.3 7.6
ns
2.3V to 2.7V 0.3 2.6 4.1 0.3 4.7 0.3 5.5
2.7V 0.3 2.5 4.0 0.3 4.5 0.3 5.0
3V to 3.6V 0.3 2.3 3.5 0.3 3.7 0.3 5.0
4.5V to 5.5V 0.3 1.7 3.2 0.3 3.4 0.3 4.5
Operating Characteristics (@TA = +25°C, unless otherwise specified.)
Parameter Test
Conditions VCC = 1.8V VCC = 2.5V VCC = 3.3V VCC = 5V Unit
Typ Typ Typ Typ
Cpd Power dissipation
capacitance per gate f = 10 MHz 7.0 7.5 8.0 8.6 pF
CI Input Capacitance VI = VCC – or
GND 4 4 4 4 pF
Package Characteristics
Symbol Parameter Test Conditions VCC Min Typ Max Unit
θJA Thermal Resistance
Junction-to-Ambient SO-14 (Note 6) TBD °C/W
TSSOP-14 159
θJC Thermal Resistance
Junction-to-Case SO-14 (Note 6) TBD °C/W
TSSOP-14 25
Note: 6. Test condition for SO-14 and TSSOP-14: Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout.
74LVC06A
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74LVC07
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Parameter Measuement Information
VCC Inputs VM V
LOAD C
L R
L V∆
VI t
r/tf
1.8V±0.15V VCC ≤2ns VCC/2 2 X VCC 30pF 1KΩ 0.15V
2.5V±0.2V VCC ≤2ns VCC/2 2 X VCC 30pF 500Ω 0.15V
2.7V 2.7V ≤2ns 1.5V 6V 50pF 500Ω 0.3V
3.3V±0.3V 3V ≤2.5ns 1.5V 6V 50pF 500Ω 0.3V
5V±0.5V VCC ≤2.5ns VCC/2 2 X VCC 50pF 500Ω 0.3V
Voltage Waveform
Pulse Duration
Voltage Waveform
Propagation Delay Times
Notes: A. Includes test lead and test apparatus capacitance.
B. All pulses are supplied at pulse repetition rate ≤ 10 MHz
C. The inputs are measured one at a time with one transition per measurement.
D. tPZL is measured at VM.
E. tPLZ is measured at VOL + V∆
Figure 1. Load Circuit and Voltage Waveforms
TEST Condition
tPLZ (see Note E)
tPZL(see Note D) VLOAD
VLOAD
74LVC06A
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74LVC07
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Ordering Information
Part Number Package
Code Packaging
(Note 7) 13” Tape and Reel
Quantity Part Number Suffix
74LVC07AS14-13 S14 SO-14 2500/Tape & Reel -13
74LVC07AT14-13 T14 TSSOP-14 2500/Tape & Reel -13
Notes: 7. The taping orientation and tape details can be found at http://www.diodes.com/datasheets/ap02007.pdf
Marking Information
(1) SO-14, TSSOP-14
Part Number Package
74LVC07AS14 SO-14
74LVC07AT14 TSSOP-14
74LVC06A
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Package Outline Dimensions (All dimensions in mm.)
Package Type: SO-14
Package Type: TSSOP-14
SO-14
Dim Min Max
A 1.47 1.73
A1 0.10 0.25
A2 1.45 Typ
B 0.33 0.51
D 8.53 8.74
E 3.80 3.99
e 1.27 Typ
H 5.80 6.20
L 0.38 1.27
θ 0° 8°
All Dimensions in mm
TSSOP-14
Dim Min Max
a1 7° (4X)
a2 0° 8°
A 4.9 5.10
B 4.30 4.50
C ⎯ 1.2
D 0.8 1.05
F 1.00 Typ
F1 0.45 0.75
G 0.65 Typ
K 0.19 0.30
L 6.40 Typ
All Dimensions in mm
EH
A
A2
e
D
A1
L
Gauge Plane
Detail “A”
Detail “A”
7°(4x)
θ
B
G
L
AK
a1
D
C
a2
F
F1
Pin# 1 Indent
Det ail ‘A’
Det ail ‘A’
0
.
25
Gauge Plane
Seating Plane
B
74LVC06A
Document number: DS35259 Rev. 3 - 2 10 of 10
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74LVC07
A
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