Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LP5952 SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 LP5952 350-mA Dual-Rail Linear Regulator 1 Features 3 Description * * * * * The LP5952 is a dual-supply-rail linear regulator optimized for powering ultralow-voltage circuits from a single Li-Ion cell or 3-cell NiMH/NiCd battery. 1 * * * * * * * * * Input Voltage Range: 0.7 V to 4.5 V 2.5 V VBATT 5.5 V 0.5V VOUT 2 V Ensured 350-mA Output Current For ILOAD = 350 mA: - VBATT VOUT(NOM) + 1.5 V or 2.5 V (Whichever is Higher) For ILOAD = 150 mA: - VBATT VOUT(NOM) + 1.3 V or 2.5 V (Whichever is Higher) Excellent Load Transient Response: 15 mV Typical Excellent Line Transient Response: 1 mV Typical 50-A Typical Quiescent Current from VBATT 10-A Typical Quiescent Current from VIN 0.1-A Typical Quiescent Current in Shutdown Noise voltage = 100 VRMS Typical Operates from a Single Li-Ion Cell or 3-Cell NiMH/NiCd Battery Thermal-Overload and Short-Circuit Protection In the typical post-regulation application VBATT is directly connected to the battery (range 2.5 V to 5.5 V), and VIN is supplied by the output voltage of the DC-DC converter (range 0.7 V to 4.5 V). The device offers superior dropout and transient features combined with very low quiescent currents. In shutdown mode (Enable (EN) pin pulled low) the device turns off and reduces battery consumption to 0.1 A (typical). The LP5952 also features internal protection against overtemperature, overcurrent, and undervoltage conditions. Depending upon application, only one or two tiny surface-mount external components are required; performance is specified for a -40C to +125C junction temperature range. The device is available in fixed output voltages from 0.5 V to 2 V. For availability, please contact your local Texas Instruments sales office. Device Information(1) PART NUMBER 2 Applications * * * * * * LP5952 Mobile Phones Hand-Held Radios Personal Digital Assistants Palm-Top PCs Portable Instruments Battery-Powered Devices PACKAGE BODY SIZE (NOM) DSBGA (5) 1.326 mm x 0.96 mm USON (6) 2.00 mm x 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit VBATT: 2.7 V to 5.5 V OUT BATT C1 Preregulator For example, 1.5 V IN For example, 1.2 V 2.2 PF LP5952 + Li-Ion or 3-cell NiMh/NiCd A3 A1 Load 0 to 350 mA 1 PF EN C3 B2 GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP5952 SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information ................................................. 5 Electrical Characteristics........................................... 5 Electrical Characteristics: Quiescent Currents.......... 6 Electrical Characteristics: Shutdown Currents.......... 6 Electrical Characteristics: Enable Control................. 6 Electrical Characteristics: Thermal Protection .......... 7 Electrical Characteristics: Transient Characteristics ........................................................... 7 6.11 Input and Output Capacitors (Recommended) ....... 7 6.12 Typical Characteristics ............................................ 8 7 Detailed Description ............................................ 10 7.1 7.2 7.3 7.4 8 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 11 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application ................................................. 12 9 Power Supply Recommendations...................... 17 10 Layout................................................................... 18 10.1 Layout Guidelines ................................................. 18 10.2 Layout Examples................................................... 18 11 Device and Documentation Support ................. 19 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (May 2013) to Revision F Page * Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; update pin names to TI nomenclature.................................................................................................. 1 * Deleted lead temp spec - it is in POA ................................................................................................................................... 4 * Updated thermal information ................................................................................................................................................. 5 * Changed values for thermal specifications in Power Dissipation section per updated thermal information ....................... 14 Changes from Revision D (April 2013) to Revision E * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 18 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 LP5952 www.ti.com SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 5 Pin Configuration and Functions YZR Package 5-Pin DSBGA Top View OUT A3 A1 IN NC - No internal connection EN C3 B2 GND C1 BATT NKH Package 6-Pin USON Top View BATT 1 EN 6 GND 2 NC 5 IN 3 OUT 4 Pin Functions PIN TYPE DESCRIPTION NAME USON DSGBA BATT 1 C1 Input Bias input voltage; input range: 2.5 V to 5.5 V EN 6 C3 Input Enable pin logic input: low = shutdown, high = active, normal operation. This pin should not be left floating. Tie to BATT if this function is not used. GND 2 B2 Ground IN 3 A1 Input NC 5 -- -- OUT 4 A3 Output Ground Power input voltage; input range: 0.7 V to 4.5 V, VIN VBATT Do not make connections to this pin. Regulated output voltage Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 3 LP5952 SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN IN, BATT pins: Voltage to GND, VIN VBATT MAX V BATT pin to IN pin 0.2 EN pin, voltage to GND V Internally limited Junction Temperature (TJ-MAX ) Storage temperature, Tstg (2) (3) (4) V -0.2 Continuous power dissipation (4) (1) UNIT -0.2 -65 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. If Military or Aerospace specified devices are required, contact Texas Instruments Sales Office or Distributors for availability and specifications. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165C (typical) and disengages at TJ = 145C (typical). 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Machine model 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX Input voltage, VIN 0.7 4.5 V Input voltage, VBATT 2.5 5.5 V Input voltage, VEN 0 VBATT V Recommended load current UNIT 0 350 mA Junction temperature, TJ -40 125 C Ambient temperature, TA (1) -40 85 C (1) 4 In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RJA), as given by: TA-MAX = TJ-MAX-OP - (RJA x PD-MAX). Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 LP5952 www.ti.com SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 6.4 Thermal Information LP5952 THERMAL METRIC (1) RJA Junction-to-ambient thermal resistance (2) RJC(top) Junction-to-case (top) thermal resistance RJB Junction-to-board thermal resistance JT Junction-to-top characterization parameter JB Junction-to-board characterization parameter (1) (2) YZR (DSBGA) NKH (USON) 5 PINS 6 PINS UNIT 181.0 181.6 C/W 0.9 93.1 C/W 110.3 116.7 C/W 7.4 8.0 C/W 110.3 116.7 C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special attention must be paid to thermal dissipation issues in board design. 6.5 Electrical Characteristics Unless otherwise noted, typical values are for TA = 25C, and minimum and maximum limits apply over the full operating temperature range: -40C TJ +125C; specifications apply to the Typical Application Circuit with VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V or 2.5 V (whichever is higher), IOUT = 1 mA, CVIN = 1 F, COUT = 2.2 F, VEN = VBATT. (1) (2) (3) PARAMETER VOUT / VOUT Output voltage tolerance VOUT / VIN VOUT / VBATT VOUT / mA VDO_VBATT (4) VDO_VIN (1) (2) (3) (4) (5) Output voltage dropout VBATT (5) Output voltage dropout VIN Output noise MIN TYP MAX -1.5 1.5 VIN = VOUT(NOM) + 0.3 V 2 2 VIN = VOUT(NOM) + 0.3 V to 4.5 V, VBATT = 4.5 V 1 VBATT = VOUT(NOM) + 1.5 V ( 2.5 V) to 5.5 V 2.2 IOUT = 1 mA to 350 mA DSBGA package 30 IOUT = 1 mA to 350 mA USON package 60 Load regulation error Output current (short circuit) ISC EN Line regulation error TEST CONDITIONS VIN = VOUT(NOM) + 0.3 V, TA = 25C VOUT = 0 V, VEN = VIN = VBATT = VOUT(NOM) + 1.5 V 350 0.3 0.5 1 UNIT mV/V 2.2 15 30 V/mA 43 60 V/mA 500 mA IOUT = 350 mA, VIN = VOUT(NOM) + 0.3 V DSBGA package 1.07 1.5 V IOUT = 350 mA VIN = VOUT(NOM) + 0.3 V USON package 1.08 1.5 V IOUT = 150 mA VIN = VOUT(NOM) + 0.3 V DSBGA package 0.96 1.3 V IOUT = 150 mA VIN = VOUT(NOM) + 0.3 V USON package 0.97 1.3 V IOUT = 350 mA VBATT = VOUT(NOM) + 1.5 V or 2.5 V DSBGA package 88 200 mV IOUT = 350 mA VBATT = VOUT(NOM) + 1.5 V or 2.5 V USON package 128 250 mV 10 Hz to 100 kHz 100 VRMS All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V or 2.5 V, whichever is higher, TA = 25C. VOUT(NOM) is the stated output voltage option This specification does not apply if the battery voltage VBATT needs to be decreased below the minimum operating limit of 2.5 V during this test. Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100mV below the nominal output voltage. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 5 LP5952 SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, typical values are for TA = 25C, and minimum and maximum limits apply over the full operating temperature range: -40C TJ +125C; specifications apply to the Typical Application Circuit with VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V or 2.5 V (whichever is higher), IOUT = 1 mA, CVIN = 1 F, COUT = 2.2 F, VEN = VBATT.(1)(2)(3) PARAMETER Power Supply Rejection Ratio PSRR Power Supply Rejection Ratio PSRR TEST CONDITIONS MIN TYP Sine modulated VBATT, = 10 Hz 70 Sine modulated VBATT, = 100 Hz 65 Sine modulated VBATT, = 1 kHz 45 Sine modulated VIN, = 10 Hz 80 Sine modulated VIN, = 100 Hz 90 Sine modulated VIN, = 1 kHz 95 Sine modulated VIN, = 10 kHz 85 Sine modulated VIN, = 100 kHz 64 MAX UNIT dB dB 6.6 Electrical Characteristics: Quiescent Currents Unless otherwise noted, typical values are for TA = 25C, and minimum and maximum limits apply over the full operating temperature range: -40C TJ +125C. (1) (2) (3) TYP MAX UNIT IQ_VBATT PARAMETER Current into VBATT ILOAD = 0 mA to 350mA 50 100 A IQ_VIN Current into VIN ILOAD = 0 11 28 A (1) (2) (3) TEST CONDITIONS MIN All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V or 2.5 V, whichever is higher, TA = 25C. VOUT(NOM) is the stated output voltage option 6.7 Electrical Characteristics: Shutdown Currents Unless otherwise noted, typical values are for TA = 25C, and minimum and maximum limits apply over the full operating temperature range: -40C TJ +125C. (1) (2) (3) TYP MAX IQ_VBATT PARAMETER Current into VBATT VEN = 0 V 0.1 1 A IQ_VIN Current into VIN VEN = 0 V 0.1 1 A (1) (2) (3) TEST CONDITIONS MIN UNIT All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V or 2.5 V, whichever is higher, TA = 25C. VOUT(NOM) is the stated output voltage option. 6.8 Electrical Characteristics: Enable Control Unless otherwise noted, typical values are for TA = 25C, and minimum and maximum limits apply over the full operating temperature range: -40C TJ +125C. (1) (2) (3) PARAMETER IEN Maximum input current at EN input VIL Low input threshold (shutdown) VIH High input threshold (enable) (1) (2) (3) 6 TEST CONDITIONS MIN 1 TYP MAX 0.01 1 UNIT A 0.4 V V All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V or 2.5 V, whichever is higher, TA = 25C. VOUT(NOM) is the stated output voltage option. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 LP5952 www.ti.com SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 6.9 Electrical Characteristics: Thermal Protection Typical values are for TA = 25C. (1) (2) (3) PARAMETER TEST CONDITIONS TSHDN Thermal-shutdown temperature TSHDN Thermal-shutdown hysteresis (1) (2) (3) MIN TYP MAX UNIT 165 C 20 C All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V or 2.5 V, whichever is higher, TA = 25C. VOUT(NOM) is the stated output voltage option. 6.10 Electrical Characteristics: Transient Characteristics Unless otherwise noted, typical values are for TA = 25C, and minimum and maximum limits apply over the full operating temperature range: -40C TJ +125C. (1) (2) (3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT Dynamic line transient response VIN VIN = VOUT(NOM) + 0.3 V to VOUT(NOM) + 0.9 V; tr, tf = 10 s 1 mV VOUT Dynamic line transient response VBATT VBATT = VOUT(NOM) + 1.5 V to VOUT(NOM) + 2.1 V; tr, tf = 10 s 15 mV Pulsed load 0 ...300 mA, di/dt = 300 mA/1 s 15 mV VOUT Dynamic load transient response -35/+15 mV TSTARTUP Start-up time (1) (2) (3) DSBGA package Pulsed load 0 ...300mA, di/dt USON package = 300 mA/1 s EN to 0.95 x VOUT 70 150 s All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V or 2.5 V, whichever is higher, TA = 25C. VOUT(NOM) is the stated output voltage option. 6.11 Input and Output Capacitors (Recommended) All values are for TA = 25C. (1) (2) (3) PARAMETER COUT Output capacitance CVIN Input capacitance at VIN TEST CONDITIONS Capacitance (4) ESR (3) (4) TYP MAX 1.5 2.2 10 F 300 m 3 Capacitance (4), not needed in typical postregulation application (see Figure 18) ESR (1) (2) MIN 0.47 3 UNIT 1 F 300 m All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = VOUT(NOM) + 1 V, VBATT= VOUT(NOM) + 1.5 V or 2.5 V, whichever is higher, TA = 25C. VOUT(NOM) is the stated output voltage option. The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R, Y5V, and Z5U can also be used. The shown minimum limit represents real minimum capacitance, including all tolerances and must be maintained over temperature and DC bias voltage (See Detailed Design Procedure in Application and Implementation.) Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 7 LP5952 SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 www.ti.com 6.12 Typical Characteristics 0.4 140 0.3 130 0.2 120 DROPOUT VIN (mV) VOUT CHANGE (%) Unless otherwise specified, TA = 25C, CIN = 1-F ceramic, COUT = 2.2-F ceramic, VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V, EN pin is tied to VBATT (DSBGA package). 0.1 0.0 -0.1 110 100 90 80 -0.2 -0.3 70 -0.4 -40 -20 60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 0 20 40 60 80 100 120 TEMPERATURE (C) ILOAD = 350 mA Figure 1. Output Voltage Change vs Temperature Figure 2. Dropout VIN vs Temperature 90 ILOAD = 0 IIN (100 mA/ DIV) 70 IQ_VBATT (A) VOUT (500 mV/ DIV) VEN (500 mV/ DIV) 80 0 0 TA = 125C 60 TA = 25C 50 40 TA = -40C 30 0 20 10 2.0 TIME (10 Ps/DIV) 1.5-V Option 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VBATT (V) Figure 3. Inrush Current VIN Figure 4. Quiescent Current IQ_VBATT vs VBATT 100 ILOAD = 0 80 GROUND CURRENT (A) GROUND CURRENT (A) 90 TA = 125C 70 TA = 25C 60 50 TA = -40C 40 30 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LOAD CURRENT (mA) VBATT /VIN (V) Figure 5. Ground Current vs VBATT / VIN 8 Submit Documentation Feedback Figure 6. Ground Current vs Load Current Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 LP5952 www.ti.com SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 Typical Characteristics (continued) Unless otherwise specified, TA = 25C, CIN = 1-F ceramic, COUT = 2.2-F ceramic, VIN = VOUT(NOM) + 1 V, VBATT = VOUT(NOM) + 1.5 V, EN pin is tied to VBATT (DSBGA package). 0 CIN = 100nF -20 RIPPLE REJECTION (dB) RIPPLE REJECTION (dB) 0 -40 IL = 50 mA -60 IL = 0 mA -80 10 100 1k 10k 100k -20 IL = 300 mA -40 -60 -80 10 1M IL = 0 mA 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) 1.5-V Option 1.5-V Option Figure 7. Power Supply Rejection Ratio VIN Figure 8. Power Supply Rejection Ratio VBATT Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 9 LP5952 SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The LP5952 is a dual-supply-rail linear regulator optimized for powering ultralow-voltage circuits from a single LiIon cell or 3 cell NiMH/NiCd batteries. In a typical application, BATT is connected to the battery, and IN can be supplied by the output of front stage DC-DC Converter. IN does not exceed BATT at any time. 7.2 Functional Block Diagram BATT VREF IN + - EN Enable and start-up management OUT Thermal, undervoltage, and overcurrent protection GND 7.3 Feature Description 7.3.1 Dual-Rail Supply The LP5952 requires two different supply voltages: * VIN, the power input voltage, is regulated to the fixed output voltage. * VBATT, the bias input voltage, supplies internal circuitry. It is important that VIN does not exceed VBATT at any time. If the device is used in the typical post-regulation application as shown in Figure 18, the sequencing of the two power supplies is not an issue because VBATT supplies both the DC-DC regulator and the LP5952 device. The output voltage of the DC-DC regulator takes some time to rise up and supply the input voltage of the device. In this application VIN always ramps up more slowly than VBATT. If VIN is shorted to VBATT, the voltages at the two supply pins ramp up simultaneously causing no problems. However, in applications with two independent supplies connected to the LP5952, special care must be taken to ensure that VIN is always VBATT. 7.3.2 No-Load Stability The LP5952 remains stable and in regulation with no external load. This is an important consideration in some circuits, for example, CMOS RAM keep-alive applications. 7.3.3 Fast Turnon Fast turnon is ensured by an optimized architecture allowing a fast ramp of the output voltage to reach the target voltage while the inrush current is controlled low at 120 mA typical (for a COUT of 2.2 F). 10 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 LP5952 www.ti.com SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 Feature Description (continued) 7.3.4 Short-Circuit Protection The LP5952 is short-circuit protected and, in the event of a peak overcurrent condition, the output current through the NFET pass device is limited. If the overcurrent condition exists for a longer time, the average power dissipation increases depending on the input-to-output voltage difference until the thermal shutdown circuitry turns the NFET off. Refer to Power Dissipation and Device Operation for power dissipation calculations. 7.3.5 Thermal-Overload Protection Thermal-overload protection limits the total power dissipation in the LP5952. When the junction temperature exceeds TJ = 165C typical, the shutdown logic is triggered, and the NFET is turned off, allowing the device to cool down. After the junction temperature dropped by 20C (temperature hysteresis) typical, the NFET is activated again. This results in a pulsed output voltage during continuous thermal-overload conditions. The thermal-overload protection is designed to protect the LP5952 in the event of a fault condition. For normal continuous operation, do not exceed the absolute maximum junction temperature rating of TJ = 150C (see Absolute Maximum Ratings). 7.3.6 Reverse Current Path The internal NFET pass device in LP5952 has an inherent parasitic body diode. During normal operation, the input voltage is higher than the output voltage, and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, the current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 50 mA. For currents above this limit an external Schottky diode must be connected from VOUT to VIN (cathode on VIN, anode on VOUT). 7.4 Device Functional Modes 7.4.1 Enable Operation The LP5952 may be switched to an ON or OFF state by a logic input at the EN pin, VEN. A logic high at this pin turns the device on. When the enable pin is low, the regulator output is off, and the device typically consumes 0.1 A. If the application does not require the enable switching feature, the EN pin must be tied to VBATT to keep the regulator output permanently on. To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below the specified turnon and turnoff voltage thresholds shown in VIL and VIH in Electrical Characteristics: Enable Control. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 11 LP5952 SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP5952 is designed to meet ultralow input-voltage application, by implementing VBATT as power supply of this device. The VBATT is connected to the battery (range 2.5 V to 5.5 V), the VIN range can be 0.7 V to 4.5 V. The device offers superior dropout and transient features combined with very low-quiescent currents. The LP5952 delivers this performance in standard packages DSBGA and USON with an operating junction temperature (TJ) of -40C to +125C. 8.2 Typical Application 8.2.1 Dual-Rail Linear Regulator VBATT: 2.7 V to 5.5 V OUT BATT C1 Preregulator For example, 1.5 V IN For example, 1.2 V 2.2 PF LP5952 + Li-Ion or 3-cell NiMh/NiCd A3 A1 Load 0 to 350 mA 1 PF EN C3 B2 GND Figure 9. LP5952 Typical Application Circuit 8.2.1.1 Design Requirements For typical dual-rail linear regulator parameters, see Table 1. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 0.7 V to 4.5 V VBATT voltage range 2.7 V to 5.5 V Output voltage 1.5 V Output current 350 mA Output capacitor range 2.2 F Input/output capacitor ESR range 3 m to 300 m 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 External Capacitors As is common with most regulators, the LP5952 requires external capacitors to ensure stable operation. The LP5952 is specifically designed for portable applications requiring minimum board space and the smallest size components. These capacitors must be correctly selected for good performance. 8.2.1.2.2 Input Capacitor If the LP5952 is used as a stand-alone device, an input capacitor at VIN is required for stability. It is recommended that a 1-F capacitor be connected between the LP5952 power voltage IN pin and ground. (This capacitance value may be increased without limit). 12 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 LP5952 www.ti.com SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. A capacitor at VBATT is not required if the distance to the supply does not exceed 5 cm. If the device is used in the typical application as post regulator after a DC-DC regulator, no input capacitors are required -- the capacitors of the DC-DC regulator (CIN and COUT) are sufficient if both components are mounted close to each other and a proper GND plane is used. If the distance between the output capacitor of the DC-DC regulator and the IN pin of the LP5952 is larger than 5 cm, adding an input capacitor at VIN is recommended. NOTE Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. The equivalent series resistance (ESR) of the input capacitor should be in the range of 3 m to 300 m. The tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains 470 nF over the entire operating temperature range. 8.2.1.2.3 Output Capacitor The LP5952 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types X7R, Z5U, or Y5V) in the 2.2-F range (up to 10 F) and with an ESR between 3 m to 300 m is suitable as COUT in the LP5952 application circuit. This capacitor must be located a distance of not more than 1 cm from the OUT pin and returned to a clean analog ground. It is also possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). 8.2.1.2.4 Capacitor Characteristics The LP5952 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the 1-F to 4.7-F range, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high-frequency noise. The ESR of a typical 1-F ceramic capacitor is in the range of 3 m to 40 m, which easily meets the ESR requirement for stability for the LP5952. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. In particular, the output capacitor selection must take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer performance figures in general. Figure 10 shows a typical graph comparing different capacitor case sizes in a capacitance vs. DC Bias plot. As shown Figure 10, increasing the DC-bias condition can result in the capacitance value falling below the minimum value given in Input and Output Capacitors (Recommended) (0.47 F or 1.5 F in this case). The graph shows the capacitance out of specification for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor-manufacturer specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (such as 0402) may not be suitable in the actual application. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 13 LP5952 CAP VALUE (% of Nom. 1 PF) SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 www.ti.com 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 10. Typical Variation In Capacitance vs DC Bias Capacitance of the ceramic capacitor can vary with temperature. The capacitor type X7R, which operates over a temperature range of -55C to +125C, only varies the capacitance to within 15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of -55C to +85C. Many large value ceramic capacitors, larger than 1 F, are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25C to 85C. Therefore, X7R is recommended over Z5U and Y5V in applications where the ambient temperature changes significantly above or below 25C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1-F to 4.7-F range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. The ESR of a typical tantalum increases about 2:1 as the temperature goes from 25C down to -40C, so some guard band must be allowed. 8.2.1.2.5 Power Dissipation and Device Operation The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. As stated in the Recommended Operating Conditions, the allowable power dissipation for the device in a given package can be calculated using Equation 1: PD = (TJ(MAX) - TA) / RJA (1) With an RRJA = 181C/W, the device in the 5-pin DSBGA package returns a value of 552 mW with a maximum junction temperature of 125C at TA of 25C or 221 mW at TA of 85C. The actual power dissipation across the device can be estimated by Equation 2: PD = (VIN - VOUT) x IOUT 14 (2) Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 LP5952 www.ti.com SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. Equation 1 and Equation 2 must be used to determine the optimum operating conditions for the device in any application. As an example, to keep full load current capability of 350 mA for a 1.5-V output voltage option at a high ambient temperature of 85C, VIN has to be kept 2.1 V (for DSBGA package): VIN PD / IOUT + VOUT = 221 mW / 350 mA + 1.5 V = 2.1 V (3) Figure 11 shows the output current derating due to these considerations: 350 DSBGA USON ILOADMAX (mA) 300 250 200 150 100 50 0 0.5 1 1.5 2 2.5 VIN - VOUT (V) 3 3.5 TA = 85C VOUT = 1.5 V RJA(DSBGA) = 181C/W RJA(USON) = 181.6C/W 4 D001 Figure 11. Maximum Load Current vs VIN - VOUT The typical contribution of the bias input voltage supply VBATT to the power dissipation can be neglected (Equation 4): PD_VBATT = VBATT x IQVBATT = 5.5 V x 50 A = 0.275 mW typical (4) Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 15 LP5952 SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 www.ti.com 8.2.1.3 Application Curves IL = 350 mA 0 0 VOUT VEN (500 mV/DIV) 0 (500 mV/DIV) VEN (500 mV/DIV) VOUT 0 (200 mV/DIV) IL = 350 mA TIME (10 s/DIV) TIME (10 s/DIV) 0.7-V Option 1.5-V Option LOAD CURRENT (mA) Figure 13. Enable Start-Up Time 0 AVOUT 350 0 (10 mV/DIV) 350 (10 mV/DIV) AVOUT LOAD CURRENT (mA) Figure 12. Enable Start-Up Time TIME (50 s/DIV) TIME (50 s/DIV) 0.7-V Option 1.5-V Option Figure 14. Load Transient Response VBATT 2.5 AVOUT (500 mV/DIV) IL = 350 mA 3.1 3.6 3.0 (10 mV/DIV) (500 mV/DIV) IL = 350 mA (1 mV/DIV) AVOUT VIN VBATT = 3.1V Figure 15. Load Transient Response TIME (100 Ps/DIV) TIME (100 Ps/DIV) 1.5-V Option 1.5-V Option Figure 16. Line Transient Response VIN 16 Submit Documentation Feedback Figure 17. Line Transient Response VBATT Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 LP5952 www.ti.com SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 8.2.2 Additional Application Circuit BATT C1 VOUTDCDC VBATT 3 V to 5.5 V VIN A1 4.7 PF B2 SW 1.8 V A3 LP5952 IN OUT 2.2 PF Load 0 to 350 mA A1 L1: 2.2 PH LM3671TL-1.8 1.5 V 10 PF GND A3 EN EN C1 C3 C3 B2 GND FB Figure 18. Typical Application Circuit With DC-DC Converter as Pre-Regulator for VIN 9 Power Supply Recommendations This device is designed to operate from an input supply voltage range of 0.7 V to 4.5 V. The input supply should be well regulated and free of spurious noise. A minimum capacitor value of 1-F is required to be within 1 cm of the IN pin. The VBATT range is 2.5 V to 5.5 V and, in the typical application, VBATT is connected to batteries. In any application, VIN does not exceed VBATT. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 17 LP5952 SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 www.ti.com 10 Layout 10.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near to the respective LDO pin connections as practical. Place ground return connections as close as possible to the input and output capacitor and to the LDO ground pin, connected by a wide, copper surface. The use of vias and long traces to create LDO circuit connection is strongly discouraged and negatively affect system performance. 10.2 Layout Examples COUT OUT2 EN C3 OUT A3 B2 GND A1 IN CIN C1 BATT CBATT Figure 19. LP5952 DSBGA Layout Example CBATT BATT 1 6 EN GND 2 5 NC IN 3 4 OUT CIN COUT Figure 20. LP5952 WSON Layout Example 18 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 LP5952 www.ti.com SNVS469F - OCTOBER 2006 - REVISED DECEMBER 2015 11 Device and Documentation Support 11.1 Device Support For availability of evaluation boards, refer to the product folder of LP5952 at www.ti.com. 11.2 Documentation Support 11.2.1 Related Documentation For information regarding evaluation boards, please refer to AN-1531 LP5952 Evaluation Board (SNVA188). 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP5952 19 PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LP5952LC-1.2/NOPB ACTIVE USON NKH 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L28 LP5952LC-1.3/NOPB ACTIVE USON NKH 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L43 LP5952LC-1.5/NOPB ACTIVE USON NKH 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L25 LP5952LC-1.8/NOPB ACTIVE USON NKH 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L29 LP5952TL-1.0/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 L LP5952TL-1.2/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 7 LP5952TL-1.3/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 U LP5952TL-1.5/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 T LP5952TL-1.6/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 B LP5952TL-1.8/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 8 LP5952TLX-1.0/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 L LP5952TLX-1.2/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 7 LP5952TLX-1.5/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 T LP5952TLX-1.8/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 8 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2017 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP5952LC-1.2/NOPB USON NKH 6 1000 178.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1 LP5952LC-1.3/NOPB USON NKH 6 1000 178.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1 LP5952LC-1.5/NOPB USON NKH 6 1000 178.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1 LP5952LC-1.8/NOPB USON NKH 6 1000 178.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1 LP5952TL-1.0/NOPB DSBGA YZR 5 250 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 LP5952TL-1.2/NOPB DSBGA YZR 5 250 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 LP5952TL-1.3/NOPB DSBGA YZR 5 250 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 LP5952TL-1.5/NOPB DSBGA YZR 5 250 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 LP5952TL-1.6/NOPB DSBGA YZR 5 250 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 LP5952TL-1.8/NOPB DSBGA YZR 5 250 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 LP5952TLX-1.0/NOPB DSBGA YZR 5 3000 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 LP5952TLX-1.2/NOPB DSBGA YZR 5 3000 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 LP5952TLX-1.5/NOPB DSBGA YZR 5 3000 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 LP5952TLX-1.8/NOPB DSBGA YZR 5 3000 178.0 8.4 1.04 1.4 0.76 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP5952LC-1.2/NOPB USON NKH 6 1000 210.0 185.0 35.0 LP5952LC-1.3/NOPB USON NKH 6 1000 210.0 185.0 35.0 LP5952LC-1.5/NOPB USON NKH 6 1000 210.0 185.0 35.0 LP5952LC-1.8/NOPB USON NKH 6 1000 210.0 185.0 35.0 LP5952TL-1.0/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP5952TL-1.2/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP5952TL-1.3/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP5952TL-1.5/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP5952TL-1.6/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP5952TL-1.8/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP5952TLX-1.0/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP5952TLX-1.2/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP5952TLX-1.5/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP5952TLX-1.8/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NKH0006B LCA06B (Rev A) www.ti.com MECHANICAL DATA YZR0005xxx D 0.6000.075 E TLA05XXX (Rev C) D: Max = 1.356 mm, Min =1.296 mm E: Max = 0.99 mm, Min = 0.93 mm 4215043/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. 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