ANALOG DEVICES +2.] V to +9.5 V, 350 KSPS, 10-Bit 4-/8-Channel Sampling ADCs AD7811/AD7812 FEATURES 10-Bit ADC with 2.3 ps Conversion Time The AD7811 has Four Single-Ended Inputs that Can Be Configured as Three Pseudo Differential Inputs with Respect to a Common, or as Two Inde- pendent Pseudo Differential Channels The AD7812 has Eight Single-Ended Inputs that Can Be Configured as Seven Pseudo Differential Inputs with Respect to a Common, or as Four Independent Pseudo Differential Channels Onboard Track and Hold Onboard Reference 2.5 V + 2.5% Operating Supply Range: +2.7 V to +5.5 V Specifications at 2.7 V-3.6 V and 5 V + 10% DSP-/Microcontroller-Compatible Serial Interface High Speed Sampling and Automatic Power-Down Modes Package Address Pin on the AD7811 and AD7812 Allows Sharing of the Serial Bus in Multipackage Applications Input Signal Range: 0 V to Vper Reference Input Range: 1.2 V to Vpp GENERAL DESCRIPTION The AD7811 and AD7812 are high speed, low power, 10-bit A/D converters that operate from a single +2.7 V to +5.5 V supply. The devices contain a 2.3 ws successive approximation A/D converter, an on-chip track/hold amplifier, a 2.5 V on-chip reference and a high speed serial interface that is compatible with the serial interfaces of most DSPs (Digital Signal Proces- sors) and microcontrollers. The user also has the option of using an external reference by connecting it to the Vapp pin and set- ting the EXTREF bit in the control register. The Vazp pin may be tied to Vpp. At slower throughput rates the power-down mode may be used to automatically power down between conversions. The control registers of the AD7811 and AD7812 allow the input channels to be configured as single-ended or pseudo differential. The control register also features a software convert start and a software power-down. Two of these devices can share the same serial bus and may be individually addressed in a multipackage application by hardwiring the device address pin. The AD7811 is available in a small, 16-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a 16-lead 0.15" wide, Small Outline IC (SOIC) and in a 16-lead, Thin Shrink Small Out- line Package (TSSOP). The AD7812 is available in a small, 20-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a 20-lead, Small Outline IC (SOIC) and in a 20-lead, Thin Shrink Small Outline Package (TSSOP). PRODUCT HIGHLIGHTS 1. Low Power, Single Supply Operation Both the AD7811 and AD7812 operate from a single +2.7 V to +5.5 V supply and typically consume only 10 mW of power. The power dissipation can be significantly reduced at lower throughput rates by using the automatic power-down mode e.g., 315 pW @ 10 kKSPS, Vpp = 3 Vsee Power vs. Throughput. 2. 4-/8-Channel, 10-Bit ADC The AD7811 and AD7812 have four and eight single-ended input channels respectively. These inputs can be configured as pseudo differential inputs by using the Control Register. 3. On-chip 2.5 V (42.5%) reference circuit that is powered down when using an external reference. 4. Hardware and Software Control The AD7811 and AD7812 provide for both hardware and software control of Convert Start and Power-Down. FUNCTIONAL BLOCK DIAGRAMS Crer REF in Yop AGND DGND Ld Ld } 1.23V } [ REF f AD7811 > CLOCK BUF , osc y DOUT CHARGE IN DIN REDISTRIBUTION oa RFS DAC 4 TFS Vint ; SCLK Vine MUX Ving LOY CONTROL Vina Vp! LOGIC AO CONVST REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Crer REFiy Vpp AGND DGND t O O O 1.230 ] v AD7812 s ( > CLOCK , Osc , DOUT Vint DIN CHARGE PN Ving REDISTRIBUTION SERIAL RFS DAC Vins TFS Vina MUX SCLK yiNs 5 IN6 CONTROL Vinz LOGIC Ving AO CONVST One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1998AD7811/AD7812-SPECIFICATIONS (Von = +2.1 V to +3.6 V, Von =+5V+ 10%, GND = OV, Ver = +Vop [EXT]. All specifications 40C to +105C unless otherwise noted.) Parameter Y Version Units Test Conditions/Comments DYNAMIC PERFORMANCE fy = 30 kHz Any Channel, fsamprz = 350 KHz Signal to (Noise + Distortion) Ratio! 58 dB min Verse Internal or External Total Harmonic Distortion (THD)! -66 dB max Peak Harmonic or Spurious Noise! -80 dB typ Intermodulation Distortion ? fa = 29 kHz, fb = 30 kHz Second Order Terms -67 dB max Third Order Terms -67 dB max Channel-to-Channel Isolation) -80 dB typ fy = 20 kHz DC ACCURACY Any Channel Resolution 10 Bits Minimum Resolution for Which No Missing Codes are Guaranteed 10 Bits Relative Accuracy +1 LSB max Differential Nonlinearity! +1 LSB max Gain Error! +2 LSB max Gain Error Match! +0.75 LSB max Offset Error! +2 LSB max Offset Error Match! +0.75 LSB max ANALOG INPUT Input Voltage Range 0 V min VREF V max Input Leakage Current +1 HA max Input Capacitance? 20 pF max REFERENCE INPUTS? Veer Input Voltage Range 1.2 V min Vpp V max Input Leakage Current +3 HA max Input Capacitance 20 pF max ON-CHIP REFERENCE Nominal 2.5 V Reference Error 42.5 % max Temperature Coefficient 50 ppm/C typ LOGIC INPUTS? Vinu, Input High Voltage 2.4 V min Vpp = 5 V+ 10% Vint, Input Low Voltage 0.8 V max Vpp = 5 V+ 10% Vinu, Input High Voltage 2 V min Vpp = 3 V+ 10% Vint, Input Low Voltage 0.4 V max Vpp = 3 V+ 10% Input Current, In +1 HA max Typically 10 nA, Vypy = 0 V to Vpp Input Capacitance, Cpy 8 pF max LOGIC OUTPUTS Output High Voltage, Voy Isourcz = 200 pA 4 V min Vpp =5 Vt 10% 2.4 V min Vpp = 3 Vt 10% Output Low Voltage, Vor Isnvx = 200 pA 0.4 V max High Impedance Leakage Current +1 HA max High Impedance Capacitance 15 pF max CONVERSION RATE Conversion time 2.3 pis max Track/Hold Acquisition Time 200 ns max REV. AAD7811/AD7812 Parameter Y Version Units Test Conditions/Comments POWER SUPPLY Vop 2.7 V min For Specified Performance 5.5 V max Ipp Digital Inputs = 0 V or Vpp Normal Operation 3.5 mA max Power-Down Full Power-Down 1 HA max Partial Power-Down (Internal Ref) 350 HA max See Power-Up Times Section Power Dissipation Vpp =3 V Normal Operation 10.5 mW max Auto Pull Power-Down See Power vs. Throughput Section Throughput 1 kSPS 31.5 pW max Throughput 10 kKSPS 315 pW max Throughput 100 kSPS 3.15 mW max Partial Power-Down (Internal Ref) 1.05 mW max Full Power-Down 3 pW max NOTES See Terminology. *Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice. TIMING CHARACTERISTICS": 2 (Vop = +2.7 V to +5.5 V, Vper = +Vpp [EXT] unless otherwise noted) Parameter Y Version Units Conditions/Comments TpowER-UP 1 lis (max) Power-Up Time of AD7811/AD7812 After Rising Edge of CONVST ty 2.3 lis (max) Conversion Time ty 20 ns (min) CONVST Pulsewidth Ts 25 ns (min) SCLK High Pulsewidth ty 25 ns (min) SCLK Low Pulsewidth ts 5 ns (min) RES Rising Edge to SCLK Rising Edge Setup Time te 5 ns (min) TES Falling Edge to SCLK Falling Edge Setup Time t, 10 ns (max) SCLK Rising Edge to Data Out Valid ts 10 ns (min) DIN Data Valid to SCLK Falling Edge Setup Time to 5 ns (min) DIN Data Valid after SCLK Falling Edge Hold Time ty?" 20 ns (max) SCLK Rising Edge to Dour High Impedance ty 100 ns (min) DOUT High Impedance to CONVST Falling Edge NOTES 'Sample tested to ensure compliance. *See Figures 16, 17 and 18. 3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V pp = 5 V + 10% and 0.4 V or 2 V for Vpp = 3 Vt 10%. Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t,,, quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. TO OUTPUT PIN +2.1V Figure 1. Load Circuit for Digital Output Timing Specifications REV. A -3-AD7811/AD7812 ABSOLUTE MAXIMUM RATINGS* SOIC Package, Power Dissipation ............... 450 mW Vpp to DGND ... 1... eee ee 0.3. Vto+7V Oy, Thermal Impedance ..............000000- 75CIW Digital Input Voltage to DGND (CONVST, SCLK, RES, TES, Lead Temperature, Soldering DIN, A0) 21... ee eee eee ee ee eee -0.3 V, Vpp + 0.3 V Vapor Phase (60 sec) ............---2 20 eee +215C Digital Output Voltage to DGND (DOUT) Infrared (15 sec) oo. ceeee eee +220C wn eee ene eee eee eens 0.3 V, Vpop + 0.3 V TSSOP Package, Power Dissipation ............. 450 mW REF py to AGND .. 2... ee eee eee -0.3 V, Vpp + 0.3. V O;, Thermal Impedance ................000- 115C/W Analog Inputs Lead Temperature, Soldering Vini-Ving (AD7811) 0-0 eee -0.3 V, Vpp + 0.3 V Vapor Phase (60 sec) ..... 0. cece cece eee ee +215C Vini-Ving (AD7812) 0... eee ee -0.3 V, Vpp + 0.3 V Infrared (15 sec) oo. cee eee eee eee eee +220C Storage Temperature Range ............ 65C to +150C DCL) Da 3kV Junction Temperature .................---2200- +150C kStresses above those listed under Absolute Maximum Ratin . . . gs may cause perma- Plastic DIP Package, Power Dissipation sree ees 450 mW nent damage to the device. This is a stress rating only; functional operation of the Ora Thermal Impedance see we eee ee eee ee eee +105C/W device at these or any other conditions above those listed in the operational Lead Temperature, (Soldering 10 sec) See ee eeeeee +260C sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Linearity Package Package Model Error Descriptions Options AD7811YN +1 LSB 16-Lead Plastic DIP N-16 AD7811YR +1 LSB 16-Lead Small Outline IC (SOIC) R-16A AD7811YRU +1 LSB 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD7812YN +1 LSB 20-Lead Plastic DIP N-20 AD7812YR +1 LSB 20-Lead Small Outline IC (SOIC) R-20A AD7812YRU +1 LSB 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20 REV. AAD7811/AD7812 Veer [1] @ Crer [2] Vint [3] AGND [4] Ving [5] (Not to Scale) Vins [6] Vina [7] AO [a] TOP VIEW PIN CONFIGURATIONS DIP/SOIC/TSSOP TV 7 Veer [1] 20] Voo 5] CONVST Crer [2] ha] CONVET AD7811 fa] Sor Vini [BI hg] SCLK AGND [4] 7] DIN fa] DOUT Vine [5] AD7812 [ie] DOUT Vv, TOP VIEW 15| RFS INS [e| (Not to Scale) 5] Vina [7 ha] TFS re] DGND Vins [a] 3] DGND Vine [31 fa] 40 Vinz [to] A] Vins PIN FUNCTION DESCRIPTIONS Pin(s) AD7811 Pin(s) AD7812 Name Description 3, 5-7 10 11 12 13 14 15 16 3, 5-11 12 13 14 15 16 17 18 19 20 VREF Crer Vini-Vinacs) AGND AO DGND TFS RFS DOUT DIN SCLK CONVST Vpp An external reference input can be applied here. When using an external precision reference or Vpp the EXTREF bit in the control register must be set to logic one. The external reference input range is 1.2 V to Vpp. Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise performance of the on-chip reference. Analog Inputs. The analog input range is 0 V to Vaz. Analog Ground. Ground reference for track/hold, comparator, on-chip reference and DAC. Package Address Pin. This Logic Input can be hardwired high or low. When used in conjunction with the package address bit in the control register this input allows two devices to share the same serial bus. For example a twelve channel solution can be achieved by using the AD7811 and the AD7812 on the same serial bus. Digital Ground. Ground reference for digital circuitry. Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new control byte should be shifted in on the next 10 falling edges of SCLK. Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in the serial interface. It is used to provide compatibility with DSPs which use a continuous serial clock and framing signal. In multipackage applications the RFS Pin can also be used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a rising edge on this input. The counter is reset at the end of a serial read operation. Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial clock. The output enters a High impedance condition on the rising edge of the 11th SCLK pulse. Serial Data Input. The control byte is read in at this input. In order to complete a serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are shifted insee Serial Interface section. Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK. Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold Mode on the falling edge of this signal and a conversion is initiated. The state of this pin at the end of conversion also determines whether the part is powered down or not. See operating modes section of this data sheet. Positive Supply Voltage +2.7 V to +5.5 V. REV. A -5-AD7811/AD7812 TERMINOLOGY Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distor- tion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Notse + Distortion) = (6.02N + 1.76) dB Thus for a 10-bit converter, this is 62 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7811 and AD7812 it is defined as: 2 2 2 2 2 5 +V; +V; +Vz +V; THD (dB) =20 log 7 1 where V, is the rms amplitude of the fundamental and V,, V3, V4, Vs and V, are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f,/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa + nfb where m,n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa fb), while the third order terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb). The AD7811 and AD7812 are tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the inter- modulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full- scale 20 kHz sine wave signal to all nonselected input channels and determining how much that signal is attenuated in the selected channel. The figure given is the worst case across all four or eight channels for the AD7811 and AD7812 respectively. Relative Accuracy Relative accuracy, or endpoint nonlinearity, is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (0000... 000) to (0000... 001) from the ideal, i.e., AGND + 1 LSB. Offset Error Match This is the difference in Offset Error between any two channels. Gain Error This is the deviation of the last code transition (1111... 110) to (1111...111) from the ideal, i.e., Vag 1 LSB, after the offset error has been adjusted out. Gain Error Match This is the difference in Gain Error between any two channels. Track/Hold Acquisition Time Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within +1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected V.y input of the AD7811 or AD7812. It means that the user must wait for the duration of the track/hold acquisi- tion time after the end of conversion or after a channel change/ step input change to Vj, before starting another conversion, to ensure that the part operates to specification. REV. AAD7811/AD7812 Control Register (AD7811) The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7811 receives a falling edge on its TFS pin. The AD7811 will maintain the same configuration until a new control byte is written to the part. The control register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros; therefore, when the supplies are connected, the AD7811 is powered down by default. Control Register AD7811 xX* AO PDI PDO | V,;y,,AGND DIFF/SGL CH1 CHO | CONVST | EXTREF *This is a dont care bit. AO PD1, PDO VinwAGND DIF/SGL CH1, CHO CONVST EXTREF REV. A This is the package address bit. It is used in conjunction with the package address pin to allow two AD7811s to share the same serial bus. The AD7811 can also share the same serial bus with the AD7812. When a control word is written to the control register of the AD7811 the control word is ignored if the package address bit in the con- trol byte does not match how the package address pin is hardwired. Only the serial port of the device that received the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus on the next serial read. When the part powers up this bit is set to 0. These bits allow the AD7811 to be fully powered down and powered up. Bit combinations PD1 = PDO = 0 and PD1 = PDO = 1 override the automatic power-down decision at the end of conversion. These bits also decide the power-down mode when the AD7811 enters a power-down at the end of a conversion. There are two power-down modesFull Power-Down and Partial Power-Down. See Power-Down Options section of this data sheet. PD1 PDO Description 0 0 Full Power-Down of the AD7811 0 1 Partial Power-Down at the End of Conversion 1 0 Full Power-Down at the End of Conversion 1 1 Power-Up the AD7811 The DIF/SGL bit in the control register must be set to 0 to use this option otherwise this bit is ignored. Setting Vinz/AGND to 0 configures the analog inputs of the AD7811 as four single-ended analog inputs referenced to analog ground (AGND). By setting this bit to 1 the input channels Vpy; to Vyy3 are configured as three pseudo- differential channels with respect to Vyy4see Table I. This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0 the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to Vina as explained above. Setting this bit to 1 configures the analog input channels as two pseudo differential pairs Vini/Vinz and Viy3/Vinasee Table I. These bits are used in conjunction with Vypy4/AGND and DIF/SGL to select an analog input channel. The table shows how the various channel selections are madesee Table I. Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initiated in the same serial write. The bit is reset after the end of a conversion. This bit must be set to a logic one if the user wishes to use an external reference or use Vpp as the reference. When the external reference is selected the on chip reference circuitry powers down.AD7811/AD7812 Control Register (AD7812) The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7812 receives a falling edge on its TFS pin. The AD7812 will maintain the same configuration until a new control byte is written to the part. The control register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros; therefore, when the supplies are connected, the AD7812 is powered down by default. Control Register AD7812 0 AO PD1 PDO |Vyn/AGND DIFF/SGL CH2 CHI CHO | CONVST | EXTREF AO PD1, PDO Vins/AGND DIF/SGL CH2, CH1, CHO CONVST EXTREF This is the package address bit. It is used in conjunction with the package address pin to allow two AD7812s to share the same serial bus. The AD7812 can also share the same serial bus with the AD7811. When a control word is written to the control register of the AD7812 the control word is ignored if the package address bit in the con- trol byte does not match how the package address pin is hardwired. Only the serial port of the device which re- ceived the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus on the next serial read. When the part powers up this bit is set to 0. These bits allow the AD7812 to be fully powered down and powered up. Bit combinations PD1 = PDO = 0 and PD1 = PDO = 1 override the automatic power-down decision at the end of conversion. These bits also decide the power-down mode when the AD7812 enters a power-down at the end of a conversion. There are two power-down modesFull Power-Down and Partial Power-Down. See Power-Down section of this data sheet. PD1 PDO Description Full Power-Down of the AD7812 Partial Power-Down at the End of Conversion Full Power-Down at the End of Conversion Power-Up the AD7812 ere OS RP Or The DIF/SGL bit in the control register must be set to 0 in order to use this option otherwise this bit is ignored. Setting Viys/AGND to 0 configures the analog inputs of the AD7812 as eight single-ended analog inputs referenced to analog ground (AGND). By setting this bit to 1 the input channels Vpy; to Vyy7 are configured as seven pseudo differential channels with respect to Vpygsee Table II. This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0 the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to Ving as explained above. Setting this bit to 1 configures the analog input channels as four pseudo differential pairs Vini/Vinvs Vins/Vinas Vins/Vine and Vin7/Vingsee Table II. These bits are used in conjunction with Viys/AGND and DIF/SGL to select an analog input channel. Table II shows how the various channel selections are made. Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initi- ated in the same write operation. The bit is reset after the end of a conversion. This bit must be set to a logic one if the user wishes to use an external reference or use Vpp as the reference. When the external reference is selected the on-chip reference circuitry powers down and the current consumption is reduced by about 1 mA. -8- REV. AAD7811/AD7812 Table I. AD7811 Channel Configurations VingIAGND DIF/SGL CH1 CHO Description 0 0 0 0 Vin: Single-Ended with Respect to AGND 0 0 0 1 Vinz Single-Ended with Respect to AGND 0 0 1 0 Vin; Single-Ended with Respect to AGND 0 0 1 1 Vina Single-Ended with Respect to AGND 1 0 0 0 Vin; Pseudo Differential with Respect to Vaya 1 0 0 1 Ving Pseudo Differential with Respect to Via 1 0 1 0 Vin3 Pseudo Differential with Respect to Vays X 1 0 0 Vini(+) Pseudo Differential with Respect to Viy2(-) X 1 0 1 Vin3(+) Pseudo Differential with Respect to ViyaC) xX 1 1 0 Internal Test. SAR Input Equal to Vpgp/2 xX 1 1 1 Internal Test. SAR Input Equal to Varr Table II. AD7812 Channel Configurations Vins[AGND DIF/SGL CH2 CHI CHO Description MX dK Kd OOOO OOOO mee eee re OoCooeococococococoococmlctOCCOCoclcUCOCC OCD Vin: Single-Ended with Respect to AGND Vinz Single-Ended with Respect to AGND Vin; Single-Ended with Respect to AGND Vina Single-Ended with Respect to AGND Vins Single-Ended with Respect to AGND Vine Single-Ended with Respect to AGND Vin7 Single-Ended with Respect to AGND Ving Single-Ended with Respect to AGND Vin; Pseudo Differential with Respect to Viyg Ving Pseudo Differential with Respect to Viyg Vin3 Pseudo Differential with Respect to Viyg Vina Pseudo Differential with Respect to Viyg Vins Pseudo Differential with Respect to Viyg Vine Pseudo Differential with Respect to Viyg Vin7 Pseudo Differential with Respect to Viyg Vini (+) Pseudo Differential with Respect to Viy2-) Vin3(+) Pseudo Differential with Respect to ViyaC) Vins(+) Pseudo Differential with Respect to Vpye6(-) Vin7(+) Pseudo Differential with Respect to Vpyg(-) Internal Test. SAR Input Equal to Vpzp/2 Internal Test. SAR Input Equal to Varr ere OOCOCT OFF FP OCC COF Fe rer OOO Se Oorrocrcocoocorr oor rR CO OrFRFHKH COO FP OrOrCOCOrF OF OF Or OF Or Or REV. AAD7811/AD7812 CIRCUIT DESCRIPTION Converter Operation The AD7811 and AD7812 are successive approximation analog- to-digital converters based around a charge redistribution DAC. The ADCs can convert analog input signals in the range 0 V to Vpp. Figures 2 and 3 show simplified schematics of the ADC. Figure 2 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A, the comparator is held in a balanced condition and the sampling capacitor acquires the signal on Vy. CHARGE REDISTRIBUTION DAC SAMPLING A CAPACITOR Vy OO-_o_] IN swt CONTROL LoGic BP? ACQUISITION PHASE SW2 | COMPARATOR AGND CLOCK osc Vpp/3 Figure 2. ADC Acquisition Phase When the ADC starts a conversion, see Figure 3, SW2 will open and SW1 will move to position B causing the comparator to become unbalanced. The Control Logic and the Charge Redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebal- anced, the conversion is complete. The Control Logic generates the ADC output code. Figure 10 shows the ADC transfer function. CHARGE REDISTRIBUTION DAC SAMPLING A CAPACITOR Yin O CONTROL swi B Loaic CONVERSION PHASE COMPARATOR sw2 AGND CLOCK osc Vpp/3 Figure 3. ADC Conversion Phase TYPICAL CONNECTION DIAGRAM Figure 4 shows a typical connection diagram for the AD7811/ AD7812. The AGND and DGND are connected together at the device for good noise suppression. The serial interface is implemented using three wires with RFS/TFS connected to CONVST see Serial Interface section for more details. Vag is connected to a well decoupled Vpp pin to provide an analog input range of 0 V to Vpp. If the AD7811 or AD7812 is not sharing a serial bus with another AD7811 or AD7812 then AO (package address pin) should be hardwired low. The default power up value of the package address bit in the control register is 0. For applications where power consumption is of concern, the automatic power down at the end of a conversion should be used to improve power performance. See Power-Down Options section of the data sheet. -10- SUPPLY +2.7V TO 45.5V THREE-WIRE 10pF =5 0-1pF 10nF SERIAL v v v INTERFACE Voo VREF Crer SCLK Vint V DOUT ov To e INQ AD7811/ Vrer Ap7812.ODIN HC/pP INPUT e ) Vina) CONVST RFS TFS AO Figure 4. Typical Connection Diagram Analog Input Figure 5 shows an equivalent circuit of the analog input struc- ture of the AD7811 and AD7812. The two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This will cause these diodes to become forward biased and start conducting current into the substrate. 20 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. How- ever, it is worth noting that a small amount of current (1 mA) being conducted into the substrate due to an overvoltage on an unselected channel can cause inaccurate conversions on a se- lected channel. The capacitor C2 in Figure 5 is typically about 4 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a multiplexer and a switch. This resistor is typically about 125 Q. The capacitor C1 is the ADC sampling capacitor and has a capacitance of 3.5 pF. Yop D1 Rt 35 F 1250 oP Vin K vp 08 D2 CONVERSION PHASE - SWITCH OPEN TRACK PHASE SWITCH CLOSED Figure 5. Equivalent Analog Input Circuit The analog inputs on the AD7811 and AD7812 can be config- ured as single ended with respect to analog ground (AGND), as pseudo differential with respect to a common, and also as pseudo differential pairssee Control Register section. REV.AAD7811/AD7812 An example of the pseudo differential scheme using the AD7811 is shown in Figure 6. The relevant bits in the AD7811 Control Register are set as follows DIF/SGL = 1, CH1 = CH2 = 0, ie., Vini pseudo differential with respect to Viy2. The signal is ap- plied to Vyy, but in the pseudo differential scheme the sampling capacitor is connected to Vy, during conversion and not AGND as described in the Converter Operation section. This input scheme can be used to remove offsets that exist in a system. For example, if a system had an offset of 0.5 V the offset could be applied to Viz and the signal applied to Vpy,. This has the effect of offsetting the input span by 0.5 V. It is only possible to offset the input span when the reference voltage is less than Vpp-OFFSET. CHARGE REDISTRIBUTION DAC SAMPLING CAPACITOR CONTROL LOGIC Vv CONVERSION IN PHASE COMPARATOR V, Vv CLOCK Vpp/3 Vv Figure 6. Pseudo Differential Input Scheme When using the pseudo differential input scheme the signal on Vinz Must not vary by more than a 1/2 LSB during the conver- sion process. If the signal on Vyy2 varies during conversion, the conversion result will be incorrect. In single-ended mode the sampling capacitor is always connected to AGND during con- version. Figure 7 shows the AD7811/AD7812 pseudo differen- tial input being used to make a unipolar de current measurement. A sense resistor is used to convert the current to a voltage and the voltage is applied to the differential input as shown. Vop Oo __JJ Vins AD7811/ AD7812 T Vine RLS . 5 ' Figure 7. DC Current Measurement Scheme > Rsense 2 > DC Acquisition Time The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the end of a conversion a settling time is associated with the sam- pling circuit. This settling time lasts approximately 100 ns. The analog signal on Vyy: is also being acquired during this settling time. Therefore, the minimum acquisition time needed is ap- proximately 100 ns. REV. A Figure 8 shows the equivalent charging circuit for the sampling capacitor when the ADC is in its acquisition phase. R2 repre- sents the source impedance of a buffer amplifier or resistive network; R1 is an internal multiplexer resistance, and C1 is the sampling capacitor. During the acquisition phase the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it takes to charge the sampling capacitor (TeparcE) is given by the following formula: T CHARGE =7.6x (R2 +125 Q) x 3.5 pr R1 Vins 1250 O O c1 -L SAMPLING 3.5pF JL CAPACITOR Figure 8. Equivalent Sampling Circuit For small values of source impedance, the settling time associ- ated with the sampling circuit (100 ns) is, in effect, the acquisi- tion time of the ADC. For example, with a source impedance (R2) of 10 Q the charge time for the sampling capacitor is approximately 4 ns. The charge time becomes significant for source impedances of 2 kQ and greater. AC Acquisition Time In ac applications it is recommended to always buffer analog input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. In addition, better perfor- mance can generally be achieved by using an External 1 nF capacitor on Vy. ON-CHIP REFERENCE The AD7811 and AD7812 have an on-chip 2.5 V reference circuit. The schematic in Figure 9 shows how the reference circuit is implemented. A 1.23 V bandgap reference is gained up to provide a 2.5 V + 2% reference voltage. The on-chip refer- ence is not available externally (SW2 is open). An external refer- ence (1.2 V to Vpp) can be applied at the Vggr pin. However in order to use an external reference the EXTREF bit in the con- trol register (Bit 0) must first be set to a Logic 1. When EXTREF is set to a Logic 1 SW2 will close, SW3 will open and the ampli- fier will power down. This will reduce the current consumption of the part by about 1 mA. It is possible to use two different reference voltages by selecting the on-chip reference or external reference. EXTERNAL CAPACITOR swi 1.23V [ 2.5V Figure 9. On-Chip Reference Circuitry -11-AD7811/AD7812 When using automatic power-down between conversions to improve the power performance of the part (see Power vs. Throughput) the switch SW1 will open when the part enters its power-down mode if using the internal on-chip reference. This provides a high impedance discharge path for the external ca- pacitor (see Figure 9). A typical value of external capacitance is 10 nF. When the part is in Mode 2 Full Power-Down, because the external capacitor holds its charge during power-down, the internal bandgap reference will power up more quickly after relatively short periods of full power-down. When operating the part in Mode 2 Partial Power-Down the external capacitor is not required as the on-chip reference stays powered up while the rest of the circuitry powers down. ADC TRANSFER FUNCTION The output coding of the AD7811 and AD7812 is straight binary. The designed code transitions occur at successive inte- ger LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = Verp/ 1024. The ideal transfer characteristic for the AD7811 and AD7812 is shown in Figure 10. 111...111 111...110 111...000 4LSB = Vper/1024 ADC CODE ee 011...111 e 000...010 000...001 000...000 S T ov 1LSB +Vper-1LSB ANALOG INPUT Figure 10. AD7811 and AD7812 Transfer Characteristic e POWER-DOWN OPTIONS The AD7811 and AD7812 provide flexible power management to allow the user to achieve the best power performance for a given throughput rate. The power management options are selected by programming the power-down bits (i.e., PD1 and PDO) in the control register. Table III below summarizes the options available. When the power-down bits are programmed for Mode 2 Power Down (full and partial), a rising edge on the CONVST pin will power up the part. This feature is used when powering down between conversionssee Power vs. Throughput. When the AD7811 and AD7812 are placed in partial power-down the on-chip reference does not power down. However, the part will power up more quickly after long periods of power-down when using partial power-downsee Power-Up Times section. Table III. AD7811/AD7812 Power-Down Options POWER-UP TIMES The AD7811 and AD7812 have a 1 Us power-up time when using an external reference or when powering up from partial power-down. When Vpp is first connected, the AD7811 and AD7812 are in a low current mode of operation. In order to carry out a conversion the AD7811 and AD7812 must first be powered up by writing to the control register of each ADC to set the power-down bits (i.e., PD1 = 1, PDO = 1) for a full power-up. See the Quick Evaluation Setup section on the fol- lowing page. Mode 2 Full Power-Down (PD1 = 1, PDO = 0) The power-up time of the AD7811 and AD7812 after power is first connected, or after a long period of Full Power-Down, is the time it takes the on-chip 1.23 V reference to power up plus the time it takes to charge the external capacitor Cppysee Figure 9. The time taken to charge Cggp to the 10-bit level is given by the equation (7.6 X 2 kQ X Crzr). For Crgz = 10 nF the power-up time is approximately 152 ps. It takes 30 ps to power up the on-chip reference so the total power-up time of either ADC in either of these conditions is 182 us. However, when powering down fully between conversions to achieve a better power performance this power-up time reduces to 1 us after a relatively short period of power-down as Cppr holds its charge (see On-Chip Reference section). The AD7811 and AD7812 can therefore be used in Mode 2 with throughput rates of 250 kSPS and under. Mode 2 Partial Power-Down (PD1 = 0, PDO = 1) The power-up time of the AD7811 and AD7812 from a Partial Power-Down is 1 4s maximum. When using a Partial Power- Down between conversions, there is no requirement to connect an external capacitor to the Cgz pin because the reference remains powered up. This means that the AD7811 and AD7812 will power up in 30 us after the supplies are first connected as there is no requirement to charge an external capacitor. POWER VS. THROUGHPUT By using the Automatic Power-Down (Mode 2) at the end of a conversionsee Operating Modes section of the data sheet, superior power performance can be achieved. Figure 11 shows how the Automatic Power-Down is imple- mented using the CONVST signal to achieve the optimum power performance for the AD7811 and AD7812. The AD7811 and AD7812 are operated in Mode 2 and the control register Bits PD1 and PD0 are set to 1 and 0 respectively for Full Power- Down, or 0 and 1 for Partial Power-Down. The duration of the CONVST pulse is set to be equal to or less than the power-up time of the devicessee Operating Modes section. As the throughput rate is reduced, the device remains in its power- down state longer and the average power consumption over time drops accordingly. PD1 | PDO | CONVST* | Description te ee poweR-Down* 1 1 x Full Power-Up pr fe \ 0 0 x Full Power-Down teyeLe 0 1 0 Mode 2 Partial Power-Down 100,18 @ 10kSPS (Reference Stays Powered-Up) Figure 11. Automatic Power-Down 0 1 1 No Power-Down 1 0 0 Mode 2 Full Power-Down 1 0 1 No Power-Down *This refers to the state of the CONVST signal at the end of a conversion. -12- REV.AAD7811/AD7812 For example, if the AD7811 is operated in a continuous sam- pling mode with a throughput rate of 10 kSPS, PD1 = 1, PDO = 0 and using the on chip reference the power consump- tion is calculated as follows. The power dissipation during nor- mal operation is 10.5 mW, Vpp = 3 V. If the power-up time is 1 us and the conversion time is 2.3 us, the AD7811 can be said to dissipate 10.5 mW for 3 us (worst case) during each conver- sion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 us and the average power dissipated during each cycle is (3/100) x (10.5 mW) = 315 uw. Figure 12 shows the Power vs. Throughput Rate for automatic full power-down. 10 POWER - mV 0.01 0 5 10 15 20 25 30 35 40 45 50 THROUGHPUT - kSPS Figure 12. AD7811/AD7812 Power vs. Throughput 0 AD7811/12 2048 POINT FFT -20 SAMPLING 357.142kHz fin = 30.168kHz -10 -30 40 dBs 50 -60 o 617 35 582 70 87 105 122 140 157 174 FREQUENCY kHz Figure 13. AD7811/AD7812 SNR QUICK EVALUATION SETUP The schematic shown in Figure 14 shows a suggested configura- tion of the AD7812 for a first look evaluation of the part. No external reference circuit is needed as the Vag pin can be connected to Vpp. The CONVST signal is connected to TFS and RFS to enable the serial port. Also by selecting Mode 2 operation (see Operating Modes section) the power perfor- mance of the AD7812 can be evaluated. REV. A Figure 14. Evaluation Quick Setup The setup uses a full duplex, 16-bit, serial interface protocol, e.g., SPI. It is possible to use 8-bit transfers by carrying out two consecutive read/write operations. The MSB of data is trans- ferred first. 1. When power is first connected to the device it is in a powered down mode of operation and is consuming only 1 uA. The AD7812 must first be configured by carrying out a serial write operation. 2. The CONVST signal is first pulsed to enable the serial port (rising and falling edge on RFS and TFS respectivelysee Serial Interface section). 3. Next, a 16-bit serial read/write operation is carried out. By writing 6040 Hex to the AD7812 the part is powered up, set up to use external reference (i.e., Vpp) and the analog input Vini is selected. The data read from the part during this read/ write operation is invalid. 4. It is necessary to wait approximately 1 ps before pulsing CONVST again and initiating a conversion. The 1 ps is to allow the AD7812 to power up correctlysee Power-Up Times section. 5. Approximately 2.3 us after the falling edge of CONVST, i.e., after the end of the conversion, a serial read/write can take place. This time 4040 Hex is written to the AD7812 and the data read from the part is the result of the conversion. The output code is in a straight binary format and will be left justified in the 16-bit serial register (MSB clocked out first). 6. By idling the CONVST signal high or low it is possible to operate the AD7812 in Mode 1 and Mode 2 respectively. -~13-AD7811/AD7812 OPERATING MODES The mode of operation of the AD7811 and AD7812 is selected when the (logic) state of the CONVST is checked at the end of a conversion. If the CONVST signal is logic high at the end of a conversion, the part does not power down and is operat- ing in Mode 1. If, however, the CONVST signal is brought logic low before the end of a conversion, the AD7811 and AD7812 will power down at the end of the conversion. This is Mode 2 operation. Mode 1 Operation (High Speed Sampling) When the AD7811 and AD7812 are operated in Mode 1 they are not powered down between conversions. This mode of op- eration allows high throughput rates to be achieved. The timing diagram in Figure 16 shows how this optimum throughput rate is achieved by bringing the CONVST signal high before the end of the conversion. The sampling circuitry leaves its tracking mode and goes into hold on the falling edge of CONVST. A conversion is also initi- ated at this time. The conversion takes 2.3 us to complete. At this point, the result of the current conversion is latched into the serial shift register and the state of the CONVST signal checked. The CONVST signal should be logic high at the end of the conversion to prevent the part from powering down. The serial port on the AD7811 and AD7812 is enabled on the rising edge of the first SCLK after the rising edge of the RFS signalsee Serial Interface section. As explained earlier, this rising edge should occur before the end of the conversion process if the part is not to be powered down. A serial read can take place at any stage after the rising edge of CONVST. If a serial read is initi- ated before the end of the current conversion process (i.e., at time A), the result of the previous conversion is shifted out on the DOUT pin. It is possible to allow the serial read to extend beyond the end of a conversion. In this case the new data will not be latched into the output shift register until the read has finished. The dynamic performance of the AD7811 and AD7812 typically degrades by up to 3 dBs while reading during a conversion. If the user waits until the end of the conversion process, i.e., 2.3 us after the falling edge of CONVST (Point B) before initiating a read, the current conversion result is shifted out. The serial read must finish at least 100 ns prior to the next falling edge of CONVST to allow the part to accurately acquire the input signal. Mode 2 Operation (Automatic Power-Down) When used in this mode of operation the part automatically powers down at the end of a conversion. This is achieved by leaving the CONVST signal low until the end of the conversion. Because it takes approximately 1 us for the part to power-up after it has been powered down, this mode of operation is in- tended to be used in applications where slower throughput rates are required, i.e., in the order of 250 kSPS and improved power performance is requiredsee Power vs. Throughput section. There are two power-down modes the AD7811/AD7812 can Yoo tpowen-up rT us { {convert 2.3p3 2.38 tconverT 4a CONVST 1 5 4040 HEX 4040 HEX DIN 6040 HEX 6 VALID DATA DOUT NOT VALID Lg VALID DATA Figure 15. Read/Write Sequence for AD7812 >{|{| ty CONVST ble ws AU. ( DOUT \ CURRENT CONVERSION RESULT Figure 16. Mode 1 Operation Timing Diagram -14 REV.AAD7811/AD7812 enter during automatic power-down. These modes are discussed in the Power-Up Times section of this data sheet. The timing diagram in Figure 17 shows how to operate the part in Mode 2. If the AD7811/AD7812 is powered down, the rising edge of the CONVST pulse causes the part to power-up. Once the part has powered up (~1 us after the rising edge of CONVST) the CONVST signal is brought low and a conver- sion is initiated on this falling edge of the CONVST signal. The conversion takes 2.3 us and after this time the conversion result is latched into the serial shift register and the part powers down. Therefore, when the part is operated in Mode 2 the effective conversion time is equal to the power-up time (1 ts) and the SAR conversion time (2.3 us). NOTE: Although the AD7811 and AD7812 take 1 Us to power up after the rising edge of CONVST, it is not necessary to leave CONVST high for 1 ps after the rising edge before bringing it low to initiate a conversion. If the CONVST signal goes low before 1 ps in time has elapsed, then the power-up time is timed out internally and a conversion is then initiated. Hence the AD7811 and AD7812 are guaranteed to have always powered- up before a conversion is initiated, even if the CONVST pulse- width is <1 ps. If the CONVST pulsewidth is > 1 pis, then a conversion is initiated on the falling edge. As in the case of Mode 1 operation, the rising edge of the first SCLK after the rising edge of RFS enables the serial port of the AD7811 and AD7812 (see Serial Interface section). If a serial read is initiated soon after this rising edge (Point A), i-e., before the end of the conversion, the result of the previous con- version is shifted out on pin DOUT. In order to read the result of the current conversion, the user must wait at least 2.3 us after power-up or at least 2.3 us after the falling edge of CONVST, ee tpower-uP (Point B), whichever occurs latest before initiating a serial read. The serial port of the AD7811 and AD7812 is still func- tional even though the devices have been powered down. Because it is possible to do a serial read from the part while it is powered down, the AD7811 and AD7812 are powered up only to do the conversion and are immediately powered down at the end of a conversion. This significantly improves the power consumption of the part at slower throughput ratessee Power vs. Throughput section. SERIAL INTERFACE The serial interface of the AD7811 and AD7812 consists of five wires, a serial clock input, SCLK, receive data to clock syn- chronization input RES, transmit data to clock synchronization input TFS, a serial data output, DOUT, and a serial data in- put, DIN, (see Figure 18). The serial interface is designed to allow easy interfacing to most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI, SPI, DSP56000, TMS320 and ADSP-21xx, without the need for any gluing logic. When interfacing to the 8051, the SCLK must be inverted. The Microprocessor/Microcontroller Interface section explains how to interface to some popular DSPs and microcontrollers. Figure 18 shows the timing diagram for a serial read and write to the AD7811 and AD7812. The serial interface works with both a continuous and a noncontinuous serial clock. The rising edge of RFS and falling edge of TFS resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. Once the correct number of bits have been shifted in and out, the SCLE is ignored. In order for another serial transfer to take place the counter must be reset by the active edges of TFS and dps ty CONVST (a PP] & SCLK <C @ : DOUT & ( CURRENT CONVERSION \ RESULT Figure 17. Mode 2 Operation Timing Diagram " 7 8 9 10 1 12 ) 13 , ' aa tio > DB7 xX DB6 xX DBS x DB4 x DB3 xX DB2 Xx DB1 x DBO yo ts Figure 18. Serial Interface Timing Diagram ~15- REV. AAD7811/AD7812 RES. The first rising SCLK edge after the rising edge of the RES signal causes DOUT to leave its high impedance state and data is clocked out onto the DOUT line and also on subsequent SCLK rising edges. The DOUT pin goes back into a high im- pedance state on the 11th SCLK rising edgePoint A on Figure 18. A minimum of 11 SCLKs are therefore needed to carry out a serial read. Data on the DIN line is latched in on the first SCLK falling edge after the falling edge of the TFS signal and on subsequent SCLK falling edges. The control register is updated on the 13th SCLK rising edgepoint B on Figure 18. A minimum of 13 SCLK pulses are therefore needed to complete a serial write operation. In multipackage applica- tions the RFS and TFS signals can be used as chip select sig- nals. The serial interface will not shift data in or out until it receives the active edge of the RFS or TFS signal. Simplifying the Serial Interface The five-wire interface is designed to support many different serial interface standards. However, it is possible to reduce the number of lines required to just three. By simply connecting the TFS and RFS pins to the CONVST signal (see Figure 4), the CONVST signal can be used to enable the serial port for read- ing and writing. This is only possible where a noncontinuous serial clock is being used. MICROPROCESSOR INTERFACING The serial interface on the AD7811 and AD7812 allows the parts to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7811 and AD7812 with some of the more common micro- controller and DSP serial interface protocols. AD7812/AD7811 to PIC16C6x/7x The PIC16C6x Synchronous Serial Port (SSP) is configured as an SPI Master with the Clock Polarity bit = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See user PIC16/17 Microcontroller User Manual. Figure 19 shows the hardware connections needed to interface to the PIC16/17. In this example I/O port RAI is being used to pulse CONVST and enable the serial port of the AD7811/ AD7812. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive read/write operations are needed. AD7811/AD7812* PIC16C6x/7x* SCLK SCK/RC3 DOUT SDO/RC5 DIN SDI/ RC4 CONVST RA1 RFS TFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 19. Interfacing to the PIC16/17 -16- AD7811/AD7812 to MC68HC11 The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for Master Mode (MSTR = 0), Clock Polarity Bit (CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is configured by writing to the SPI Control Register (SPCR)see 68HC11 user manual. A connection diagram is shown in Figure 20. AD7811/AD7812* MC68HC11* SCLK SCLK/PD4 DOUT MISO/PD2 DIN MOSI/PD3 CONVST PAO RFS TFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 20. Interfacing to the MC68HC11 AD7811/AD7812 to 8051 The AD7811/AD7812 requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode serial data enters and exits through RxD and a shift clock is output on TxD (half duplex). Figure 21 shows how the 8051 is connected to the AD7811/AD7812. However, because the AD7811/AD7812 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. AD7811/AD7812* 8051* SCLK TxD DOUT RxD DIN RFS P__0O P1.1 TFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 21. Interfacing to the 8051 Serial Port REV.AAD7811/AD7812 It is possible to implement a serial interface using the data ports on the 8051. This would also allow a full duplex serial transfer to be implemented. The technique involves bit banging an I/O port (e.g., P1.0) to generate a serial clock and using two other I/O ports (e.g., P1.1 and P1.2) to shift data in and out see Figure 22. AD7811/AD7812* SCLK DOUT DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. Interfacing to the 8051 Using I/O Ports AD7811/AD7812 to TMS320C5x The serial interface on the TMS320C5x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7811. Frame synchronization inputs have been supplied on the AD7811/AD7812 to allow easy interfacing with no extra gluing logic. The serial port of the TMS320C5x is set up to operate in Burst Mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The Serial Port Control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1 and TXM = 1. The connection diagram is shown in Figure 23. AD7811/AD7812* TMS320C5x* SCLK CLKX CLKR DOUT DIN RFS TFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 23. Interfacing to the TMS320C5x REV. A AD7811/AD7812 to ADSP-21xx The ADSP-21xx family of DSPs are easily interfaced to the AD7811/AD7812 without the need for extra gluing logic. The SPORT is operated in normal framing mode. The SPORT control register should be set up as follows: TFSW = RESW = 0, Normal Framing INVRES = INVTES = 0, Active High Frame Signal DTYPE = 00, Right Justify Data SLEN = 1001, 10-Bit Data Words ISCLK = 1, Internal Serial Clock TFSR = RESR = 1, Frame Every Word IRFS = 0, External Framing Signal ITFS = 1, Internal Framing Signal The 10-bit data words will be right justified in the 16-bit serial data registers when using this configuration. Figure 24 shows the connection diagram. AD7811/AD7812* ADSP-21xx* SCLK SCLK DOUT DR DIN DT RFS RFS TFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 24. Interfacing to the ADSP-21xx AD7811/AD7812 to DSP56xxx The connection diagram in Figure 25 shows how the AD7811 and AD7812 can be connected to the SSI (Synchronous Serial Interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in Synchronous Mode (SYN bit in CRB =1) with internally generated 1-bit clock period frame sync for both Tx and Rx (FSL1 and FSLO bits in CRB = 1 and 0 respectively). AD7811/AD7812* DSP56xxx* SCLK ScK DOUT SRD DIN STD RFS sc2 TFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 25. Interfacing to the DSP56xxx -17-AD7811/AD7812 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) & 4 2 2. 4 4 *) 10.280 (7.11) e! 3 |0-240 (6.10) 0.325 (8.25) wyF PF FF 7 0.300 (7.62) 0.195 (4.95) PIN1 0.060 (1.52) <= 0.115 (2.93) ~~ 0.210 (5.33) 0.015 (0.38) maxy WL LY LL LY LU LF 0.130 2h 0.160 (4.06) A LE (3.30) 0.115 (2.93) "hie tke = MIN 0.015 (0.381) 0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204) 0.074 (0.356) (2:54) 0.045(1.15) PLANE BSC 16-Lead Small Outline Package (SOIC) (R-16A) 0.3937 (10.00) 0.3859 (9.80) - ARAAARAAA GA A 16 9 0.1574 (4.00) 0.2550 (6.20) 0.1497 (5.80) JT 8|| 0.2284 (5.80) HR Ha Hod PIN 1 0.0688 (1.75) 0.0196 (0.50) 0.0098 (0.25) 0.0532 (1.35) *| 0.0099 (0.25) ** 0.0040 (0.10) > \ ae + 7 C050 9.0192 (0.49) 0.0099 (0.25) 0.0500 (1.27) SEATING (1.27) 9.0138 (0.35) ee PLANE Bsc . . 0.0075 (0.19) 0.0160 (0.41) 16-Lead Thin Shrink Outline Package (TSSOP) (RU-16) 0.201 (5.10) *~ 0.193 (4.90) - 16 9 _ >| 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 3 PIN 1 0.006 (0.15) 0.002 (0.05) spot 0.0433 t (1.10) FA be max ot + 0.028 (0.70) Fi SEATING 0.0256 0.0118 (0.30) = 0.020 (0.50) PLANE (2:85) 0.0075 (0.19) 9.0079 (0.20) BSC 0.0035 (0.090) -18- REV.AAD7811/AD7812 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic DIP (N-20) 1.060 (26.90) 0.925 (23.50) . AAA ea ee eee 20 110.280 (7.11) 0.240 (6.10 e! 10 (6-10) 0.325 (8.25) Wing TT oe 7 yy 0.300 (7.62) 0.195 (4.95) 0.060 (1.52) << 0.115 (2.93) 0.210 (5.33) 0-015 (0.38) f MAX y WH A AH A 0.130 0.160 (4.06) J . XN (3.30) 0.115 (2.93) tee et ee 7\e MIN 0.015 (0.381) 0.022 (0.558) 0.100 0.070(1.77) SEATING 0.008 (0.204) 0.074 (0.356) (254) 01045 (1.15) PLANE BSC 20-Lead Small Outline Package (SOIC) (R-20A) 0.5118 (13.00) 0.4961 (12.60) fAiAARAAR AAA 20 11 0.2992 (7.60) 0.2914 (7.40) Ig 0.4193 (10.65) 0.3937 (10.00) 1 10 Hu HH HH EY YY PIN1 0.1043 (2.65) 0.0291 (0.74) 0.0926 (2.35) *| [Fs.00s8 0.25 0.0098 (0.25) + - et he Sa Hy 8 0.0500(1.27) 0.0118 (0.30) 0.0500 0.0192 (0.49) 0 0.0157 (0.40) 0.0040 (0.10) SEATING 0.0040(0.10) 227) 0.0138 (0.35) PLANE 0.0125 aor 032 32) 0.0091 (0.23) x 45 20-Lead Thin Shrink Outline Package (TSSOP) (RU-20) 0.260 (6.60) 0.252 (6.40) PRR RRR hhh | ,| 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) _t 0.006 (0.15) PIN 14 0.002 (0.05) 0.0433 4 SPEAR Go yA, - f le the , 0.028 (0.70) lle 0.0256 (0.65) 0.0118 (0.30) o 0.020(0.50 SEATING BSC 0.0075 (0.19) 9.0079 (0.20) (0.50) PLAN 0.0035 (0.090) REV. A -19-86/L L-O-88ELED v's'N NI GALNIYd ~20-