9300/DM9300 4-Bit Parallel-Access Shift Register General Description The 9300 4-bit registers feature parallel inputs, parallel outputs, JK serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load and shift (in direction QA toward QD). Parallel loading is accomplished by applying the four bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flops, and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the JK inputs. These inputs permit the first stage to perform as a JK, D or T-type flip-flop as shown in the function table. These shift registers are fully compatible with most other TTL and DTL families. All inputs, including the clock, are buffered to lower the drive requirements to one normalized Series 54/74 load. Features Fully buffered inputs Direct overriding clear Synchronous parallel load Parallel inputs and outputs from each flip-flop Positive edge-triggered clocking J and K inputs to first stage Typical shift frequency39 MHz Y Y Y Y Y Y Y Connection Diagram Dual-In-Line Package Order Number 9300DMQB, 9300FMQB or DM9300N See NS Package Number J16A, N16E or W16A TL/F/6600 - 1 Function Table Inputs Clear Shift/ Load L H H H H H H Clock X L H H H H H X u L u u u u Outputs Serial Parallel J K P0 P1 P2 P3 X X X L L H H X X X H L H L X a X X X X X X b X X X X X X c X X X X X X d X X X X X QA QB QC QD QD L a QA0 QA0 L H QAn L b QB0 QA0 QAn QAn QAn L c QC0 QBn QBn QBn QBn L d QD0 QCn QCn QCn QBn H d QD0 QCn QCn QCn QCn H e High Level (Steady State) L e Low Level (Steady State) X e Don't Care u e Transition from low-to-high level a, b, c, d, e The level of steady state input at P0, P1, P2, or P3 respectively. QA0, QB0, QC0, QD0 e The level of QA, QB, QC, or QD, respectively before the indicated steady state input conditions were established. QAn, QBn, QCn e The level of QA, QB, QC, respectively, before the most recent transition of the clock. u C1995 National Semiconductor Corporation TL/F/6600 RRD-B30M105/Printed in U. S. A. 9300/DM9300 4-Bit Parallel-Access Shift Register June 1989 Absolute Maximum Ratings (Note) Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Storage Temperature Range 7V 5.5V b 65 C to a 150 C Operating Free Air Temperature Range b 55 C to a 125 C Military Commercial 0 C to a 70 C Recommended Operating Conditions Symbol Military Parameter Commercial Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 V 0.8 0.8 V mA VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current b 0.48 b 0.8 IOL Low Level Output Current 9.6 16 mA fCLK Clock Frequency (Note 5) 30 MHz tW Pulse Width (Note 5) tSU 2 2 0 Setup Time (Note 5) 30 V 0 Clock 17 16 11 Clear 25 30 15 S/L 36 30 13 Data 18 20 13 Clear 36 30 13 b 11 tH Data Hold Time (Note 5) 0 0 tREL S/L Release Time (Notes 1 and 5) 10 10 TA Free Air Operating Temperature b 55 125 ns ns ns ns 0 70 C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 2) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max 0.4 V II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V 1 mA IIH High Level Input Current VCC e Max, VI e 2.4V 40 IIL IOS ICC Low Level Input Current Input VCC e Max, VI e 0.4V Short Circuit Output Current VCC e Max (Note 3) Supply Current VCC e Max (Note 4) 2.4 V CP Input 80 PE Input 92 Input b 1.6 CP Input b 3.2 PE Input b 3.7 MIL b 20 b 80 COM b 18 b 55 MIL 86 COM 92 mA mA mA mA Note 1: RELEASE TIME: tRELEASE is defined as the maximum time allowed for the logic level to be present at the logic input prior to the clock transition from low to high in order for the flip-flop(s) not to respond. Note 2: All typicals are at VCC e 5V, TA e 25 C. Note 3: Not more than one output should be shorted at a time. Note 4: With all outputs open, SHIFT/LOAD grounded, and 4.5V applied to J, K, and data inputs, ICC is measured by applying momentary ground, then 4.5V to CLEAR, and then to CLOCK. Note 5: TA e 25 C and VCC e 5V. 2 Switching Characteristics Symbol Parameter at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output) Military Commercial RL e 400X, CL e 15 pF RL e 400X, CL e 15 pF Min Max 30 Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Output 20 22 ns tPHL Propagation Delay Time High to Low Level Output Clock to Output 24 26 ns tPHL Propagation Delay Time High to Low Level Output Clear to Output 37 30 ns 3 30 MHz DM9300 TL/F/6600 - 2 Schematic Diagram 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 9300DMQB NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM9300N NS Package Number N16E 5 9300/DM9300 4-Bit Parallel-Access Shift Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 9300FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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