9300DMQB - National Semiconductor

TL/F/6600

9300/DM9300 4-Bit Parallel-Access Shift Register

June 1989

9300/DM9300 4-Bit Parallel-Access Shift Register

General Description

The 9300 4-bit registers feature parallel inputs, parallel out-

puts, JK serial inputs, shift/load control input, and a direct

overriding clear. The registers have two modes of operation:

parallel (broadside) load and shift (in direction QAtoward

QD).

Parallel loading is accomplished by applying the four bits of

data and taking the shift/load control input low. The data is

loaded into the associated flip-flops, and appears at the out-

puts after the positive transition of the clock input. During

loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load

control input is high. Serial data for this mode is entered at

the JK inputs. These inputs permit the first stage to perform

asaJK

, D or T-type flip-flop as shown in the function table.

These shift registers are fully compatible with most other

TTL and DTL families. All inputs, including the clock, are

buffered to lower the drive requirements to one normalized

Series 54/74 load.

Features

YFully buffered inputs

YDirect overriding clear

YSynchronous parallel load

YParallel inputs and outputs from each flip-flop

YPositive edge-triggered clocking

YJ and K inputs to first stage

YTypical shift frequencyÐ39 MHz

Connection Diagram

Dual-In-Line Package

TL/F/6600–1

Order Number 9300DMQB,

9300FMQB or DM9300N

See NS Package Number

J16A, N16E or W16A

Function Table

Inputs Outputs

Clear Shift/ Clock Serial Parallel QAQBQCQDQD

Load JKP0 P1 P2 P3

L X X XXXXXX L L L L H

XX a b c d a b c d d

H H L XXXXXXQ

A0 QB0 QC0 QD0 QD0

LHXXXXQ

A0 QA0 QBn QCn QCn

LLXXXX LQ

An QBn QCn QCn

HHXXXX HQ

An QBn QCn QCn

HLXXXXQ

An QAn QBn QBn QCn

HeHigh Level (Steady State)

LeLow Level (Steady State)

XeDon’t Care

eTransition from low-to-high level

a, b, c, d, eThe level of steady state input at P0, P1, P2, or P3 respectively.

QA0,Q

B0,Q

C0,Q

D0 eThe level of QA,Q

,orQ

, respectively before the indicated steady state input conditions were established.

QAn,Q

Bn,Q

Cn eThe level of QA,Q

, respectively, before the most recent

transition of the clock.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 5.5V

Storage Temperature Range b65§Ctoa

150§C

Operating Free Air Temperature Range

Military b55§Ctoa

125§C

Commercial 0§Ctoa

70§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter Military Commercial Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.8 0.8 V

IOH High Level Output Current b0.48 b0.8 mA

IOL Low Level Output Current 9.6 16 mA

fCLK Clock Frequency (Note 5) 0 30 0 30 MHz

tWPulse Width Clock 17 16 11 ns

(Note 5) Clear 25 30 15

tSU Setup Time S/L 36 30 13

(Note 5) Data 18 20 13 ns

Clear 36 30 13

tHData Hold Time (Note 5) 0 0 b11 ns

tREL S/L Release Time (Notes 1 and 5) 10 10 ns

TAFree Air Operating Temperature b55 125 0 70 §C

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VIInput Clamp Voltage VCC eMin, IIeb

12 mA b1.5 V

VOH High Level Output VCC eMin, IOH eMax 2.4 V

Voltage VIL eMax, VIH eMin

VOL Low Level Output VCC eMin, IOL eMax 0.4 V

Voltage VIH eMin, VIL eMax

IIInput Current @Max VCC eMax, VIe5.5V 1 mA

Input Voltage

IIH High Level Input Current VCC eMax, Input 40

VIe2.4V CP Input 80 mA

PE Input 92

IIL Low Level Input Current VCC eMax, Input b1.6

VIe0.4V CP Input b3.2 mA

PE Input b3.7

IOS Short Circuit VCC eMax MIL b20 b80 mA

Output Current (Note 3) COM b18 b55

ICC Supply Current VCC eMax MIL 86 mA

(Note 4) COM 92

Note 1: RELEASE TIME: tRELEASE is defined as the maximum time allowed for the logic level to be present at the logic input prior to the clock transition from low to

high in order for the flip-flop(s)

not

to respond.

Note 2: All typicals are at VCC e5V, TAe25§C.

Note 3: Not more than one output should be shorted at a time.

Note 4: With all outputs open, SHIFT/LOAD grounded, and 4.5V applied to J, K, and data inputs, ICC is measured by applying momentary ground, then 4.5V to

CLEAR, and then to CLOCK.

Note 5: TAe25§C and VCC e5V.

Switching Characteristics at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load)

From (Input)

Military Commercial

Symbol Parameter To (Output) RLe400X,C

Le15 pF RLe400X,C

Le15 pF Units

Min Max Min Max

fMAX Maximum Clock Frequency 30 30 MHz

tPLH Propagation Delay Time Clock to 20 22 ns

Low to High Level Output Output

tPHL Propagation Delay Time Clock to 24 26 ns

High to Low Level Output Output

tPHL Propagation Delay Time Clear to 37 30 ns

High to Low Level Output Output

Schematic Diagram

DM9300

TL/F/6600–2

Physical Dimensions inches (millimeters)

16-Lead Ceramic Dual-In-Line Package (J)

Order Number 9300DMQB

NS Package Number J16A

16-Lead Molded Dual-In-Line Package (N)

Order Number DM9300N

NS Package Number N16E

9300/DM9300 4-Bit Parallel-Access Shift Register

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flat Package (W)

Order Number 9300FMQB

NS Package Number W16A

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with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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