CY7C1021D
1-Mbit (64K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05462 Rev. *E Revised February 22, 2007
Features
• Pin-and function-compatible with CY7C1021B
• High speed
—t
AA = 10 ns
• Low active power
—I
CC = 80 mA @ 10 ns
• Low CMOS Standby Power
—I
SB2 = 3 mA
• 2.0V Data Retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Independent control of upper and lower bits
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin TSOP II packages
Functional Description [1]
The CY7C1021D is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected. The input/output pins
(IO0 through IO15) are placed in a high-impedance state when:
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
•BHE
and BLE are disabled (BHE, BLE HIGH)
• When the write operation is active (CE LOW, and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,
then data from IO pins (IO0 through IO7), is written into the
location specified on the address pins (A0 through A15). If Byte
High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the
address pins (A0 through A15).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7.
If Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 8 for a
complete description of read and write modes.
Logic Block Diagram
64K x 16
RAM Array IO
0
–IO
7
ROW DECODER
A
7
A
6
A
5
A
4
A
3
A
0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
2
A
1
IO
8
–IO
15
CE
WE
BLE
BHE
A
8
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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Document #: 38-05462 Rev. *E Page 2 of 11
Pin Configuration [2]
Selection Guide
–10 (Industrial) –12 (Automotive) [3] Unit
Maximum Access Time 10 12 ns
Maximum Operating Current 80 120 mA
Maximum CMOS Standby Current 315 mA
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
SOJ/TSOP II
Top View
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC NC
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
Notes
2. NC pins are not connected on the die.
3. Automotive Product Information is Preliminary.
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Document #: 38-05462 Rev. *E Page 3 of 11
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND [4] ... –0.5V to +6.0V
DC Voltage Applied to Outputs
in High-Z State [4] .....................................–0.5V to VCC+0.5V
DC Input Voltage [4]..................................–0.5V to VCC+0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40°C to +85°C 5V ± 10% 10 ns
Automotive –40°C to +125°C 12 ns
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
–10 (Industrial) –12 (Automotive)
Unit
Min Max Min Max
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5V 2.0 VCC + 0.5V V
VIL Input LOW Voltage [4] −0.5 0.8 –0.5 0.8 V
IIX Input Leakage Current GND < VI < VCC −1+1–5 +5 µA
IOZ Output Leakage Current GND < VI < VCC, Output Disabled −1+1–5 +5 µA
ICC VCC Operating
Supply Current
VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz 80 -mA
83 MHz 72 120 mA
66 MHz 58 100 mA
40 MHz 37 63 mA
ISB1 Automatic CE Power-down
Current —TTL Inputs
Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fmax
10 50 mA
ISB2 Automatic CE Power-down
Current —CMOS Inputs
Max VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
315 mA
Note
4. VIL (min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
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Document #: 38-05462 Rev. *E Page 4 of 11
Capacitance [5]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 8 pF
COUT Output Capacitance 8 pF
Thermal Resistance [5]
Parameter Description Test Conditions SOJ TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52 53.91 °C/W
ΘJC Thermal Resistance
(Junction to Case)
36.75 21.24 °C/W
AC Test Loads and Waveforms [6]
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: ≤ 3 ns Fall Time: ≤ 3 ns
30 pF*
OUTPUT
Z = 50
Ω
50 Ω
1.5V
(b)
(a)
5V
OUTPUT
5 pF
(c)
R1 480Ω
R2
255Ω
High-Z characteristics:
INCLUDING
JIG AND
SCOPE
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
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Document #: 38-05462 Rev. *E Page 5 of 11
Switching Characteristics (Over the Operating Range) [7]
Parameter Description –10 (Industrial) –12 (Automotive) Unit
Min Max Min Max
Read Cycle
tpower [8] VCC(typical) to the first access 100 100 µs
tRC Read Cycle Time 10 12 ns
tAA Address to Data Valid 10 12 ns
tOHA Data Hold from Address Change 3 3ns
tACE CE LOW to Data Valid 10 12 ns
tDOE OE LOW to Data Valid 5 6ns
tLZOE OE LOW to Low Z [9] 0 0 ns
tHZOE OE HIGH to High Z [9, 10] 56ns
tLZCE CE LOW to Low Z [9] 3 3 ns
tHZCE CE HIGH to High Z [9, 10] 56ns
tPU CE LOW to Power-Up 0 0ns
tPD CE HIGH to Power-Down 10 12 ns
tDBE Byte Enable to Data Valid 5 6ns
tLZBE Byte Enable to Low Z 0 0ns
tHZBE Byte Disable to High Z 5 6ns
Write Cycle [12]
tWC Write Cycle Time 10 12 ns
tSCE CE LOW to Write End 7 10 ns
tAW Address Set-Up to Write End 7 10 ns
tHA Address Hold from Write End 0 0ns
tSA Address Set-Up to Write Start 0 0ns
tPWE WE Pulse Width 7 10 ns
tSD Data Set-Up to Write End 6 7ns
tHD Data Hold from Write End 0 0ns
tLZWE WE HIGH to Low Z [9] 3 3 ns
tHZWE WE LOW to High Z [9, 10] 56ns
tBW Byte Enable to End of Write 7 10 ns
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of “AC Test Loads and Waveforms [6]” on page 4. Transition is measured when
the outputs enter a high impedance state.
11. This parameter is guaranteed by design and is not tested.
12. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the write.
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Document #: 38-05462 Rev. *E Page 6 of 11
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Max Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
Industrial 3 mA
Automotive 15 mA
tCDR [4] Chip Deselect to Data Retention Time 0 ns
tR [13] Operation Recovery Time tRC ns
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [14, 15]
Read Cycle No. 2 (OE Controlled) [15, 16]
4.5V4.5V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
tDBE
tLZBE
tHZCE
HIGH
IMPEDANCE
ICC
ISB
OE
CE
ADDRESS
DATA OUT
VCC
SUPPLY
BHE,BLE
CURRENT
Notes
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs.
14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
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Document #: 38-05462 Rev. *E Page 7 of 11
Write Cycle No. 1 (CE Controlled) [17, 18]
Write Cycle No. 2 (BLE or BHE Controlled)
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
DATA IO
ADDRESS
CE
WE
BHE,BLE
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA IO
ADDRESS
BHE,BLE
CE
WE
Notes
17. Data IO is high impedance if OE or BHE and/or BLE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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Document #: 38-05462 Rev. *E Page 8 of 11
Write Cycle No. 3 (WE Controlled, OE LOW)
Truth Table
CE OE WE BLE BHE IO0–IO7IO8–IO15 Mode Power
H X X X X High Z High Z Power-Down Standby (ISB)
L L H L L Data Out Data Out Read – All bits Active (ICC)
L H Data Out High Z Read – Lower bits only Active (ICC)
H L High Z Data Out Read – Upper bits only Active (ICC)
L X L L L Data In Data In Write – All bits Active (ICC)
L H Data In High Z Write – Lower bits only Active (ICC)
H L High Z Data In Write – Upper bits only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
10 CY7C1021D-10VXI 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1021D-10ZSXI 51-85087 44-pin TSOP Type II (Pb-free)
12 CY7C1021D-10ZSXE 51-85087 44-pin TSOP Type II (Pb-free) Automotive
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Switching Waveforms (continued)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
tSA
tLZWE
tHZWE
DATA IO
ADDRESS
CE
WE
BHE,BLE
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Document #: 38-05462 Rev. *E Page 9 of 11
Package Diagrams
Figure 1. 44-pin (400-Mil) Molded SOJ, 51-85082
51-85082-*B
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CY7C1021D
Document #: 38-05462 Rev. *E Page 10 of 11
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Figure 2. 44-Pin Thin Small Outline Package Type II, 51-85087
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-85087-*A
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CY7C1021D
Document #: 38-05462 Rev. *E Page 11 of 11
Document History Page
Document Title: CY7C1021D, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05462
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 201560 See ECN SWI Advance Information data sheet for C9 IPP
*A 233695 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in the Ordering Information
*B 263769 See ECN RKF Added Data Retention Characteristics Table
Added Tpower Spec in Switching Characteristics Table
Shaded Ordering Information
*C 307601 See ECN RKF Reduced Speed bins to –10 and –12 ns
*D 520647 See ECN VKN Converted from Preliminary to Final
Removed Commercial Operating range
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Added Automotive Product Information
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4
*E 802877 See ECN VKN Changed Commercial operating range ICC spec from 60 mA to 80 mA for
100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to
37 mA for 40MHz
Changed Automotive operating range ICC spec from 100 mA to 120 mA for
83MHz, 90 mA to 100 mA for 66MHz, 60 mA to 63 mA for 40MHz
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