DATA SHEET ICS84021 ICS84021 Integrated 260MHZ, CRYSTAL-TO-LVCMOS Circuit Systems, Inc. LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS84021 is a general purpose, Crystal-toLVCMOS/LVTTL High Frequency Synthesizer HiPerClockSTM and a member of the HiPerClock STM family of High Performance Clock Solutions from ICS. The ICS84021 has a selectable TEST_CLK or crystal input. The VCO operates at a frequency range of 620MHz to 780MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interface to the configuration logic. * 2 LVCMOS/LVTTL outputs ICS * Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK * Output frequency range: 103.3MHz to 260MHz * Crystal input frequency range: 14MHz to 40MHz * VCO range: 620MHz to 780MHz * Parallel or serial interface for programming counter and output dividers * RMS period jitter: 4.3ps (typical) (N / 4, VDDO = 3.3V 5%) * RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz to 20MHz): 2.88ps (typical) Phase noise: 155.52MHz Offset Noise Power 100Hz ................. -93.7 dBc/Hz 1KHz ............... -111.3 dBc/Hz 10KHz ............... -120.4 dBc/Hz 100KHz ............... -125.1 dBc/Hz * Full 3.3V or mixed 3.3V core/2.5V or 1.8V supply voltage * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT XTAL_IN nP_LOAD M0 M1 M2 M3 M4 OE1 VCO_SEL OE0 VCO_SEL 32 31 30 29 28 27 26 25 XTAL_SEL TEST_CLK 0 XTAL_IN OSC 1 XTAL_OUT PLL M5 1 24 XTAL_OUT M6 2 23 TEST_CLK M7 3 22 XTAL_SEL M8 4 21 VDDA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK GND 8 17 MR PHASE DETECTOR 9 10 11 12 13 14 15 16 GND Q0 Q1 VDDO Q0 OE0 1 /3 /4 /5 /6 OE1 /M 0 VDD VCO TEST MR ICS84021 Q1 S_LOAD S_DATA S_CLOCK nP_LOAD CONFIGURATION INTERFACE LOGIC TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View M0:M8 N0:N1 84021AY www.icst.com/products/hiperclocks.html IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 1 1 REV. C JUNE 9, 2005 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The ICS84021 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 620MHz to 780MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 25 M 31. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVCMOS output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84021 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the T1 T0 TEST Output 0 0 LOW 0 1 S_DATA, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout SERIAL LOADING S_CLOCK S_DATA T1 t S_LOAD S T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 t H t nP_LOAD S PARALLEL LOADING M0:M8, N0:N1 M, N nP_LOAD t S t H S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 2 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 2 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER ICS84021 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. TABLE 1. PIN DESCRIPTIONS Number Name 1 2, 3, 4, 28, 29, 30, 31, 32 M5 M6, M7, M8, M0, M1, M2, M3, M4 5, 6 Type Input Description Pullup Input M divider inputs. Data latched on LOW-to-HIGH transition Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. N0, N1 Input Pulldown 7 nc Unused 8, 16 GND Power 9 TEST Output 10 VDD Power 11, 12 OE1, OE0 Input 13 VDDO Power 14, 15 Q0, Q1 Output 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VDDA Power 22 XTAL_SEL Input Pullup 23 24, 25 TEST_CLK XTAL_OUT, XTAL_IN Input Pulldown 26 nP_LOAD Input Pulldown 27 VCO_SEL Input Pullup Pullup Input Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. Power supply ground. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS / LVTTL interface levels. Core supply pin. Output enable. When logic HIGH, the outputs are enabled (default). When logic LOW, the outputs are in Tri-State. See Table 3E, OE Function Table. LVCMOS / LVTTL interface levels. Output supply pin. Clock outputs. LVCMOS / LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels Test clock input. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 3 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 3 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance C PD Power Dissipation Capacitance (per output) RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor ROUT Output Impedance TABLE 3A. PARALLEL Test Conditions AND Minimum Typical Maximum Units 4 pF VDD, VDDA, VDDO = 3.465V 15 pF VDD, VDDA = 3.465V, VDDO = 2.625V 15 pF VDD, VDDA = 3.465V, VDDO = 1.89V 20 pF 51 k 51 k VDDO = 3.465V 7 VDDO = 2.625V 7 VDDO = 1.89V 10 SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L Data Data L X X L H X X L Data L H X X L Data L H X X L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H Data Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1) 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 25 0 0 0 0 1 1 0 0 1 * * * * * * * * * * 700 28 0 0 0 0 1 1 1 0 0 * * * * * * * * * * * VCO Frequency (MHz) M Divide 625 * 775 31 0 0 0 0 1 1 1 1 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz. 84021AY www.icst.com/products/hiperclocks.html 1 REV. C JUNE 9, 2005 4 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 4 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER ICS84021 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (PLL ENABLED) Inputs Output Frequency (MHz) N Divider Value N1 N0 Minimum Maximum 0 0 3 206.7 260 0 1 4 155 195 1 0 5 124 15 6 1 1 6 103.3 130 TABLE 3D. COMMONLY USED CONFIGURATION FUNCTION TABLE Input Output Frequency (MHz) Crystal (MHz) M Divider Value N Divider Value 19.44 32 4 155.52 19.53125 32 4 156.25 25 25 4 156.25 25 25 5 125 25.50 25 3 212.50 25.50 25 4 159.375 25.50 25 6 106.25 38.88 16 4 155.52 TABLE 3E. OUTPUT ENABLE & CLOCK ENABLE FUNCTION TABLE Control Inputs Output OE0 OE1 Q0 0 0 Hi-Z Hi-Z 0 1 Hi-Z Enabled 1 0 Enabled Hi-Z 1 1 Enabled Enabled 84021AY Q1 www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 5 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 5 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD=VDDA=3.3V5%, VDDO=3.3V5%, 2.5V5% OR 1.8V5%, TA=0C TO 70C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3. 3 3.465 V VDDO Output Supply Voltage 2.375 2. 5 2.625 V 1.71 1. 8 1.89 V IDD Power Supply Current 140 mA IDDA Analog Supply Current 25 mA IDDO Output Supply Current 5 mA 84021AY Test Conditions www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 6 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 6 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD=VDDA=3.3V5%, VDDO=3.3V5%, 2.5V5% OR 1.8V5%, TA=0C TO 70C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, OE0, OE1, N0:N1, M0:M8 TEST_CLK VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, OE0, OE1, N0:N1, M0:M8 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, OE0, OE1, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 3.465V 150 A VDD = VIN = 3.465V 5 A M5, OE0, OE1, XTAL_SEL, VCO_SEL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Minimum Typical VDD = 3.465V, VIN = 0V -5 A VDD = 3.465V, VIN = 0V -150 A VDDO = 3.3V 5% 2.6 V VDDO = 2.5V 5% 1.8 V VDDO = 1.8V 5% VDDO - 0.3 V VDDO = 3.3V 5% 0. 5 V VDDO = 2.5V 5% 0.5 V VDDO = 1.8V 5% 0.4 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Section, "Load Test Circuit Diagrams". TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units TEST_CLK; NOTE 1 14 40 MHz XTAL_IN, XTAL_OUT; Input Frequency 14 40 MHz fIN NOTE 1 S_CLOCK 50 MHz NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 620MHz to 780MHz range. Using the minimum input frequency of 14MHz, valid values of M are 45 M 55. Using the maximum frequency of 40MHz, valid values of M are 16 M 19. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 40 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance (CO) 7 pF Drive Level 1 mW 84021AY 14 www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 7 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 7 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter FOUT Test Conditions Output Frequency tjit(per) Period Jitter, RMS; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time tS tH o dc Setup Time Hold Time Minimum Typical 103.3 Maximum Units 260 MHz N/3 7.5 10 ps N/4 4.3 7 ps N/5 4.1 6 ps N/6 12.9 20% to 80% 300 16 ps 100 ps 800 ps M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns Output Duty Cycle 45 55 % PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter FOUT tjit(per) Test Conditions Output Frequency Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time Setup Time Maximum Units 260 MHz N/3 6.4 8 ps N/4 4.3 8 ps N/5 4.2 7 ps N/6 9 12 ps 90 ps 800 ps 20% to 80% M, N to nP_LOAD tS Typical 103.3 Period Jitter, RMS; NOTE 1 tsk(o) Minimum 300 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns tH Hold Time odc Output Duty Cycle S_CLOCK to S_LOAD 5 45 ns 55 % PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 8 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 8 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. TABLE 7C. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V5%, TA = 0C TO 70C Symbol Parameter FOUT Test Conditions Output Frequency tjit(per) Period Jitter, RMS; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 t R / tF Output Rise/Fall Time tS tH o dc Setup Time Hold Time Minimum Typical 103.3 Maximum Units 260 MHz N/3 6.8 8 ps N/4 4.5 8 ps N/5 4.2 6 ps N/6 8.5 20% to 80% 300 10 ps 120 ps 800 ps M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns Output Duty Cycle 42 58 % PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 9 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 9 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. PARAMETER MEASUREMENT INFORMATION 1.65V5% 2.05V5% 1.25V5% SCOPE VDD, VDDA, VDDO VDDO Qx LVCMOS SCOPE VDD, VDDA Qx LVCMOS GND GND -1.65V5% -1.25V5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.4V5% 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT 0.9V5% VOH VREF SCOPE VDD, VDDA VDDO Qx LVCMOS VOL 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements GND Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) -0.9V5% PERIOD JITTER 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT V 80% DDO Qx Clock Outputs V DDO Qy 80% 2 20% 20% tR tF 2 tsk(o) OUTPUT SKEW OUTPUT RISE/FALL TIME V DDO 2 Q0, Q1 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 10 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 10 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84021 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01F 24 VDDA .01F 10F FIGURE 2. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS84021 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 3. CRYSTAL INPUt INTERFACE 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 11 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 11 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. APPLICATION SCHEMATIC EXAMPLE 18pF parallel resonant crystal is used. The C1=22pF and C2=22pF are approximate values for frequency accuracy. The C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Figure 4 shows a schematic example of the ICS84021. In this example, a series ter mination is shown. Additional LVCMOS ter mination approaches are sho wn in the LVCMOS Termination Application Note. In this example, an C1 X1 22p C2 22p 32 31 30 29 28 27 26 25 18pF M5 M6 M7 M8 N0 N1 nc GND X_OUT T_CLK nXTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR 24 23 22 21 20 19 18 17 R7 24 VDDA C11 0.01u VDD=3.3V C16 10u VDDO=3.3V, 2.5V or 1.8V ICS84021 9 10 11 12 13 14 15 16 TEST VDD OE1 OE0 VDDO Q1 Q0 GND 1 2 3 4 5 6 7 8 VDD M4 M3 M2 M1 M0 VCO_SEL nP_LOAD X_IN U1 Logic Input Pin Examples VDD Set Logic Input to '1' VDD C14 0.1u R1 Zo = 50 Ohm VDDO RU1 1K 43 C15 0.1u R2 Set Logic Input to '0' VDD RU2 Not Install To Logic Input pins Zo = 50 Ohm RD1 Not Install To Logic Input pins RD2 1K 43 FIGURE 4. ICS84021 APPLICATION SCHEMATIC EXAMPLE 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 12 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 12 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. RELIABILITY INFORMATION TABLE 8. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8C/W 47.9C/W 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84021 is: 4325 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 13 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 13 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC 0.75 L 0.45 0.60 0 -- 7 ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 14 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 14 ICS84021 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS84021AY ICS84021AY 32 Lead LQFP tray 0C to 70C ICS84021AYT ICS84021AY 32 Lead LQFP 1000 tape & reel 0C to 70C ICS84021AYLF ICS84021AYLF 32 Lead "Lead-Free" LQFP tray 0C to 70C ICS84021AYLFT ICS84021AYLF 32 Lead "Lead-Free" LQFP 1000 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84021AY www.icst.com/products/hiperclocks.html REV. C JUNE 9, 2005 15 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 15 ICS84021 Integrated ICS84021 Circuit 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER ICS84021 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL TSD FREQUENCY SYNTHESIZER Systems, Inc. REVISION HISTORY SHEET Rev Table T2 B C 84021AY T6 T10 Page 4 12 1 2 7 15 Description of Change Pin Characteristics Table - added ROUT rows. Added Schematic Layout. Changed XTAL naming convention to XTAL_IN/XTAL_OUT throughout the data sheet. Features Section - added Lead-Free bullet. Updated Parallel & Serial Load Operations Diagram. Cr ystal Characteristics Table - added Drive Level. Ordering Information Table - added Lead-Free package. www.icst.com/products/hiperclocks.html Date 1/5/04 6/9/05 REV. C JUNE 9, 2005 16 IDTTM / ICSTM 260MHZ, CRYSTAL-TO-LVCMOS LVTTL FREQUENCY SYNTHESIZER 16 ICS84021 ICS84021 ICS650-40A ICS252 ETHERNET 260MHZ, CRYSTAL-TO-LVCMOS SWITCH CLOCK SOURCE LVTTL FREQUENCY SYNTHESIZER FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER TSD TSD Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 clockhelp@idt.com 408-284-8200 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX