NUP4114 Series ESD Protection Diode Low Clamping Voltage The NUP4114 ESD protection diode array is designed to protect high speed data lines from ESD. Ultra-low capacitance and high level of ESD protection make these devices well suited for use in USB 2.0 high speed applications. www.onsemi.com 5 Features * * * * * * * Low Clamping Voltage Low Capacitance (<0.6 pF Typical, I/O to GND) Low Leakage Response Time is Typically < 1.0 ns IEC61000-4-2 Level 4 ESD Protection SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant 1 2 MARKING DIAGRAMS 6 Typical Applications * * * * * * LVDS USB 2.0 High Speed Data Line and Power Line Protection Digital Video Interface (DVI) and HDMI Gigabit Ethernet Monitors and Flat Panel Displays Notebook Computers SC-88 W1 SUFFIX CASE 419B 1 6 SC-88 W1 SUFFIX CASE 419B Value 6 Unit Operating Junction Temperature Range TJ -40 to +125 C Storage Temperature Range Tstg -55 to +150 C Lead Solder Temperature - Maximum (10 Seconds) TL 260 C ESD 8 15 10 21 30 kV IEC 61000-4-2 Contact IEC 61000-4-2 Air ISO 10605 330 pF / 330 W Contact ISO 10605 330 pF / 2 kW Contact ISO 10605 150 pF / 2 kW Contact X4 MG G 1 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol X2 MG G 1 1 Rating 4 3 6 1 6 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. See Application Note AND8308/D for further description of survivability specs. TSOP-6 CASE 318G STYLE 12 SOT-563 CASE 463A P4H MG G 1 1 P4MG G XXX = Specific Device Code M = Date Code G = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. (c) Semiconductor Components Industries, LLC, 2014 July, 2019 - Rev. 7 1 Publication Order Number: NUP4114/D NUP4114 Series ELECTRICAL CHARACTERISTICS I (TA = 25C unless otherwise noted) Symbol IF Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR Working Peak Reverse Voltage VBR Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation V IR VF IT Breakdown Voltage @ IT IT C VC VBR VRWM Maximum Reverse Leakage Current @ VRWM IPP Uni-Directional Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage Symbol Conditions Min Typ VRWM VBR IT = 1 mA, (Note 1) 5.5 Max Unit 5.5 V 1.0 mA 6.5 V Reverse Leakage Current IR VRWM = 5.5 V Clamping Voltage VC IPP = 1 A (Note 2) 8.3 10 V IPP = 5 A (Note 3) 8.5 9.0 V IPP = 8 A (Note 3) 9.2 10 V ESD Clamping Voltage VC Per IEC61000-4-2 (Note 4) Maximum Peak Pulse Current IPP 8/20 ms Waveform (Note 3) 12 A Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.6 pF VR = 0 V, f = 1 MHz between I/O Pins 0.3 pF 1. 2. 3. 4. See Figures 1 & 2 VBR is measured at pulse test current IT. Nonrepetitive current pulse (I/O to GND). Nonrepetitive current pulse (Pin 5 to Pin 2) For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000-4-2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000-4-2 www.onsemi.com 2 NUP4114 Series IEC61000-4-2 Waveform IEC 61000-4-2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000-4-2 Spec Device Under ESD Gun Oscilloscope Test 50 W 50 W Cable Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D - Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000-4-2 waveform. Since the IEC61000-4-2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8/20 ms Pulse Waveform www.onsemi.com 3 80 NUP4114 Series Figure 6. 500 MHz Data Pattern ORDERING INFORMATION Device Marking NUP4114UCLW1T1G X2 NUP4114UCLW1T2G X2 SZNUP4114UCLW1T2G X2 NUP4114UCW1T2G X4 NUP4114UPXV6T1G NUP4114UPXV6T2G P4 NUP4114HMR6T1G P4H SZNUP4114HMR6T1G P4H Package Shipping SC-88 (Pb-Free) 3000 / Tape & Reel SOT-563 (Pb-Free) 4000 / Tape & Reel TSOP-6 (Pb-Free) 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 4 NUP4114 Series APPLICATIONS INFORMATION Option 2 The new NUP4114 is a low capacitance ESD diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the NUP4114 offers low capacitance steering diodes and an ESD diode integrated in a single package (TSOP-6). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. This device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. Protection of four data lines with bias and power supply isolation resistor. I/O 1 I/O 2 VCC 1 6 2 5 3 4 10 k I/O 3 NUP4114 Configuration Options I/O 4 The NUP4114 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or VCC + Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 3, 4 and 6. The negative reference is connected at pin 2. This pin must be connected directly to ground by using a ground plane to minimize the PCB's ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. The NUP4114 can be isolated from the power supply by connecting a series resistor between pin 5 and VCC. A 10 kW resistor is recommended for this application. This will maintain a bias on the internal ESD and steering diodes, reducing their capacitance. Option 3 Protection of four data lines using the internal ESD diode as reference. I/O 1 I/O 2 Option 1 1 6 Protection of four data lines and the power supply using VCC as reference. 2 5 3 4 I/O 1 I/O 2 NC I/O 3 1 6 2 5 3 4 I/O 4 In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal ESD can be used as the reference. For these applications, pin 5 is not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the ESD plus one diode drop (VC = Vf + VESD). VCC I/O 3 I/O 4 ESD Protection of Power Supply Lines For this configuration, connect pin 5 directly to the positive supply rail (VCC), the data lines are referenced to the supply voltage. The internal ESD diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. www.onsemi.com 5 NUP4114 Series layout. Taking care to minimize the effects of parasitic inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP4114 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates an ESD diode within a network of steering diodes. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: Power Supply IESDpos VCC Protected Data Line Device D1 IESDpos D2 IESDneg IESDneg VF + VCC -VF Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = VCC + VfD1 For negative pulse conditions: Vc = -VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. Power Supply 5 1 2 Figure 7. NUP4114 Equivalent Circuit During an ESD condition, the ESD current will be driven to ground through the ESD diode as shown below. IESDpos VCC Protected Device D1 IESDpos 4 3 6 Power Supply IESDneg VCC Data Line D2 D1 VC = VCC + Vf + (L diESD/dt) IESDneg Protected Device IESDpos Data Line D2 VC = -Vf - (L diESD/dt) An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = VCC + Vf + (L diESD/dt) For negative pulse conditions: Vc = -Vf - (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board The resulting clamping voltage on the protected IC will be: Vc = VF + VESD. The clamping voltage of the ESD diode depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP-6 CASE 318G-02 ISSUE V 1 SCALE 2:1 D H EE EE 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b DETAIL Z e C SEATING PLANE DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0 MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10 - STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)- 4. D(IN)- 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS STATUS: ON SEMICONDUCTOR STANDARD 1 NEW STANDARD: TSOP-6 XXX = Specific Device Code M = Date Code G = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. 98ASB14888C (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 Rev. 0 = Specific Device Code =Assembly Location = Year = Work Week = Pb-Free Package STANDARD (Note: Microdot may be in either location) *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: 1 IC 0.95 XXX MG G http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98ASB14888C PAGE 2 OF 2 ISSUE REVISION DATE B ADDED STYLE 2. REQ.BY A. PATEL. 05 MAY 1997 C ADDED STYLE 3. REQ.BY D. BOLDT, ADDED STYLE 4. REQ.BY UKO. 14 APR 1998 D ADDED STYLE 5. REQ.BY D. BOLDT. 13 MAY 1998 E ADDED STYLE 6. REQ.BY M. ATANOVICH. 17 NOV 1999 F MOTOROLA WAS NOT REMOVED FROM (STATUS) PAGES. PAGES NOT NUMBERED CORRECTLY. REV PAGE WAS MISSING. REQ.BY F. BLAKLEY. 22 NOV 1999 G ADDED STYLE 7. REQ.BY M. ATANOVICH. 15 DEC 1999 H ADDED STYLE 8. REQ.BY D. TRUHITTE. 11 MAY 2001 J ADDED NOTE 4. REQ. BY S. RIGGS. 26 JUN 2003 K ADDED STYLE 9. REQ.BY S. BACHMAN. 09 SEP 2003 L ADDED STYLE 10. REQ. BY A. TAM. 25 FEB 2004 M ADDED STYLE 11 AND 12. REQ. BY L. ROBINSON. 07 JUN 2004 N CORRECTED STYLE 11, PIN 4 SOURCE 2. REQ. BY C. CHENG . 03 FEB 2005 P ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ. BY HONG XIAO. 27 MAY 2005 R ADDED STYLE 13. REQ. BY J. CARTER. 09 MAR 2006 S ADDED STYLE 14. REQ. BY A. SAM. 22 MAR 2006 T ADDED STYLE 15. REQ. BY S. WINSTON. 06 FEB 2008 U ADDED DETAIL Z, REMOVED INCH VALUES, ADDED L2, ADDED NOTE 5. REQ. BY J. LETTERMAN. 14 JAN 2010 V ADDED STYLES 16 & 17. REQ. BY Y. KALDERON. 12 JUN 2012 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. (c) Semiconductor Components Industries, LLC, 2012 June, 2012 - Rev. V Case Outline Number: 318G MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC-88/SC70-6/SOT-363 CASE 419B-02 ISSUE Y 1 SCALE 2:1 DATE 11 DEC 2012 2X aaa H D D H A D 6 5 GAGE PLANE 4 1 2 L L2 E1 E DETAIL A 3 aaa C 2X bbb H D 2X 3 TIPS e B 6X C A-B D M A2 DETAIL A A ccc C A1 SIDE VIEW DIM A A1 A2 b C D E E1 e L L2 aaa bbb ccc ddd b ddd TOP VIEW 6X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. C SEATING PLANE END VIEW c 6 XXXMG G 6X 0.30 INCHES MIN NOM MAX --- --- 0.043 0.000 --- 0.004 0.027 0.035 0.039 0.006 0.008 0.010 0.003 0.006 0.009 0.070 0.078 0.086 0.078 0.082 0.086 0.045 0.049 0.053 0.026 BSC 0.010 0.014 0.018 0.006 BSC 0.006 0.012 0.004 0.004 GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X MILLIMETERS MIN NOM MAX --- --- 1.10 0.00 --- 0.10 0.70 0.90 1.00 0.15 0.20 0.25 0.08 0.15 0.22 1.80 2.00 2.20 2.00 2.10 2.20 1.15 1.25 1.35 0.65 BSC 0.26 0.36 0.46 0.15 BSC 0.15 0.30 0.10 0.10 0.66 1 2.50 0.65 PITCH XXX = Specific Device Code M = Date Code* G = Pb-Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. STYLES ON PAGE 2 DOCUMENT NUMBER: STATUS: NEW STANDARD: 98ASB42985B ON SEMICONDUCTOR STANDARD http://onsemi.com SC-88/SC70-6/SOT-363 1 (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 - Rev. 0 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 1 OFXXX 3 SC-88/SC70-6/SOT-363 CASE 419B-02 ISSUE Y DATE 11 DEC 2012 STYLE 1: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 2: CANCELLED STYLE 3: CANCELLED STYLE 4: PIN 1. CATHODE 2. CATHODE 3. COLLECTOR 4. EMITTER 5. BASE 6. ANODE STYLE 5: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 6: PIN 1. ANODE 2 2. N/C 3. CATHODE 1 4. ANODE 1 5. N/C 6. CATHODE 2 STYLE 7: PIN 1. SOURCE 2 2. DRAIN 2 3. GATE 1 4. SOURCE 1 5. DRAIN 1 6. GATE 2 STYLE 8: CANCELLED STYLE 9: PIN 1. EMITTER 2 2. EMITTER 1 3. COLLECTOR 1 4. BASE 1 5. BASE 2 6. COLLECTOR 2 STYLE 10: PIN 1. SOURCE 2 2. SOURCE 1 3. GATE 1 4. DRAIN 1 5. DRAIN 2 6. GATE 2 STYLE 11: PIN 1. CATHODE 2 2. CATHODE 2 3. ANODE 1 4. CATHODE 1 5. CATHODE 1 6. ANODE 2 STYLE 12: PIN 1. ANODE 2 2. ANODE 2 3. CATHODE 1 4. ANODE 1 5. ANODE 1 6. CATHODE 2 STYLE 13: PIN 1. ANODE 2. N/C 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 14: PIN 1. VREF 2. GND 3. GND 4. IOUT 5. VEN 6. VCC STYLE 15: PIN 1. ANODE 1 2. ANODE 2 3. ANODE 3 4. CATHODE 3 5. CATHODE 2 6. CATHODE 1 STYLE 16: PIN 1. BASE 1 2. EMITTER 2 3. COLLECTOR 2 4. BASE 2 5. EMITTER 1 6. COLLECTOR 1 STYLE 17: PIN 1. BASE 1 2. EMITTER 1 3. COLLECTOR 2 4. BASE 2 5. EMITTER 2 6. COLLECTOR 1 STYLE 18: PIN 1. VIN1 2. VCC 3. VOUT2 4. VIN2 5. GND 6. VOUT1 STYLE 19: PIN 1. I OUT 2. GND 3. GND 4. V CC 5. V EN 6. V REF STYLE 20: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 21: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. N/C 6. CATHODE 1 STYLE 22: PIN 1. D1 (i) 2. GND 3. D2 (i) 4. D2 (c) 5. VBUS 6. D1 (c) STYLE 23: PIN 1. Vn 2. CH1 3. Vp 4. N/C 5. CH2 6. N/C STYLE 24: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE STYLE 25: PIN 1. BASE 1 2. CATHODE 3. COLLECTOR 2 4. BASE 2 5. EMITTER 6. COLLECTOR 1 STYLE 26: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 STYLE 27: PIN 1. BASE 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. EMITTER 2 6. COLLECTOR 2 STYLE 28: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 29: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE/ANODE 6. CATHODE STYLE 30: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1 DOCUMENT NUMBER: STATUS: NEW STANDARD: 98ASB42985B ON SEMICONDUCTOR STANDARD http://onsemi.com SC-88/SC-70/SOT-363 2 (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 - Rev. 0 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 2 OFXXX 3 DOCUMENT NUMBER: 98ASB42985B PAGE 3 OF 3 ISSUE REVISION DATE H REVISION TO CHANGE LEGAL OWNER OF DOCUMENT FROM MOTOROLA TO ON SEMICONDUCTOR. DELETED DIM "V" WAS 0.3 MM-0.4 MM/0.012-0.016 IN. REQ BY G KWONG 14 JUN 01 J ADDED STYLE 20. REQ BY M. ATANOVICH. 11 OCT 01 K UPDATED STYLE 15 WAS PIN 1, 2 AND 3: ANODE. PIN 4, 5, AND 6 CATHODE. ADDED STYLE 21. REQ BY M. ATANOVICH 03 APR 02 L ADDED STYLE 22. REQ BY S. CHANG 25 OCT 02 M ADDED STYLE 23. REQ BY B. BLACKMON 04 DEC 02 N ADDED STYLE 24. REQ BY B. BLACKMON 09 JAN 03 P ADDED STYLE 25. REQ BY S. CHANG 09 MAY 03 R REMOVED THE "1" AFTER EMITTER. REQ BY S. CHANG 03 JUN 03 S ADDED STYLE 26. REQ BY A. BINEYARD 18 AUG 03 T ADDED STYLE 27. REQ. BY M. SWEADOR 23 OCT 2003 U ADDED STYLES 28 AND 29. REQ. BY A. BINEYARD AND S. BACHMAN 22 JAN 2004 V ADDED NOM VALUES AND CHANGED DIMS TO INDUSTRY STANDARD. REQ. BY D. TRUHITTE 31 JAN 2005 W ADDED STYLE 30. REQ. BY L. DELUCA. 26 JAN 2006 Y UPDATED & REDREW TO JEDEC STANDARDS. REQ. BY D. TRUHITTE. 11 DEC 2012 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. (c) Semiconductor Components Industries, LLC, 2012 December, 2012 - Rev. Y Case Outline Number: 419B MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT-563, 6 LEAD CASE 463A ISSUE G 6 1 DATE 23 SEP 2015 SCALE 4:1 D -X- 5 6 1 2 A 4 e L E -Y- 3 b NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A b C D E e L HE HE C 5 PL 6 0.08 (0.003) M X Y STYLE 1: PIN 1. EMITTER 1 2. BASE 1 3. COLLECTOR 2 4. EMITTER 2 5. BASE 2 6. COLLECTOR 1 STYLE 2: PIN 1. EMITTER 1 2. EMITTER2 3. BASE 2 4. COLLECTOR 2 5. BASE 1 6. COLLECTOR 1 STYLE 3: PIN 1. CATHODE 1 2. CATHODE 1 3. ANODE/ANODE 2 4. CATHODE 2 5. CATHODE 2 6. ANODE/ANODE 1 STYLE 4: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 5: PIN 1. CATHODE 2. CATHODE 3. ANODE 4. ANODE 5. CATHODE 6. CATHODE STYLE 6: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE STYLE 7: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. ANODE 6. CATHODE STYLE 8: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 9: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 STYLE 10: PIN 1. CATHODE 1 2. N/C 3. CATHODE 2 4. ANODE 2 5. N/C 6. ANODE 1 MILLIMETERS MIN NOM MAX 0.50 0.55 0.60 0.17 0.22 0.27 0.08 0.12 0.18 1.50 1.60 1.70 1.10 1.20 1.30 0.5 BSC 0.10 0.20 0.30 1.50 1.60 1.70 INCHES NOM MAX 0.021 0.023 0.009 0.011 0.005 0.007 0.062 0.066 0.047 0.051 0.02 BSC 0.004 0.008 0.012 0.059 0.062 0.066 MIN 0.020 0.007 0.003 0.059 0.043 GENERIC MARKING DIAGRAM* XX MG 1 XX = Specific Device Code M = Month Code G = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. SOLDERING FOOTPRINT* 0.3 0.0118 0.45 0.0177 1.35 0.0531 1.0 0.0394 0.5 0.5 0.0197 0.0197 SCALE 20:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON11126D SOT-563, 6 LEAD Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. 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