1
Data sheet acquired from Harris Semiconductor
SCHS170B
Features
• Common Select Inputs
• Separate Output-Enable Inputs
• Three-State Outputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The CD74HC253 and CD74HCT253 are dual 4-to-1 line
selector/multiplexers having three-state outputs. One of four
sources for each section is selected by the common select
inputs, S0 and S1. When the output enable (1OE, 2OE) is
HIGH, the output is in the high-impedance state.
Pinout
CD74HC253, CD74HCT253
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC253E -55 to 125 16 Ld PDIP
CD74HC253M -55 to 125 16 Ld SOIC
CD74HC253MT -55 to 125 16 Ld SOIC
CD74HC253M96 -55 to 125 16 Ld SOIC
CD74HCT253E -55 to 125 16 Ld PDIP
CD74HCT253M -55 to 125 16 Ld SOIC
CD74HCT253MT -55 to 125 16 Ld SOIC
CD74HCT253M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1OE
S1
1I3
1I2
1I1
1I0
GND
1Y
VCC
S0
2I3
2I2
2I1
2I0
2Y
2OE
November 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD74HC253,
CD74HCT253
High-Speed CMOS Logic
Dual 4-Input Multiplexer
[
/Title
(
CD74
H
C253
,
C
D74
H
CT25
3
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
D
ual
4
-Input
M
ulti-
p
lexer)
2
Functional Diagrams
TRUTH TABLE
SELECT INPUTS
(Note 1) DATA INPUTS OUTPUT
ENABLE OUTPUT
S1 S0 I0I1I2I3OE Y
XXXXXXHZ
LLLXXXLL
LLHXXXLH
LHXLXXLL
LHXHXXLH
HLXXLXLL
HLXXHXLH
HHXXXLLL
HHXXXHLH
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance (Off).
NOTE:
1. Select inputs S1 and S0 are common to both sections.
2OE 2I32I22I12I0S0S11I01I11I21I31OE
15 13 12 11 10 14 2 6 5 4 3 1
2OE
2OE
1OE
1OE
PN PN
2OE 2OE
9
2Y
1OE 1OE
7
1Y
16
8VCC
GND
CD74HC253, CD74HCT253
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 2) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-6 4.5 3.98 - - 3.84 - 3.7 - V
-7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
-6 4.5 - - 0.26 - 0.33 - 0.4 V
-7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
CD74HC253, CD74HCT253
4
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 3) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
Three-State Leakage
Current IOZ VIL or VIH VO =
VCC or
GND
5.5 - - ±0.5 - ±5-±10 µA
NOTE:
3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
1IO - 1I3, 2IO-2l30.4
1EO, 2EO, S0, S11
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPLH,
tPHL CL= 50pF 2 - - 175 - 220 - 265 ns
Select to Outputs 4.5 - - 35 - 44 - 53 ns
CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns
CD74HC253, CD74HCT253
5
Data to Outputs tPLH,
tPHL CL= 50pF 2 - - 175 - 220 - 265 ns
4.5 - - 35 - 44 - 53 ns
CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns
Disable Delay Times tPHZ, tPLZ CL= 50pF 2 - - 150 - 190 - 225 ns
CL= 50pF 4.5 - - 30 - 38 - 45 ns
CL = 15pF 5 - 12 - - - - - ns
CL= 50pF 6 - - 26 - 33 - 38 ns
Enable Delay Times tPZH,
tPZL CL= 50pF 2 - - 110 - 140 - 165 ns
CL = 50pF 4.5 - - 22 - 28 - 33 ns
CL = 15pF 5 - 9 - - - - - ns
CL = 50pF 6 - - 19 - 24 - 28 ns
Output Transition Times tTLH,t
THL CL= 50pF 2 - - 60 - 75 - 90 ns
4.5 - - 12 - 15 - 18 ns
6 - - 10 - 13 - 15 ns
Input Capacitance CI- - - - 10 - 10 - 10 pF
Three-State Output Capacitance CO- - - - 20 - 20 - 20 pF
Power Dissipation Capacitance
(Notes 4, 5) CPD -5-46-----pF
HCT TYPES
Propagation Delay tPLH,
tPHL
Select to Outputs CL= 50pF 4.5 - - 40 - 50 - 60 ns
CL=15pF 5 - 16 - - - - ns
Data to Outputs tPLH,
tPHL CL= 50pF 4.5 - - 38 - 48 - 57 ns
CL=15pF 5 - 16 - - - - - ns
Disable Delay Times tPLH,
tPHL CL= 50pF 4.5 - 30 - 38 - 45 ns
CL=15pF 5 - 12 - - - - - ns
Enable Delay Times tPZH,
tPZL CL= 50pF 4.5 - - 30 - 38 - 45 ns
CL=15pF 5 - 12 - - - - - ns
Output Transition Time tTLH,t
THL CL= 50pF 4.5 - - 12 - 15 - 18 ns
Input Capacitance CIN - - - - 10 - 10 - 10 pF
Three-State Output Capacitance CO- - - - 20 - 20 - 20 pF
Power Dissipation Capacitance
(Notes 4, 5) CPD -5-52-----pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per multiplexer.
5. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD74HC253, CD74HCT253
6
Test Circuits and Waveforms
FIGURE 1. HC AND HCT TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto
VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
50% 10%
90%
GN
D
VCC
10%
90% 50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
0.3
2.7
GN
D
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
tr6ns
tPZH
tPHZ
tPZL
tPLZ
6ns tf
1.3
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
T
IED HIGH
OR LOW
OUTPUT
DISABLE
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZ
H
OUTPUT
RL = 1kΩ
CL
50pF
CD74HC253, CD74HCT253
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD74HC253E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC253EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC253M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC253ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC253MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC253MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC253MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC253MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT253E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT253EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT253M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT253M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT253M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT253M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT253ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT253MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT253MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT253MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT253MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2007
Addendum-Page 1
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HCT253M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HCT253M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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