PC8548EMGHYAQGA - E2V Technologies (UK), Ltd.

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e2v semiconductors SAS 2008

PC8548E

PowerQUICC III Integrated Processor

Datasheet - Preliminary Specification

Features

•Embedded e500 Core, Initial Offerings up to 1.2 GHz

– Dual Dispatch Superscalar, 7-stage Pipeline Design with out-of-order Issue and

Execution

– 3065 MIPS at 1333 MHz (Estimated Dhrystone 2.1)

•36-bit Physical Addressing

•Enhanced Hardware and Software Debug Support

•Double-precision Embedded Scalar and Vector Floating-point APUs

•Memory Management Unit (MMU)

•Integrated L1/L2 Cache

– L1 Cache-32 KB Data and 32 KB Instruction Cache with Line-locking Support

– L2 Cache-512 KB (8-Way Set Associative); 512 KB/256 KB/128 KB/64 KB Can Be Used As SRAM

– L1 and L2 Hardware Coherency

– L2 Configurable As SRAM, Cache and I/O Transactions Can Be Stashed Into L2 Cache Regions

•Integrated DDR Memory Controller With Full ECC Support, Supporting:

– 200 MHz Clock Rate (400 MHz Data Rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM

•Integrated Security Engine Supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 Encryption

Algorithms

•Four On-chip Triple-speed Ethernet Controllers (GMACs) Supporting 10- and 100-Mbps, and 1-Gbps Ethernet/IEEE*802.3

Networks with MII, RMII, GMII, RGMII, RTBI and TBI Physical Interfaces

– TCP/IP Checksum Acceleration

– Advanced QoS Features

•General-purpose I/O (GPIO)

•Serial RapidIO and PCI Express High-speed Interconnect Interfaces, Supporting

– Single x8 PCI Express, or Single x4 PCI Express and Single 4x Serial RapidIO

•On-chip Network (OCeaN) Switch Fabric

•Multiple PCI Interface Support

– 64-bit PCI 2.2 Bus Controller (Up to 66 MHz, 3.3V I/O)

– 64-bit PCI-X Bus Controller (Up to 133 MHz, 3.3V I/O), or Flexibility to Configure Two 32-bit PCI Controllers

•166 MHz, 32-bit, 3.3V I/O, Local Bus with Memory Controller

•Integrated Four-channel DMA Controller

•Dual I2C and Dual Universal Asynchronous Receiver/Transmitter (DUAR) Support

•Programmable Interrupt Controller (PIC), IEEE 1149.1 JTAG Test Access Port

•1.1V Core Voltage with 3.3V and 2.5V I/O, 783-pin HITCE Package

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Description

The PC8548E contains a PowerPC® processor core. The PC8548E integrates a processor that implements the PowerPC

architecture with system logic required for networking, storage, and general-purpose embedded applications. For func-

tional characteristics of the processor, refer to the PC8548E Integrated Processor Preliminary Reference Manual.

Screening

•Full Military Temperature Range (TC = -55°C, TJ = +125°C)

•Industrial Temperature Range (TC = -40°C, TJ = +110°C)

1. PC8548E Architecture General Overview

Figure 1-1. PC8548E Block Diagram

Core Complex

Bus

x8 PCI Express

4x RapidlO

66 MHz

PCI 32-bit

10/100/1Gb

MII, GMII, TBI,

RTBI, RGMII,

RMII

MII, GMII, TBI,

RTBI, RGMII,

RMII

MII, GMII, TBI,

RTBI, RGMII,

RMII

RTBI, RGMII,

RMII

IRQs

SDRAM

DDR

Flash

SDRAM

GPIO

I2C

Controller

I2C

Controller

eTSEC

e500

Coherency

Module

DDR/DDR2/

Memory Controller

Local Bus Controller

Programmable Interrupt

Controller (PIC)

e500 Core

512-Kbyte

L2 Cache/

SRAM

32-bit PCI/

64-bit PCI/PCI-X

Bus Interface

32-Kbyte L1

Instruction

Cache

32-Kbyte

L1 Data

Cache

OceaN

Switch

Fabric

Serial RapidIO

PCI Express

4-Channel DMA

Controller

PCI/PCI-X

133 MHz

10/100/1Gb

eTSEC

Security

Engine

XOR

Engine

Serial

32-bit PCI Bus Interface

(If 64-bit not used)

DUART

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PC8548E [Preliminary]

2. Features Overview

The following list provides an overview of the PC8548E feature set:

• High-performance 32-bit Book E–enhanced core that implements the PowerPC® architecture

– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches

can be locked entirely or on a per-line basis, with separate locking for instructions and data.

– Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive

instruction set for vector (64-bit) integer and fractional operations. These instructions use

both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.

– Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs.

– 36-bit real addressing

– Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bit) floating-point instructions.

– Memory management unit (MMU). Especially designed for embedded applications. Supports

4-Kbyte–4-Gbyte page sizes.

– Enhanced hardware and software debug support

– Performance monitor facility that is similar to, but separate from, the PC8548E performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some

features that this device implements more specifically. An understanding of these differences can be

critical to ensure proper operations.

• 512-Kbyte L2 cache/SRAM

– Flexible configuration.

– Full ECC support on 64-bit boundary in both cache and SRAM modes

– Cache mode supports instruction caching, data caching, or both.

– External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

– 1, 2, or 4 ways can be configured for stashing only.

– Eight-way set-associative cache organization (32-byte cache lines)

– Supports locking entire cache or selected lines. Individual line locks are set and cleared

through Book E instructions or by externally mastered transactions.

– Global locking and flash clearing done through writes to L2 configuration registers

– Instruction and data locks can be flash cleared separately.

– SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for smaller-

than-cache-line accesses.

• Address translation and mapping unit (ATMU)

– Eight local access windows define mapping within local 36-bit address space.

– Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express

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– Four inbound windows plus a default window on RapidIO

– Four outbound windows plus default translation for PCI/PCI-X and PCI Express

– Eight outbound windows plus default translation for RapidIO with segmentation and sub-

segmentation support

• DDR/DDR2 memory controller

– Programmable timing supporting DDR and DDR2 SDRAM

– 64-bit data interface

– Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes

– DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports

– Full ECC support

– Page mode support

– Up to 16 simultaneous open pages for DDR

– Up to 32 simultaneous open pages for DDR2

– Contiguous or discontiguous memory mapping

– Read-modify-write support for RapidIO atomic increment, decrement, set, and clear

transactions

– Sleep mode support for self-refresh SDRAM

– On-die termination support when using DDR2

– Supports auto refreshing

– On-the-fly power management using CKE signal

– Registered DIMM support

– Fast memory access via JTAG port

– 2.5V SSTL_2 compatible I/O (1.8V SSTL_1.8 for DDR2)

– Support for battery-backed main memory

• Programmable interrupt controller (PIC)

– Programming model is compliant with the OpenPIC architecture.

– Supports 16 programmable interrupt and processor task priority levels

– Supports 12 discrete external interrupts

– Supports 4 message interrupts with 32-bit messages

– Supports connection of an external interrupt controller such as the 8259 programmable

interrupt controller

– Four global high resolution timers/counters that can generate interrupts

– Supports a variety of other internal interrupt sources

– Supports fully nested interrupt delivery

– Interrupts can be routed to external pin for external processing.

– Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.

– Interrupt summary registers allow fast identification of interrupt source.

• Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE,

WTLS/WAP, SSL/TLS, and 3GPP

– Four crypto-channels, each supporting multi-command descriptor chains

– Dynamic assignment of crypto-execution units via an integrated controller

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– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

– PKEU: public key execution unit

– RSA and Diffie-Hellman; programmable field size up to 2048 bits

– Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to

511 bits

– DEU: Data Encryption Standard execution unit

– DES, 3DES

– Two key (K1, K2, K1) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

– AESU: Advanced Encryption Standard unit

– Implements the Rijndael symmetric key cipher

– ECB, CBC, CTR, and CCM modes

– 128-, 192-, and 256-bit key lengths

– AFEU: ARC four execution unit

– Implements a stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

– MDEU: message digest execution unit

– SHA with 160- or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

– KEU: Kasumi execution unit

– Implements F8 algorithm for encryption and F9 algorithm for integrity checking

– Also supports A5/3 and GEA-3 algorithms

– RNG: random number generator

– XOR engine for parity checking in RAID storage applications

•Dual I

2C controllers

– Two-wire interface

– Multiple master support

– Master or slave I2C mode support

– On-chip digital filtering rejects spikes on the bus

• Boot sequencer

– Optionally loads configuration data from serial ROM at reset via the I2C interface

– Can be used to initialize configuration registers and/or memory

– Supports extended I2C addressing mode

– Data integrity checked with preamble signature and CRC

•DUART

– Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

– Programming model compatible with the original 16450 UART and the PC16550D

• Local bus controller (LBC)

– Multiplexed 32-bit address and data bus operating at up to 133 MHz

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– Eight chip selects support eight external slaves

– Up to eight-beat burst transfers

– The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.

– Three protocol engines available on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

– Parity support

– Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)

• Four enhanced three-speed Ethernet controllers (eTSECs)

– Three-speed support (10/100/1000 Mbps)

– Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers

– Support for various Ethernet physical interfaces:

– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, and RGMII

– 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMI

– Flexible configuration for multiple PHY interface configurations.

– TCP/IP acceleration and QoS features available

– IP v4 and IP v6 header recognition on receive

– IP v4 header checksum verification and generation

– TCP and UDP checksum verification and generation

– Per-packet configurable acceleration

– Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS

stacks, and ESP/AH IP-security headers

– Supported in all FIFO modes

– Quality of service support:

– Transmission from up to eight physical queues

– Reception to up to eight physical queues

– Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):

– EEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software-

programmed PAUSE frame generation and recognition)

– Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and IEEE

802.1 virtual local area network (VLAN) tags and priority

– VLAN insertion and deletion

– Per-frame VLAN control word or default VLAN for each eTSEC

– Extracted VLAN control word passed to software separately

– Retransmission following a collision

– CRC generation and verification of inbound/outbound frames

– Programmable Ethernet preamble insertion and extraction of up to 7 bytes

– MAC address recognition:

– Exact match on primary and virtual 48-bit unicast addresses

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PC8548E [Preliminary]

– VRRP and HSRP support for seamless router fail-over

– Up to 16 exact-match MAC addresses supported

– Broadcast address (accept/reject)

– Hash table match on up to 512 multicast addresses

– Promiscuous mode

– Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet

programming models

– RMON statistics support

– 10-Kbyte internal transmit and 2-Kbyte receive FIFOs

– MII management interface for control and status

– Ability to force allocation of header information and buffer descriptors into L2 cache

• OCeaN switch fabric

– Full crossbar packet switch

– Reorders packets from a source based on priorities

– Reorders packets to bypass blocked packets

– Implements starvation avoidance algorithms

– Supports packets with payloads of up to 256 bytes

• Integrated DMA controller

– Four-channel controller

– All channels accessible by both the local and remote masters

– Extended DMA functions (advanced chaining and striding capability)

– Support for scatter and gather transfers

– Misaligned transfer capability

– Interrupt on completed segment, link, list, and error

– Supports transfers to or from any local memory or I/O port

– Selectable hardware-enforced coherency (snoop/no snoop)

– Ability to start and flow control each DMA channel from external 3-pin interface

– Ability to launch DMA from single write transaction

• Two PCI/PCI-X controllers

– PCI 2.2 and PCI-X 1.0 compatible

– One 32-/64-bit PCI/PCI-X port with support for speeds of up to 133 MHz (maximum PCI-X

frequency in synchronous mode is 110 MHz)

– One 32-bit PCI port with support for speeds from 16 to 66 MHz (available when the other

port is in 32-bit mode)

– Host and agent mode support

– 64-bit dual address cycle (DAC) support

– PCI-X supports multiple split transactions

– Supports PCI-to-memory and memory-to-PCI streaming

– Memory prefetching of PCI read accesses

– Supports posting of processor-to-PCI and PCI-to-memory writes

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– PCI 3.3V compatible

– Selectable hardware-enforced coherency

• Serial RapidIO interface unit

– Supports RapidIO Interconnect Specification, Revision 1.2

– Both 1x and 4x LP-serial link interfaces

– Long- and short-haul electricals with selectable pre-compensation

– Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per

lane

– Auto detection of 1x- and 4x-mode operation during port initialization

– Link initialization and synchronization

– Large and small size transport information field support selectable at initialization time

– 34-bit addressing

– Up to 256 bytes data payload

– All transaction flows and priorities

– Atomic set/clr/inc/dec for read-modify-write operations

– Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at

a remote memory system

– Receiver-controlled flow control

– Error detection, recovery, and time-out for packets and control symbols as required by the

RapidIO specification

– Register and register bit extensions as described in part VIII (Error Management) of the

RapidIO specification

– Hardware recovery only

– Register support is not required for software-mediated error recovery.

– Accept-all mode of operation for fail-over support

– Support for RapidIO error injection

– Internal LP-serial and application interface-level loopback modes

– Memory and PHY BIST for at-speed production test

• RapidIO–compliant message unit

– 4 Kbytes of payload per message

– Up to sixteen 256-byte segments per message

– Two inbound data message structures within the inbox

– Capable of receiving three letters at any mailbox

– Two outbound data message structures within the outbox

– Capable of sending three letters simultaneously

– Single segment multicast to up to 32 devIDs

– Chaining and direct modes in the outbox

– Single inbound doorbell message structure

– Facility to accept port-write messages

• PCI Express interface

– PCI Express 1.0a compatible

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PC8548E [Preliminary]

– Supports x8, x4, x2, and x1 link widths

– Auto-detection of number of connected lanes

– Selectable operation as root complex or endpoint

– Both 32- and 64-bit addressing

– 256-byte maximum payload size

– Virtual channel 0 only

– Traffic class 0 only

– Full 64-bit decode with 32-bit wide windows

• Pin multiplexing for the high speed I/O interfaces supports one of the following configurations:

– x8 PCI Express

– x4 PCI Express and 4x serial RapidIO

• Power management

– Supports power saving modes: doze, nap, and sleep

– Employs dynamic power management, which automatically minimizes power consumption of

blocks when they are idle

• System performance monitor

– Supports eight 32-bit counters that count the occurrence of selected events

– Ability to count up to 512 counter-specific events

– Supports 64 reference events that can be counted on any of the eight counters

– Supports duration and quantity threshold counting

– Burstiness feature that permits counting of burst events with a programmable time between

bursts

– Triggering and chaining capability

– Ability to generate an interrupt on overflow

• System access port

– Uses JTAG interface and a TAP controller to access entire system memory map

– Supports 32-bit accesses to configuration registers

– Supports cache-line burst accesses to main memory

– Supports large block (4-Kbyte) uploads and downloads

– Supports continuous bit streaming of entire block for fast upload and download

• IEEE 1149.1 compliant, JTAG boundary scan

• 783 HITCE package

3. Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

PC8548E. This device is currently targeted to these specifications. Some of these specifications are

independent of the I/O cell, but are included for a more complete reference. These are not purely I/O

buffer design specifications.

3.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

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3.2 Detailed Specification

This specification describes the specific requirements for the microprocessor PC8548E in compliance

with e2v standard screening.

3.3 Applicable Documents

1. MIL-STD-883: Test methods and procedures for electronics

2. MIL-PRF-38535: Appendix A: General specifications for microcircuits

The microcircuits are in accordance with the applicable documents and as specified herein.

3.3.1 Absolute Maximum Ratings

Table 3-1 provides the absolute maximum ratings.

Notes: 1. Functional and tested operating conditions are given in Table 3-2 on page 11. Absolute maximum ratings are stress ratings

only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability

or cause permanent damage to the device.

Table 3-1. Absolute Maximum Ratings(1)

Characteristic Symbol Max Value Unit Notes

Core supply voltage VDD -0.3 to 1.21 V

PLL supply voltage AVDD -0.3 to 1.21 V

Core power supply for SerDes transceivers SVDD -0.3 to 1.21 V

Pad power supply for SerDes transceivers XVDD -0.3 to 1.21 V

DDR and DDR2 DRAM I/O voltage GVDD

-0.3 to 2.75

-0.3 to 1.98 V

Three-speed Ethernet I/O, MII management voltage

LVDD (for eTSEC1

and eTSEC2)

-0.3 to 3.63

-0.3 to 2.75

TVDD (for

eTSEC3

and eTSEC4)

-0.3 to 3.63

-0.3 to 2.75

PCI/PCI-X, DUART, system control and power management, I2C,

and JTAG I/O voltage OVDD -0.3 to 3.63 V (3)

Local bus I/O voltage BVDD

-0.3 to 3.63

-0.3 to 2.75

-0.3 to 1.98

V(3)

Input voltage

DDR/DDR2 DRAM signals MVIN -0.3 to (GVDD + 0.3) V (2)(5)

DDR/DDR2 DRAM reference MVREF -0.3 to (GVDD/2 + 0.3) V (2)(5)

Three-speed Ethernet signals LVIN

TVIN

-0.3 to (LVDD + 0.3)

-0.3 to (TVDD + 0.3) V(4)(5)

Local bus signals BVIN -0.3 to (BVDD + 0.3)

DUART, SYSCLK, system control and

power management, I2C, and JTAG

signals

OVIN -0.3 to (OVDD + 0.3) V (5)

PCI/PCI-X OVIN -0.3 to (OVDD + 0.3) V (6)

Storage temperature range TSTG -55 to 150 °C

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2. Caution: MVIN must not exceed GVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-

on reset and power-down sequences.

3. Caution: OVIN must not exceed OVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-

on reset and power-down sequences.

4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3-1 on page

12.

6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3V operation, as

shown in Figure 7-1 on page 22.

3.3.2 Recommended Operating Conditions

Table 3-2 provides the recommended operating conditions for this device. Note that the values in Table

3-2 are the recommended and tested operating conditions. Proper device operation outside these condi-

tions is not guaranteed.

Notes: 1. This voltage is the input to the filter discussed in Section 22.2.1 ”PLL Power Supply Filtering” on page 89 and not necessar-

ily the voltage at the AVDD pin, which may be reduced from VDD by the filter.

2. Caution: MVIN must not exceed GVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-

on reset and power-down sequences.

Table 3-2. Recommended Operating Conditions

Characteristic Symbol Recommended Value Unit Notes

Core supply voltage VDD 1.1V ± 55 mV V

PLL supply voltage AVDD 1.1V ± 55 mV V (1)

Core power supply for SerDes transceivers SVDD 1.1V ± 55 mV V

Pad power supply for SerDes transceivers XVDD 1.1V ± 55 mV V

DDR and DDR2 DRAM I/O voltage GVDD

2.5V ± 125 mV

1.8V ± 90 mV V

Three-speed Ethernet I/O voltage

LVDD

3.3V ± 165 mV

2.5V ± 125 mV V

(4)

TVDD

3.3V ± 165 mV

2.5V ± 125 mV

(4)

PCI/PCI-X, DUART, system control and power management, I2C, and

JTAG I/O voltage OVDD 3.3V ± 165 mV V (3)

Local bus I/O voltage BVDD

3.3V ± 165 mV

2.5V ± 125 mV V

Input voltage

DDR and DDR2 DRAM signals MVIN GND to GVDD V(2)

DDR and DDR2 DRAM reference MVREF GND to GVDD/2 V (2)

Three-speed Ethernet signals LVIN

TVIN

GND to LVDD

GND to TVDD

V(4)

Local bus signals BVIN GND to BVDD V

PCI, Local bus, DUART, SYSCLK,

system control and power management,

I2C, and JTAG signals

OVIN GND to OVDD V(3)

Operating Temperature range TC,TJTC = -55°C to TJ = 125°C °C

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3. Caution: OVIN must not exceed OVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-

on reset and power-down sequences.

4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

Figure 3-1 shows the undershoot and overshoot voltages at the interfaces of the PC8548E.

Figure 3-1. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD/BVDD

Note: 1. tCLOCK refers to the clock period associated with the respective interface:

For I2C and JTAG, tCLOCK references SYSCLK.

For DDR, tCLOCK references MCLK.

For eTSEC, tCLOCK references EC_GTX_CLK125.

For LBIU, tCLOCK references LCLK.

For PCI, tCLOCK references PCIn_CLK or SYSCLK.

For SerDes, tCLOCK references SD_REF_CLK.

2. Please note that with the PCI overshoot allowed (as specified above), the device does not fully comply

with the maximum AC ratings and device protection guideline outlined in the PCI rev. 2.2 standard (sec-

tion 4.2.2.3).

The core voltage must always be provided at nominal 1.1V. (See Table 3-2 on page 11 for actual recom-

mended core voltage). Voltage to the processor interface I/Os are provided through separate sets of

supply pins and must be provided at the voltages shown in Table 3-2 on page 11. The input voltage

threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are

simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM inter-

face uses a single-ended differential receiver referenced the externally supplied MVREF signal (nominally

set to GVDD/2) as is appropriate for the SSTL2 electrical signaling standard.

GND

GND – 0.3V

GND – 0.7V Not to exceed 10% of tCLOCK

B/G/L/OVDD + 20%

B/G/L/OVDD + 5%

B/G/L/OVDD

VIH

VIL

(1)

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3.3.3 Output Driver Characteristics

Table 3-3 provides information on the characteristics of the output driver strengths. The values are pre-

liminary estimates.

Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in

PORIMPSCR.

2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.

3. The drive strength of the DDR interface in half-strength mode is at TC = 105°C and at GVDD (min).

3.4 Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device

operation. These requirements are as follows for power-up:

1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD, TVDD, XVDD

2. GVDD

All supplies must be at their stable values within 50 ms.

Notes: 1. Items on the same line have no ordering requirement with respect to one another. Items on separate

lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their

value before the voltage rails on the current step reach 10% of theirs.

2. In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is

no concern about any of the DDR signals being in an indeterminate state during power-up, then the

sequencing for GVDD is not required.

Table 3-3. Output Drive Capability

Driver Type

Programmable Output

Impedance (Ω) Supply Voltage Notes

Local bus interface utilities signals

BVDD = 3.3V

BVDD = 2.5V (1)

45 (default)

BVDD = 3.3V

BVDD = 2.5V

PCI signals 25 OVDD = 3.3V (2)

45 (default)

DDR signal 18

36 (half strength mode) GVDD = 2.5V (3)

DDR2 signal 18

36 (half strength mode) GVDD = 1.8V (3)

TSEC/10/100 signals 45 L/TVDD = 2.5/3.3V

DUART, system control, JTAG 45 OVDD = 3.3V

I2C150OV

DD = 3.3V

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4. Power Characteristics

The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for

this family of PowerQUICC III devices is shown in Table 4-1.

Notes: 1. CCB Frequency is the SoC platform frequency, which corresponds to the DDR data rate.

2. SLEEP is based on VDD = 1.1 V, TJ = 65°C.

3. Typical-65 is based on VDD = 1.1 V, TJ = 65°C, running Dhrystone.

4. Typical-105 is based on VDD = 1.1 V, TJ = 105°C, running Dhrystone.

5. Maximum is based on VDD = 1.1 V, TJ = 125°C, running a smoke test.

At allowable voltage levels, the estimated power dissipation on the 1.1V AVDD supplies for the PC8548E

PLLs is shown in Table 4-2.

Because I/O usage varies from design to design, for power dissipation estimates on the G/L/OVDD power

rails, refer to the PowerQUICC III I/O power calculator.

Table 4-1. PC8548E Power Dissipation(1)

CCB

Frequency(1) Core

Frequency SLEEP(2) Typical-65(3) Typical-

105(4) Maximum(5) Unit

400

800 2.7 4.6 7.5 11

W1000 2.7 5.0 7.9 11.6

1200 2.7 5.4 8.3 11.9

533 1333 6.2 7.9 10.8 12.8 W

Table 4-2. PC8548E Estimated I/O Power Dissipation

Interface Parameters 1.1V (XVDD)1.8V (GV

DD)

2.5V

(B/G/L/TVDD)

3.3V

(B/L/O/TVDD) Comments

DDR

266 MHz data 0.31 W 0.59 W

333 MHz data 0.38 W 0.73 W

400 MHz data 0.46 W

533 MHz data 0.60 W

PCI-Express x8, 2.5 G-baud 0.71 W

Serial RapidIO x4, 3.125 G-baud 0.49 W

PCI-X 64-bit, 133 MHz 0.25 W

PCI

64-bit, 66 MHz 0.14 W

64-bit, 33 MHz 0.08 W

32-bit, 66 MHz 0.07 W Power per PCI

port

32-bit, 33 MHz 0.04 W

Local Bus

32-bit, 133 MHz 0.14 W 0.24 W

32-bit, 66MHz 0.07 W 0.13 W

32-bit, 33 MHz 0.04 W 0.07 W

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5. Input Clocks

5.1 System Clock Timing

Table 5-1 provides the system clock (SYSCLK) AC timing specifications for the PC8548E.

Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such SYSCLK fre-

quency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum operating frequencies.

Refer to Section 20.2 ”CCB/SYSCLK PLL Ratio” on page 85” and Section 20.3 ”e500 Core PLL Ratio” on page 86, for ratio

settings.

2. Rise and fall times for SYSCLK are measured at 0.6V and 2.7V

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter – short term and long term – and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be < 500 kHz at -20 dB. The bandwidth must cascade-connected

PLL-based devices to track SYSCLK drivers with the specified jitter.

6. This parameter has been adjusted slower according to the workaround for device erratum GEN-13.

5.2 Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then

used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter specifi-

cation. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB

clock. That is, minimum clock high time is 2 × tCCB, and minimum clock low time is 2 × tCCB. There is no

minimum RTC frequency; RTC may be grounded if not needed.

eTSEC

(10/100/1000

Ethernet)

MII 0.01 W

Power per

eTSEC used

GMII 0.07 W

TBI 0.07 W

RGMII 0.04 W

RTBI 0.04 W

eTSEC

(packet FIFO)

16-bit, 200 MHz 0.20 W

Power per FIFO

interface used

16-bit, 155 MHz 0.16 W

8-bit, 200 MHz 0.11 W

8-bit, 155 MHz 0.08 W

Table 4-2. PC8548E Estimated I/O Power Dissipation (Continued)

Interface Parameters 1.1V (XVDD)1.8V (GV

DD)

2.5V

(B/G/L/TVDD)

3.3V

(B/L/O/TVDD) Comments

Table 5-1. SYSCLK AC Timing Specifications (At Recommended Operating Conditions with OVDD = 3.3V ± 165 mV

(see Table 3-2 on page 11)

Parameter/Condition Symbol Min Typical Max Unit Notes

SYSCLK frequency fSYSCLK 16 – 133 MHz (1)(6)

SYSCLK cycle time tSYSCLK 7.5 – 60 ns (6)

SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns (2)

SYSCLK duty cycle tKHK/tSYSCLK 40 – 60 % (3)

SYSCLK jitter – – – ± 150 ps (4)(5)

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5.3 eTSEC Gigabit Reference Clock Timing

Table 5-2 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for

the PC8548E.

Note: 1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TVDD = 2.5V, and from 0.6 and 2.7V for

L/TVDD = 3.3V.

2. Timing is guaranteed by design and characterization.

3. EC_GTX_CLK125 is used to generate the GTX clock TSECn_GTX_CLK for the eTSEC transmitter with 2% degradation.

EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle gener-

ated by the TSECn_ GTX_CLK. See Section 9.2.6 ”RGMII and RTBI AC Timing Specifications” on page 33 for duty cycle for

10Base-T and 100Base-T reference clock.

5.4 PCI/PCI-X Reference Clock Timing

When the PCI/PCI-X controller is configured for asynchronous operation, the reference clock for the

PCI/PCI-x controller is not the SYSCLK input, but instead the PCIn_CLK. Table 5-3 provides the

PCI/PCI-X reference clock AC timing specifications for the PC8548E.

Notes: 1. Rise and fall times for SYSCLK are measured at 0.6V and 2.7V.

2. Timing is guaranteed by design and characterization.

Table 5-2. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Notes

EC_GTX_CLK125 frequency fG125 – 125 – MHz

EC_GTX_CLK125 cycle time tG125 –8–ns

EC_GTX_CLK125 rise and fall time

- L/TVDD = 2.5V

- L/TVDD = 3.3V

tG125R/tG125F –0.75

1.0 ns (1)

EC_GTX_CLK125 duty cycle

- GMII, TBI

- 1000Base-T for RGMII, RTBI

tG125H/tG125 45

–55

%(2)(3)

Table 5-3. PCIn_CLK AC Timing Specifications (At Recommended Operating Conditions with OVDD = 3.3V ± 165 mV

(see Table 3-2 on page 11)

Parameter/Condition Symbol Min Typical Max Unit Notes

PCIn_CLK frequency fPCICLK 16 – 133 MHz

PCIn_CLK cycle time tPCICLK 7.5 – 60 ns

PCIn_CLK rise and fall time tPCIKH, tPCIKL 0.6 1.0 2.1 ns (1)(2)

PCIn_CLK duty cycle tPCIKHKL/tPCICLK 40–60%(2)

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5.5 Platform to FIFO restrictions

Please note the following FIFO maximum speed restrictions based on platform speed.

For FIFO GMII mode:

FIFO TX/RX clock frequency <= platform clock frequency / 4.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more

than 127 MHz

For FIFO encoded mode:

FIFO TX/RX clock frequency <= platform clock frequency / 3.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more

than 167 MHz.

5.6 Platform Frequency Requirements for PCI-Express and Serial RapidIO

The CCB clock frequency must be considered for proper operation of the high-speed PCI-Express and

Serial RapidIO interfaces as described below.

For proper PCI Express operation, the CCB clock frequency must be greater than:

For proper serial RapidIO operation, the CCB clock frequency must be greater than:

5.7 Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes, and

eTSEC, see the specific section of this document.

6. RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the PC8548E. Table 6-1 provides the RESET initialization AC timing specifications for the DDR SDRAM

component(s).

Note: 1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the PC8548E.

500 MHz x (PCI-Express link width)

2 x (0.80) x (Serial RapidIO interface frequency) x (Serial RapidIO link width)

Table 6-1. RESET Initialization Timing Specifications

Parameter/Condition Min Max Unit Notes

Required assertion time of HRESET 100 – µs

Minimum assertion time for SRESET 3 – SYSCLKs (1)

PLL input setup time with stable SYSCLK before HRESET negation 100 – µs

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET 4 – SYSCLKs (1)

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET 2 – SYSCLKs (1)

Maximum valid-to-high impedance time for actively driven POR configs

with respect to negation of HRESET – 5 SYSCLKs (1)

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Table 6-2 provides the PLL lock times.

7. DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

PC8548E. Note that GVDD(typ) = 2.5V for DDR SDRAM, and GVDD(typ) = 1.8V for DDR2 SDRAM.

7.1 DDR SDRAM DC Electrical Characteristics

Table 7-1 provides the recommended operating conditions for the DDR2 SDRAM controller of the

PC8548E when GVDD(typ) = 1.8V.

Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ± 2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF

. This rail should track variations in the DC level of MVREF

4. Output leakage is measured with all outputs disabled, 0V ≤ VOUT ≤ GVDD.

Table 7-2 provides the DDR capacitance when GVDD(typ) = 1.8V.

Note: 1. This parameter is sampled. GVDD = 1.8V ± 0.090V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2V.

Table 6-2. PLL Lock Times

Parameter/Condition Min Max Unit

Core and platform PLL lock times – 100 µs

Local bus PLL lock time – 50 µs

PCI/PCI-X bus PLL lock time – 50 µs

Table 7-1. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GVDD 1.71 1.89 V (1)

I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V(2)

I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V (3)

Input high voltage VIH MVREF + 0.125 GVDD + 0.3 V

Input low voltage VIL -0.3 MVREF - 0.125 V

Output leakage current IOZ -50 50 µA (4)

Output high current (VOUT = 1.420V) IOH -13.4 – mA

Output low current (VOUT = 0.280V) IOL 13.4 – mA

Table 7-2. DDR2 SDRAM Capacitance for GVDD(typ)=1.8V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, DQS CIO 68pF

(1)

Delta input/output capacitance: DQ, DQS,

DQS CDIO –0.5pF(1)

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Table 7-3 provides the recommended operating conditions for the DDR SDRAM component(s) when

GVDD(typ) = 2.5V.

Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF

. This rail should track variations in the DC level of MVREF

4. Output leakage is measured with all outputs disabled, 0V ≤VOUT ≤GVDD.

Table 7-4 provides the DDR capacitance when GVDD (typ) = 2.5V.

Notes: 1. This parameter is sampled. GVDD = 2.5V ± 0.125V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2,

VOUT (peak-to-peak) = 0.2V.

Table 7-5 provides the current draw characteristics for MVREF.

Notes: 1. The voltage regulator for MVREF must be able to supply up to 500 µA current.

Table 7-3. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GVDD 2.375 2.625 V (1)

I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V(2)

I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V (3)

Input high voltage VIH MVREF + 0.15 GVDD + 0.3 V

Input low voltage VIL -0.3 MVREF – 0.15 V

Output leakage current IOZ -50 50 µA (4)

Output high current (VOUT = 1.95V) IOH -16.2 – mA

Output low current (VOUT = 0.35V) IOL 16.2 – mA

Table 7-4. DDR SDRAM Capacitance for GVDD (typ) = 2.5V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS CIO 68pF

(1)

Delta input/output capacitance: DQ, DQS CDIO –0.5pF(1)

Table 7-5. Current Draw Characteristics for MVREF

Parameter/Condition Symbol Min Max Unit Note

Current draw for MVREF IMVREF –500µA(1)

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7.2 DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface. The DDR controller

supports both DDR1 and DDR2 memories. DDR1 is supported with the following AC timings at data

rates of 333 MHz. DDR2 is supported with the following AC timings at data rates down to 333 MHz.

7.2.1 DDR SDRAM Input AC Timing Specifications

Table 7-6 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 1.8V.

Table 7-7 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5V.

Table 7-8 provides the input AC timing specifications for the DDR SDRAM interface.

Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any cor-

responding bit that will be captured with MDQS[n]. This should be subtracted from the total timing

budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is

called tDISKEW. This can be determined by the following equation:

tDISKEW = ± (T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of

tCISKEW.

Table 7-6. DDR2 SDRAM Input AC Timing Specifications for 1.8V Interface (At Recommended

Operating Conditions)

Parameter Symbol Min Max Unit

AC input low voltage VIL –MVREF – 0.25 V

AC input high voltage VIH MVREF + 0.25 V

Table 7-7. DDR SDRAM Input AC Timing Specifications for 2.5V Interface (At Recommended Oper-

ating Conditions)

Parameter Symbol Min Max Unit

AC input low voltage VIL –MVREF – 0.31 V

AC input high voltage VIH MVREF + 0.31 V

Table 7-8. DDR SDRAM Input AC Timing Specifications (At Recommended Operating Conditions)

Parameter Symbol Min Max Unit Notes

Controller Skew for MDQS–

MDQ/MECC/MDM tCISKEW ps (1)(2)

533 MHz -300 300

400 MHz -365 365

333 MHz -390 390

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7.2.2 DDR SDRAM Output AC Timing Specifications

Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the

rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbol-

izes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup

(S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L)

until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that tDDKHMH follows the symbol conventions described in note (1). For example, tDDKHMH describes the DDR timing

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through

control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the

same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these 2

parameters have been set to the same adjustment value. See the PC8548E PowerQUICC III Integrated Processor Refer-

ence Manual for a description and understanding of the timing modifications enabled by use of these bits.

Table 7-9. DDR SDRAM Output AC Timing Specifications (At Recommended Operating Conditions)

Parameter Symbol(1) Min Max Unit Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 3.75 10 ns (2)

ADDR/CMD output setup with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHAS

1.48

1.95

2.40

–

ns (3)

ADDR/CMD output hold with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHAX

1.48

1.95

2.40

–

ns (3)

MCS[n] output setup with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHCS

1.48

1.95

2.40

–

ns (3)

MCS[n] output hold with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHCX

1.48

1.95

2.40

–

ns (3)

MCK to MDQS Skew tDDKHMH -0.6 0.6 ns (4)

MDQ/MECC/MDM output setup with respect to MDQS

533 MHz

400 MHz

333 MHz

tDDKHDS,

tDDKLDS

538

700

900

–

ps (5)

MDQ/MECC/MDM output hold with respect to MDQS

533 MHz

400 MHz

333 MHz

tDDKHDX,

tDDKLDX

538

700

900

–

ps (5)

MDQS preamble start tDDKHMP -0.5 × tMCK – 0.6 -0.5 x tMCK +0.6 ns (6)

MDQS epilogue end tDDKHME -0.6 0.6 ns (6)

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5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the sym-

bol conventions described in note (1).

Note: For the ADDR/CMD setup and hold specifications in Table 7-9 on page 21, it is assumed that the clock con-

trol register is set to adjust the memory clocks by 1/2 applied cycle.

Figure 7-1 on page 22 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement

(tDDKHMH).

Figure 7-1. Timing Diagram for tDDKHMH

Figure 7-2 shows the DDR SDRAM output timing diagram.

Figure 7-2. DDR SDRAM Output Timing Diagram

MDQS

MCK[n]

MCK[n] tMCK

MDQS

tDDKHMH(max) = 0.6 ns

tDDKHMH(min) = -0.6 ns

ADDR/CMD

MDQ[x]

MDQS[n]

MCK[n]

D1D0

NOOP

tDDKHDX tDDKLDX

tDDKLDS

tDDKHDS

tDDKHMH

tDDKHMP

tDDKHAX, tDDKHCX

tDDKHAS, tDDKHCS

tMCK

Write A0

tDDKHME

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Figure 7-3 provides the AC test load for the DDR bus.

Figure 7-3. DDR AC Test Load

8. DUART

This section describes the DC and AC electrical specifications for the DUART interface of the PC8548E.

8.1 DUART DC Electrical Characteristics

Table 8-1 provides the DC electrical characteristics for the DUART interface.

Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 3-1 on page 10

and Table 3-2 on page 11.

8.2 DUART AC Electrical Specifications

Table 8-2 provides the AC timing parameters for the DUART interface.

Notes: 1. Guaranteed by design

2. fCCB refers to the internal platform clock.

3. Actual attainable baud rate will be limited by the latency of interrupt processing

4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subse-

quent bit values are sampled each 16th sample.

Output Z0 = 50Ω

RL = 50Ω

GVDD /2

Table 8-1. DUART DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL -0.3 0.8 V

Input current (VIN(1) = 0V or VIN = VDD)IIN –±5 µA

High-level output voltage (OVDD = mn, IOH = -100 µA) VOH OVDD– 0.2 – V

Low-level output voltage (OVDD = min, IOL = 100 µA) VOL –0.2 V

Table 8-2. DUART AC Timing specifications

Parameter Value Unit Notes

Minimum baud rate fCCB/1,048,576 baud (1)(2)

Maximum baud rate fCCB clock/16 baud (1)(2)(3)

Oversample rate 16 – (1)(4)

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9. Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

This section provides the AC and DC electrical characteristics for enhanced three-speed and MII

management.

9.1 Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1Gb Mbps) – GMII/MII/TBI/ RGMII/RTBI/RMII Electrical Characteristics

The electrical characteristics specified here apply to all gigabit media independent interface (GMII),

media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface

(RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals

except management data input/output (MDIO) and management data clock (MDC). The RGMII and

RTBI interfaces are defined for 2.5V, while the GMII and TBI interfaces can be operated at 3.3V. The

GMII, MII, or TBI interface timing is compliant with the IEEE Std. 802.3. The RGMII and RTBI interfaces

follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3

(12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2

(3/20/1998). The electrical characteristics for MDIO and MDC are specified in Section 10. ”Ethernet

Management Interface Electrical Characteristics” on page 36.

9.1.1 eTSEC DC Electrical Characteristics

All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric attributes

specified in Table 9-1 and Table 9-2. The RGMII and RTBI signals are based on a 2.5V CMOS interface

voltage as defined by JEDEC EIA/JESD8-5.

Notes: 1. LVDD supports eTSECs 1 and 2.

2. TVDD supports eTSECs 3 and 4.

3. The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 3-1 on page 10 and Table 3-2 on

page 11

Table 9-1. GMII, MII, RMII, and TBI DC Electrical Characteristics

Parameter Symbol Min Max Unit Notes

Supply voltage 3.3V LVDD

TVDD

3.13 3.47 V (1)(2)

Output high voltage

(LVDD/TVDD = Min, IOH = -4.0 mA) VOH 2.40 LVDD/TVDD + 0.3 V

Output low voltage

(LVDD/TVDD = Min, IOL = 4.0 mA) VOL GND 0.50 V

Input high voltage VIH 2.0 LVDD/TVDD + 0.3 V

Input low voltage VIL -0.3 0.90 V

Input high current

(VIN = LVDD, VIN = TVDD)IIH –40µA

(1)(2)(3)

Input low current

(VIN = GND) IIL -600 – µA (3)

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Notes: 1. LVDD supports eTSECs 1 and 2.

2. TVDD supports eTSECs 3 and 4.

3. The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 3-1 on page 10 and Table 3-2 on

page 11.

9.2 FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this

section.

9.2.1 FIFO AC Specifications

The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI

specifications, since they have similar performance and are described in a source-synchronous fashion

like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data

and source clock in GMII fashion.

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the rel-

evant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,

while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit

clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back

out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is

intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a

source- synchronous timing reference. Typically, the clock edge that launched the data can be used,

since the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that

there is relationship between the maximum FIFO speed and the platform speed. For more information

see Section 5.5 ”Platform to FIFO restrictions” on page 17.

Table 9-2. RGMII, RTBI and FIFO DC Electrical Characteristics

Parameter Symbol Min Max Unit Notes

Supply voltage 2.5V LVDD

TVDD

2.37 2.63 V (1)(2)

Output high voltage

(LVDD/TVDD = Min, IOH = -1.0 mA) VOH 2LV

DD/TVDD + 0.3 V

Output low voltage

(LVDD/TVDD = Min, IOL = 1.0 mA) VOL GND - 0.3 0.40 V

Input high voltage VIH 1.70 LVDD/TVDD + 0.3 V

Input low voltage VIL -0.3 0.90 V

Input high current

(VIN = LVDD, VIN = TVDD)IIH –10µA

(1)(2)(3)

Input low current

(VIN = GND) IIL -15 – µA (3)

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A summary of the FIFO AC specifications appears in Table 3-2 and Table 9-4 on page 26.

Timing diagrams for FIFO appear in Figure 9-1 and Figure 9-2 on page 27.

Figure 9-1. FIFO Transmit AC Timing Diagram

Table 9-3. FIFO Mode Transmit AC Timing Specification

Parameter/Condition Symbol Min Typ Max Unit

TX_CLK, GTX_CLK clock period tFIT 5.0 8.0 100 ns

TX_CLK, GTX_CLK duty cycle tFITH/tFIT 45 50 55 %

TX_CLK, GTX_CLK peak-to-peak jitter tFITJ – – 250 ps

Rise time TX_CLK (20%–80%) tFITR ––

0.75 ns

Fall time TX_CLK (80%–20%) tFITF ––

0.75 ns

FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK tFITDV 2.0 ––

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time tFITDX 0.5() –3.0 ns

Table 9-4. FIFO Mode Receive AC Timing Specification

Parameter/Condition Symbol Min Typ Max Unit

RX_CLK clock period tFIR 5.0 8.0 100 ns

RX_CLK duty cycle tFIRH/tFIR 45 50 55 %

RX_CLK peak-to-peak jitter tFIRJ ––

250 ps

Rise time RX_CLK (20%–80%) tFIRR ––

0.75 ns

Fall time RX_CLK (80%–20%) tFIRF ––

0.75 ns

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tFIRDV 1.5 – – ns

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tFIRDX 0.5 – – ns

tFIT

tFITH

tFITF

tFITDX

TXD[7:0]

TX_EN

GTX_CLK

TX_ER

tFITDV

tFITR

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Figure 9-2. FIFO Receive AC Timing Diagram

9.2.2 GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

9.2.2.1 GMII Transmit AC Timing Specifications

Table 9-5 provides the GMII transmit AC timing specifications.

Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing

(GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching

the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock ref-

erence (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 9-3 shows the GMII transmit AC timing diagram.

Figure 9-3. GMII Transmit AC Timing Diagram

tFIR

tFIRH tFIRF

tFIRR

RX_CLK

RXD[7:0]

RX_DV

RX_ER valid data

tFIRDX

tFIRDV

Table 9-5. GMII Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V ± 5%)

Parameter/Condition Symbol(1) Min Typ Max Unit

GMII data TXD[7:0], TX_ER, TX_EN setup time tGTKHDV 2.5 ––

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay tGTKHDX 0.5 –5.0 ns

GTX_CLK data clock rise time (20%-80%) tGTXR(2) ––

1.0 ns

GTX_CLK data clock fall time (80%-20%) tGTXF(2) ––

1.0 ns

GTX_CLK

TXD[7:0]

GTKHDX

GTX

GTXH

GTXR

GTXF

GTKHDV

TX_EN

TX_ER

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9.2.2.2 GMII Receive AC Timing Specifications

Table 9-6 provides the GMII receive AC timing specifications..

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing

(GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to

the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the

clock reference symbol representation is based on three letters representing the clock of a particular functional. For exam-

ple, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with

the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 9-4 provides the AC test load for eTSEC.

Figure 9-4. eTSEC AC Test Load

Figure 9-5 shows the GMII receive AC timing diagram.

Figure 9-5. GMII Receive AC Timing Diagram

Table 9-6. GMII Receive AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V ± 5%)

Parameter/Condition Symbol(1) Min Typ Max Unit

RX_CLK clock period tGRX –8.0 –ns

RX_CLK duty cycle tGRXH/tGRX 40 –60 ns

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tGRDVKH 2.0 ––

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tGRDXKH 0––

RX_CLK clock rise (20%-80%) tGRXR(2) ––

1.0 ns

RX_CLK clock fall time (80%-20%) tGRXF(2) 1.0 ns

LVDD/2

Output Z0 = 50Ω

RL = 50Ω

RX_CLK

RXD[7:0]

tGRDXKH

tGRX

tGRXH

tGRXR

tGRXF

tGRDVKV

RX_DV

RX_ER

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9.2.3 MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

9.2.3.1 MII Receive AC Timing Specifications

Table 9-7 provides the MII transmit AC timing specifications.

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing

(MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock

reference symbol representation is based on two to three letters representing the clock of a particular functional. For exam-

ple, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with

the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 9-6 shows the MII transmit AC timing diagram.

Figure 9-6. MII Transmit AC Timing Diagram

Table 9-7. MII Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V ± 5%)

Parameter/Condition Symbol(1) Min Typ Max Unit

TX_CLK clock period 10 Mbps tMTX(2) – 400 – ns

TX_CLK clock period 100 Mbps tMTX –40–ns

TX_CLK duty cycle tMTXH/tMTX 35–65%

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1.0 5 15 ns

TX_CLK data clock rise (20%-80%) tMTXR(2) 1.0 – 4 ns

TX_CLK data clock fall (80%-20%) tMTXF(2) 1.0 – 4 ns

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

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9.2.3.2 MII Receive AC Timing Specifications

Table 9-8 provides the MII receive AC timing specifications.

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing

(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to

the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the

clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is

used with

2. Guaranteed by design.

Figure 9-7 provides the AC test load for eTSEC.

Figure 9-7. eTSEC AC Test Load

Figure 9-8 shows the MII receive AC timing diagram.

Figure 9-8. MII Receive AC Timing Diagram

Table 9-8. MII Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V ± 5%)

Parameter/Condition Symbol(1) Min Typ Max Unit

RX_CLK clock period 10 Mbps tMRX(2) – 400 – ns

RX_CLK clock period 100 Mbps tMRX –40–ns

RX_CLK duty cycle tMRXH/tMRX 35–65%

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10 – – ns

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10 – – ns

RX_CLK clock rise (20%-80%) tMRXR(2) 1.0 – 4 ns

RX_CLK clock fall time (80%-20%) tMRXF(2) 1.0 – 4 ns

LVDD/2

Output Z0 = 50Ω

RL = 50Ω

RX_CLK

RXD[3:0]

tMRDXKL

tMRX

tMRXH

tMRXR

tMRXF

tMRDVKH

RX_DV

RX_ER

Valid Data

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9.2.4 TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

9.2.4.1 TBI Transmit AC Timing Specifications

Table 9-9 provides the TBI transmit AC timing specifications.

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit tim-

ing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or

setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the

referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol repre-

sentation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX

represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R

(rise) or F (fall).

2. Guaranteed by design.

Figure 9-9 shows the TBI transmit AC timing diagram.

Figure 9-9. TBI Transmit AC Timing Diagram

Table 9-9. TBI Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V ± 5%)

Parameter/Condition Symbol(1) Min Typ Max Unit

TCG[9:0] setup time GTX_CLK going high tTTKHDV 2.0 ––

TCG[9:0] hold time from GTX_CLK going high tTTKHDX 1.0 ––

GTX_CLK rise (20%–80%) tTTXR(2) ––

1.0 ns

GTX_CLK fall time (80%–20%) tTTXF(2) ––

1.0 ns

GTX_CLK

tTTX

tTTXH

tTTXR

tTTXF

tTTKHDV

TCG[9:0]

tTTXF

tTTKHDX

tTTXR

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9.2.4.2 TBI Receive AC Timing Specifications

Table 9-10 provides the TBI receive AC timing specifications.

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing

(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to

the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals

(D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock refer-

ence symbol representation is based on three letters representing the clock of a particular functional. For example, the

subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is

being skewed (TRX).

2. Guaranteed by design.

Figure 9-10 shows the TBI receive AC timing diagram.

Figure 9-10. TBI Receive AC Timing Diagram

9.2.5 TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the rele-

vant eTSEC interface. In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on

TSECn pin (no receive clock is used on in this mode, whereas for the dual-clock mode this is the PMA1

receive clock). The 125-MHz transmit clock is applied on the in all TBI modes.

Table 9-10. TBI Receive AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V ± 5%)

Parameter/Condition Symbol(1) Min Typ Max Unit

PMA_RX_CLK[0:1] clock period tTRX – 16.0 – ns

PMA_RX_CLK[0:1] skew tSKTRX 7.5 –8.5 ns

PMA_RX_CLK[0:1] duty cycle tTRXH/tTRX 40 –60 %

RCG[9:0] setup time to rising PMA_RX_CLK tTRDVKH 2.5 ––ns

RCG[9:0] hold time to rising PMA_RX_CLK tTRDXKH 1.5 ––ns

PMA_RX_CLK[0:1] clock rise time (20%-80%) tTRXR(2) 0.7 –2.4 ns

PMA_RX_CLK[0:1] clock fall time (80%-20%) tTRXF(2) 0.7 –2.4 ns

Valid Data Valid Data

PMA_RX_CLK1

RCG[9:0]

tTRXH

tTRXR

tTRXF

tTRDVKH

PMA_RX_CLK0

tTRDXKH

tTRDVKH

tTRDXKH

tSKTRX

tTRXH

tTRX

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A summary of the single-clock TBI mode AC specifications for receive appears in Table 9-11.

A timing diagram for TBI receive appears in Figure 9-11 on page 33.

Figure 9-11. TBI Single-Clock Mode Receive AC Timing Diagram

9.2.6 RGMII and RTBI AC Timing Specifications

Table 9-12 presents the RGMII and RTBI AC timing specifications.

Notes: 1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the nota-

tion for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the

subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

Table 9-11. TBI single-clock Mode Receive AC Timing Specification

Parameter/Condition Symbol Min Typ Max Unit

RX_CLK clock period tTRRX 7.5 8.0 8.5 ns

RX_CLK duty cycle tTRRH/TRRX 40 50 60 %

RX_CLK peak-to-peak jitter tTRRJ – – 250 ps

Rise time RX_CLK (20%–80%) tTRRR ––1.0ns

Fall time RX_CLK (80%–20%) tTRRF ––1.0ns

RCG[9:0] setup time to RX_CLK rising edge tTRRDVKH 2.0 – – ns

RCG[9:0] hold time to RX_CLK rising edge tTRRDXKH 1.0 – – ns

RCG[9:0]

tTRRDVKH tTRRDXKH

tTRRF

tTRRR

tTRRX

RX_CLK

tTRRH

valid data

Table 9-12. RGMII and RTBI AC Timing Specifications (At Recommended Operating Conditions with LVDD of 2.5V ±5%)

Parameter/Condition Symbol(1) Min Typ Max Unit

Data to clock output skew (at transmitter) tSKRGT(5) -500(6) 0500

(6) ps

Data to clock input skew (at receiver)(2) tSKRGT 1.0–2.8ns

Clock period(3) tRGT(5) 7.288.8ns

Duty cycle for 10BASE-T and 100BASE-TX(3)(4) tRGTH/tRGT(5) 40 50 60 %

Rise time (20%-80%) tRGTR(5) – – 0.75 ns

Fall time (20%-80%) tRGTF(5) – – 0.75 ns

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4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transi-

tioned between.

5. Guaranteed by characterization.

6. In rev 1.0 silicon, due to errata, tSKRGT is -650 ps (Min) and 650 ps (Max). Please refer to “eTSEC 10” in the device errata

document.

Figure 9-12 on page 34 shows the RGMII and RTBI AC timing and multiplexing diagrams.

Figure 9-12. RGMII and RTBI AC Timing and Multiplexing Diagrams

9.2.7 RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

9.2.7.1 RMII Transmit AC Timing Specifications

The RMII transmit AC timing specifications are in Table 9-13.

GTX_CLK

tRGT

tRGTH

tSKRGT

TX_CTL

TXD[8:5]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At Transmitter)

TXD[8:5][3:0]

TXD[7:4][3:0]

TX_CLK

(At PHY)

RX_CTL

RXD[8:5]

RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

RXD[8:5][3:0]

RXD[7:4][3:0]

RX_CLK

(At PHY)

tSKRGT

Table 9-13. RMII Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V ±5%)

Parameter/Condition Symbol(1) Min Typ Max Unit

REF_CLK clock period tRMT 15.0 20.0 25.0 ns

REF_CLK duty cycle tRMTH 35 50 65 %

REF_CLK peak-to-peak jitter tRMTJ ––

250 ps

Rise time REF_CLK (20%–80%) tRMTR 1.0 –2.0 ns

Fall time REF_CLK (80%–20%) tRMTF 1.0 –2.0 ns

REF_CLK to RMII data TXD[1:0], TX_EN delay tRMTDX 1.0 – 10 ns

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Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing

(MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock

reference symbol representation is based on two to three letters representing the clock of a particular functional. For exam-

ple, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with

the appropriate letter: R (rise) or F (fall).

Figure 9-13 shows the RMII transmit AC timing diagram.

Figure 9-13. RMII Transmit AC Timing Diagram

9.2.7.2 RMII Receive AC Timing Specifications

Note: 1. The symbols used for timing specificationsherein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing

(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to

the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the

clock reference symbol representation is based on three letters representing the clock of a particular functional. For exam-

ple, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with

the appropriate letter: R (rise) or F (fall).

Figure 9-14 provides the AC test load for eTSEC.

Figure 9-14. eTSEC AC Test Load

REF_CLK

TXD[1:0]

tRMTDX

tRMT

tRMTH

tRMTR

tRMTF

TX_EN

TX_ER

Table 9-14. RMII Receive AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V ±5%)

Parameter/Condition Symbol(1) Min Typ Max Unit

REF_CLK clock period tRMR 15.0 20.0 25.0 ns

REF_CLK duty cycle tRMRH 35 50 65 %

REF_CLK peak-to-peak jitter tRMRJ ––250ps

Rise time REF_CLK (20%–80%) tRMRR 1.0 – 2.0 ns

Fall time REF_CLK (80%–20%) tRMRF 1.0 – 2.0 ns

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge tRMRDV 4.0 – – ns

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge tRMRDX 2.0 – – ns

LVDD/2

Output Z0 = 50Ω

RL = 50Ω

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Figure 9-15 shows the RMII receive AC timing diagram.

Figure 9-15. RMII Receive AC Timing Diagram

10. Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO (manage-

ment data input/output) and MDC (management data clock). The electrical characteristics for GMII,

RGMII, RMII, TBI and RTBI are specified in Section 9. ”Ethernet: Enhanced Three-Speed Ethernet

(eTSEC), MII Management” on page 24.

10.1 MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3V. The DC electrical characteristics

for MDIO and MDC are provided in Table 10-1.

Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 3-1 on page 10

and Table 3-2 on page 11.

EF_CLK

RXD[1:0]

tRMRDX

tRMR

tRMRH

tRMRR

tRMRF

CRS_DV

RX_ER

tRMRDV

Valid Data

Table 10-1. MII Management DC Electrical Characteristics

Parameter Symbol Min Max Unit

Supply voltage (3.3V) OVDD 3.13 3.47 V

Output high voltage (OVDD = Min, IOH = -1 mA) VOH 2.10 OVDD + 0.3 V

Output low voltage (OVDD = Min, IOL = 1 mA) VOL GND 0.50 V

Input high voltage VIH 2.0 – V

Input low voltage VIL –0.90V

Input high current (OVDD = Max, VIN(1) = 2.1V) IIH –40µA

Input low current (OVDD = Max, VIN = 0.5V) IIL -600 – µA

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10.2 MII Management AC Electrical Specifications

Table 10-2 provides the MII management AC timing specifications.

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data

timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,

tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) rel-

ative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency

divided by 64.)

3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency is

8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and

the minimum frequency is 1.7 MHz.)

4. Guaranteed by design.

5. tplb_clk is the platform (CCB) clock.

Figure 10-1 shows the MII management AC timing diagram.

Figure 10-1. MII Management Interface Timing Diagram

Table 10-2. MII Management AC Timing Specifications (At Recommended Operating Conditions with OVDD is 3.3V

±5%)

Parameter/Condition Symbol(1) Min Max Unit Notes

MDC frequency fMDC 5.2 8.3 MHz (2)(4)

MDC period tMDC 120 192 ns

MDC clock pulse width high tMDCH 32 – ns

MDC to MDIO valid tMDKHDV 16*tCCB ns (5)

MDC to MDIO delay tMDKHDX 10 16*tCCB ns (3)(5)

MDIO to MDC setup time tMDDVKH 5–ns

MDIO to MDC hold time tMDDXKH 0–ns

MDC rise time tMDCR –10ns(4)

MDC fall time tMDHF –10ns(4)

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

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11. Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the PC8548.

11.1 Local Bus DC Electrical Characteristics

Table 11-1 provides the DC electrical characteristics for the local bus interface operating at BVDD = 3.3V

Note: 1. Note that the symbol VIN, in this case, represents the BVIN symbol referenced in Table 3-1 on page 10

and Table 3-2 on page 11.

Table 11-2 provides the DC electrical characteristics for the local bus interface operating at BVDD = 2.5V

DC.

Note: 1. Note that the symbol VIN, in this case, represents the BVIN symbol referenced in Table 3-1 on page 10

and Table 3-2 on page 11.

Table 11-1. Local Bus DC Electrical Characteristics (3.3V DC)

Parameter Symbol Min Max Unit

High-level input voltage VIH 2BV

DD + 0.3 V

Low-level input voltage VIL -0.3 0.8 V

Input current (VIN(1) = 0V or VIN = BVDD)I

IN –± 5µA

High-level output voltage (BVDD = min, IOH = -2 mA) VOH BVDD - 0.2 – V

Low-level output voltage (BVDD = min, IOL = 2 mA) VOL –0.2V

Table 11-2. Local Bus DC Electrical Characteristics (2.5V DC)

Parameter Symbol Min Max Unit

High-level input voltage VIH 1.70 BVDD+ 0.3 V

Low-level input voltage VIL -0.3 0.7 V

Input current (VIN(1) = 0V or VIN = BVDD)IIH –10 µA

IIL -15

High-level output voltage (BVDD = min, IOH = -1 mA) VOH 2.0 BVDD+ 0.3 V

Low-level output voltage (BVDD = min, IOL = 1 mA) VOL GND – 0.3 0.4 V

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11.2 Local Bus AC Electrical Specifications

Table 11-3 describes the general timing parameters of the local bus interface at BVDD = 3.3V DC. For

information about the frequency range of local bus see Section 20.1 ”Clock Ranges” on page 85.

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)

for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock

one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

bypass mode to 0.4 ⋅ BVDD of the signal in question for 3.3V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is pro-

grammed with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between comple-

mentary signals at BVDD/2.

8. Guaranteed by design.

Table 11-3. Local Bus General Timing Parameters (BVDD = 3.3V DC) – PLL Enabled

Parameter Symbol(1) Min Max Unit Notes

Local bus cycle time tLBK 7.5 12 ns (2)

Local bus duty cycle tLBKH/tLBK 43 57 %

LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW 150 ps (7)(8)

Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 1.8 – ns (3)(4)

LGTA/LUPWAIT input setup to local bus clock tLBIVKH2 1.7 – ns (3)(4)

Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 1.0 – ns (3)(4)

LGTA/LUPWAIT input hold from local bus clock tLBIXKH2 1.0 – ns (3)(4)

LALE output transition to LAD/LDP output transition (LATCH

setup and hold time) tLBOTOT 1.5 – ns (6)

Local bus clock to output valid (except LAD/LDP and LALE) tLBKHOV1 –2.0ns

Local bus clock to data valid for LAD/LDP tLBKHOV2 –2.2ns(3)

Local bus clock to address valid for LAD tLBKHOV3 –2.3ns(3)

Local bus clock to LALE assertion tLBKHOV4 2.3 ns (3)

Output hold from local bus clock (except LAD/LDP and LALE) tLBKHOX1 0.7 – ns (3)

Output hold from local bus clock for LAD/LDP tLBKHOX2 0.7 – ns (3)

Local bus clock to output high Impedance (except LAD/LDP and

LALE) tLBKHOZ1 –2.5ns(5)

Local bus clock to output high impedance for LAD/LDP tLBKHOZ2 –2.5ns(5)

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Table 11-4 describes the general timing parameters of the local bus interface at BVDD = 2.5V DC.

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)

for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock

one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

bypass mode to 0.4 ⋅ BVDD of the signal in question for 3.3V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. Figure 9-1 on page 26

provides the AC test load for the local bus.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between comple-

mentary signals at BVDD/2.

8. Guaranteed by design.

Table 11-4. Local Bus Timing Parameters (BVDD = 2.5V): PLL Enabled

Parameter Symbol(1) Min Max Unit Notes

Local bus cycle time tLBK 7.5 12 ns (2)

Local bus duty cycle tLBKH/tLBK 43 57 %

LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW – 150 ps (7)(8)

Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 1.9 – ns (3)(4)

LGTA/LUPWAIT input setup to local bus clock tLBIVKH2 1.8 – ns (3)(4)

Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 1.1 – ns (3)(4)

LGTA/LUPWAIT input hold from local bus clock tLBIXKH2 1.1 – ns (3)(4)

LALE output transition to LAD/LDP output transition (LATCH hold

time) tLBOTOT 1.5 – ns (6)

Local bus clock to output valid (except LAD/LDP and LALE) tLBKHOV1 –2.1ns

Local bus clock to data valid for LAD/LDP tLBKHOV2 –2.3ns(3)

Local bus clock to address valid for LAD tLBKHOV3 –2.4ns(3)

Local bus clock to LALE assertion tLBKHOV4 –2.4ns(3)

Output hold from local bus clock (except LAD/LDP and LALE) tLBKHOX1 0.8 – ns (3)

Output hold from local bus clock for LAD/LDP tLBKHOX2 0.8 – ns (3)

Local bus clock to output high Impedance (except LAD/LDP and

LALE) tLBKHOZ1 –2.6ns(5)

Local bus clock to output high impedance for LAD/LDP tLBKHOZ2 –2.6ns(5)

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Figure 11-1 provides the AC test load for the local bus.

Figure 11-1. Local Bus AC Test Load

Note: PLL bypass mode is recommended when LBIU frequency is at or below 83 MHz. When LBIU operates

above 83 Mhz, LBIU PLL is recommended to be enabled.

Figure 11-2 to Figure 11-7 on page 47 show the local bus signals.

Figure 11-2. Local Bus Signals, (PLL Enabled)

BVDD/2

Output Z0 = 50Ω

RL = 50Ω

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKHOV1

tLBKHOV2

tLBKHOV3

LSYNC_IN

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

Output (Address) Signal:

LAD[0:31]

LALE

tLBIXKH1

tLBIVKH1

tLBIVKH2

tLBIXKH2

tLBKHOX1

tLBKHOZ1

tLBKHOX2

tLBKHOZ2

Input Signal:

LGTA

tLBOTOT

tLBKHOZ2

tLBKHOX2

tLBKHOV4

LUPWAIT

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Table 11-5 describes the timing parameters of the local bus interface at BVDD = 3.3V with PLL disabled.

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)

for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock

one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus

clock because the actual launch and capture of signals is done with the internal launch/capture clock, which preceeds LCLK

by tLBKHKT

3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between comple-

mentary signals at BVDD/2.

4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 × BVDD of the signal

in question for 3.3V signaling levels.

5. Input timings are measured at the pin.

6. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD.

7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

8. Guaranteed by characterization.

9. Guaranteed by design.

Table 11-5. Local Bus Timing Parameters: PLL Bypassed

Parameter Symbol(1) Min Max Unit Notes

Local bus cycle time tLBK 12 –ns (2)

Local bus duty cycle tLBKH/tLBK 43 57 %

Internal launch/capture clock to LCLK delay tLBKHKT 2.3 4.4 ns (8)

Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 6.2 –ns (4)(5)

LGTA/LUPWAIT input setup to local bus clock tLBIVKL2 6.1 –ns (4)(5)

Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 -1.8 –ns (4)(5)

LGTA/LUPWAIT input hold from local bus clock tLBIXKL2 -1.3 –ns (4)(5)

LALE output transition to LAD/LDP output transition (LATCH

hold time) tLBOTOT 1.5 –ns (6)

Local bus clock to output valid (except LAD/LDP and LALE) tLBKLOV1 –-0.3 ns

Local bus clock to data valid for LAD/LDP tLBKLOV2 –-0.1 ns (4)

Local bus clock to address valid for LAD tLBKLOV3 –0ns

(4)

Output hold from local bus clock (except LAD/LDP and LALE) tLBKLOX1 -3.7 –ns (4)

Output hold from local bus clock for LAD/LDP tLBKLOX2 -3.7 –ns (4)

Local bus clock to output high Impedance (except LAD/LDP

and LALE) tLBKLOZ1 –0.2 ns (7)

Local bus clock to output high impedance for LAD/LDP tLBKLOZ2 –0.2 ns (7)

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Figure 11-3. Local Bus Signals (PLL Bypass Mode)

Note: In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of tLBKHKT

. In this mode, signals are

launched at the rising edge of the internal clock and are captured at falling edge of the internal clock withe the exception of

LGTA/LUPWAIT (which is captured on on the rising edge of the internal clock).

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKLOV2

LCLK[n]

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

LALE

tLBIXKH1

Input Signal:

LGTA

Output (Address) Signal:

LAD[0:31]

tLBIVKH1

tLBIXKL2

tLBIVKL2

tLBKLOX1

tLBKLOZ2

tLBOTOT

Internal launch/capture clock

tLBKLOX2

tLBKLOV1

tLBKLOV3

tLBKLOZ1

tLBKHKT

tLBKLOV4

LUPWAIT

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Figure 11-4. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enabled)

LSYNC_IN

UPM Mode Input Signal:

LUPWAIT

tLBIXKH2

tLBIVKH2

tLBIVKH1

tLBIXKH1

tLBKHOZ1

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

tLBKHOV1

tLBKHOV1 tLBKHOZ1

GPCM Mode Input Signal:

LGTA

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Figure 11-5. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)

tLBIVKH1

tLBIXKL2

Internal launch/capture clock

UPM Mode Input Signal:

LUPWAIT

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

tLBKLOV1

tLBKLOZ1

LCLK

tLBKLOX1

tLBIXKH1

GPCM Mode Input Signal:

LGTA tLBIVKL2

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Figure 11-6. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Enabled)

LSYNC_IN

UPM Mode Input Signal:

LUPWAIT

tLBIXKH2

tLBIVKH2

tLBIVKH1

tLBIXKH1

tLBKHOZ1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

tLBKHOV1

tLBKHOV1 tLBKHOZ1

Input Signals:

LAD[0:31]/LDP[0:3]

GPCM Mode Input Signal:

LGTA

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Figure 11-7. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Bypass Mode)

12. Programmable Interrupt Controller

In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed

polarity), it must remain the assertion for at lest 3 system clocks (SYSCLK periods).

tLBIXKL2

tLBIVKH1

Internal launch/capture clock

UPM Mode Input Signal:

LUPWAIT

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

Input Signals:

LAD[0:31]/LDP[0:3]

LCLK

tLBKLOV1

tLBKLOZ1

tLBKLOX1

tLBIXKH1

GPCM Mode Input Signal:

LGTA

tLBIVKL2

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13. JTAG

This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface

of the PC8548E.

13.1 JTAG DC Electrical Characteristics

Table 13-1 provides the DC electrical characteristics for the JTAG interface.

Note: 1. Note that the symbol VIN, in this case, represents the OVIN.

13.2 JTAG AC Electrical Specifications

Table 13-2 provides the JTAG AC timing specifications as defined in Figure 13-2 through Figure 13-4 on

page 50.

Table 13-1. JTAG DC Electrical Characteristics

Parameter Symbol(2) Min Max Unit

High-level input voltage VIH 2.0 OVDD + 0.3 V

Low-level input voltage VIL -0.3 0.8 V

Input current

(VIN(1) = 0 V or VIN = VDD)IIN –±5µA

High-level output voltage

(OVDD = min, IOH = -2 mA) VOH 2.4 – V

Low-level output voltage

(OVDD = min, IOL = 2 mA) VOL –0.4V

Table 13-2. JTAG AC Timing Specifications (Independent of SYSCLK)(1)

Parameter Symbol(2) Min Max Unit Notes

JTAG external clock frequency of operation fJTG 033.3MHz

JTAG external clock cycle time tJTG 30 – ns

JTAG external clock pulse width measured at 1.4V tJTKHKL 15 – ns

JTAG external clock rise and fall times tJTGR & tJTGF 02.0ns(6)

TRST assert time tTRST 25 – ns (3)

Input setup times:

- Boundary-scan data

- TMS, TDI

tJTDVKH

tJTIVKH

–

ns (4)

Input hold times:

- Boundary-scan data

- TMS, TDI

tJTDXKH

tJTIXKH

–

ns (4)

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Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50Ω load (see Figure 13-1 on

page 49). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing

(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to

the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)

went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to tTCLK.

5. Non-JTAG signal output timing with respect to tTCLK.

6. Guaranteed by design.

Figure 13-1 provides the AC test load for TDO and the boundary-scan outputs.

Figure 13-1. AC Test Load for the JTAG Interface

Figure 13-2 provides the JTAG clock input timing diagram.

Figure 13-2. JTAG Clock Input Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2).

Valid times:

- Boundary-scan data

- TDO

tJTKLDV

tJTKLOV

ns (5)

Output hold times:

- Boundary-scan data

- TDO

tJTKLDX

tJTKLOX

ns (5)

JTAG external clock to output high impedance:

- Boundary-scan data

- TDO

tJTKLDZ

tJTKLOZ

9ns (5)(6)

Table 13-2. JTAG AC Timing Specifications (Independent of SYSCLK)(1) (Continued)

Parameter Symbol(2) Min Max Unit Notes

OVDD/2

Output Z0 = 50Ω

RL = 50Ω

VMVMVM

tJTG

tJTGR tJTGF

tJTKHKL

JTAG

External Clock

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Figure 13-3 provides the TRST timing diagram.

Figure 13-3. TRST Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2).

Figure 13-4 provides the boundary-scan timing diagram.

Figure 13-4. Boundary-scan Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2).

14. I2C

This section describes the DC and AC electrical characteristics for the I2C interface of the PC8548E.

14.1 I2C DC Electrical Characteristics

Table 14-1 provides the DC electrical characteristics for the I2C interface.

Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. Refer to the PC8548E PowerQUICC III Integrated Host Processor Reference Manual for information on the digital filter used.

3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.

TRST tTRST

VMJTAG

External Clock

Boundary

Data Inputs

Boundary

Data Outputs

Boundary

Data Outputs

tJTDXKH

tJTDVKH

tJTKLDV

tJTKLDZ

Output Data Valid

tJTKLDX

Input

Data Valid

Output Data Valid

Table 14-1. I2C DC Electrical Characteristics (At Recommended Operating Conditions with OVDD of 3.3V ± 5%)

Parameter Symbol Min Max Unit Notes

Input high voltage level VIH 0.7 × OVDD OVDD + 0.3 V

Input low voltage level VIL -0.3 0.3 × OVDD V

Low level output voltage VOL 0 0.2 × OVDD V(1)

Pulse width of spikes which must be suppressed by

the input filter tI2KHKL 050ns(2)

Input current each I/O pin (input voltage is between

0.1 × OVDD and 0.9 × OVDD (max) II-10 10 µA (3)

Capacitance for each I/O pin CI–10pF

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14.2 I2C AC Electrical Specifications

Table 14-2 provides the AC timing parameters for the I2C interfaces.

Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with

respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H)

state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S)

went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C tim-

ing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropri-

ate letter: R (rise) or F (fall).

2. PC8548E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the

undefined region of the falling edge of SCL. As a transmitter, the PC8548E provides a delay time of at least 300 ns for the

SDA signal (referred to the Vihmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unin-

tended generation of Start or Stop condition. When PC8548Eacts as the I2C bus master while transmitting, PC8548E drives

both SCL and SDA. As long as the load on SCL and SDA are balanced, PC8548E would not cause unintended generation

of Start or Stop condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the

300 ns SDA output delay time is required for PC8548E as transmitter, the following setting is recommended for the FDR bit

field of the I2CFDR register to ensure both the desired I2C SCL clock frequency and SDA output delay time are achieved,

assuming that the desired I2C SCL clock frequency is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is

programmed with its default setting of 0x10 (decimal 16):

Table 14-2. I2C AC Electrical Specifications (All Values Refer to VIH (min) and VIL (max) Levels (see Table 14-1)

Parameter Symbol(1) Min Max Unit

SCL clock frequency fI2C 0 400 kHz

Low period of the SCL clock tI2CL(5) 1.3 – µs

High period of the SCL clock tI2CH(5) 0.6 – µs

Setup time for a repeated START condition tI2SVKH(5) 0.6 – µs

Hold time (repeated) START condition (after this period, the first

clock pulse is generated) tI2SXKL(5) 0.6 – µs

Data setup time tI2DVKH(5) 100 – ns

Data hold time:

- CBUS(4) compatible masters

- I2C bus devices

tI2DXKL –

0(2)

–

0.9(3)

µs

Set-up time for STOP condition tI2PVKH 0.6 – µs

Bus free time between a STOP and START condition tI2KHDX 1.3 µs

Noise margin at the LOW level for each connected device

(including hysteresis) VNL 0.1 × OVDD V

Noise margin at the HIGH level for each connected device

(including hysteresis) VNH 0.2 × OVDD V

I2C Source Clock Frequency 333 MHz 266 MHz 200 MHz 133 MHz

FDR Bit Setting 0x2A 0x05 0x26 0x00

Actual FDR Divider Selected 896 704 512 384

Actual I2C SCL Frequency Generated 371 KHz 378 KHz 390 KHz 346 KHz

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For the detail of I2C frequency calculation, refer to the application note AN2919 “Determining the I2C Fre-

quency Divider Ratio for SCL”. Note that the I2C Source Clock Frequency is half of the CCB clock

frequency for MPC8548E.

3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. CB = capacitance of one bus line in pF.

5. Guaranteed by design.

Figure 14-1 provides the AC test load for the I2C.

Figure 14-1. I2C AC Test Load

Figure 14-2 shows the AC timing diagram for the I2C bus.

Figure 14-2. I2C Bus AC Timing Diagram

15. PCI/PCI-X

Table 15-1 on page 52 describes the DC and AC electrical specifications for the PCI/PCI-X bus of the

PC8548E. Note that the maximum PCI-X frequency in synchronous mode is 110 MHz.

15.1 PCI/PCI-X DC Electrical Characteristics

Table 15-1 provides the DC electrical characteristics for the PCI/PCI-X interface.

Notes: 1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus

Specifications.

2. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 3-1 on page 10

and Table 3-2 on page 11.

OVDD/2

Output Z0 = 50Ω

RL = 50Ω

SrS

SDA

SCL

tI2SVKH

tI2KHKL

tI2CF

tI2CL

tI2SXKL

tI2DXKL, tI2OVKL

tI2CH

tI2DVKH

tI2SXKL tI2CR

tI2CF

tI2PVKH

Table 15-1. PCI/PCI-X DC Electrical Characteristics(1)

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL -0.3 0.8 V

Input current (VIN(2) = 0V or VIN = VDD)I

IN –± 5µA

High-level output voltage (OVDD = min, IOH = -100 µA) VOH OVDD – 0.2 – V

Low-level output voltage (OVDD = min, IOL = 100 µA) VOL –0.2V

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15.2 PCI/PCI-X AC Electrical Specifications

This section describes the general AC timing parameters of the PCI/PCI-X bus. Note that the clock refer-

ence CLK is represented by SYSCLK when the PCI controller is configured for asynchronous mode and

by PCIn_CLK when it is configured for asynchronous mode.

Table 15-2 provides the PCI AC timing specifications at 66 MHz.

Notes: 1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (refer-

ence)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes

PCI/PCI-X timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock,

tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI/PCI-X timing (PC) with respect to

the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 ⋅ OVDD of the signal in question for 3.3V

PCI signaling levels.

4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

5. Input timings are measured at the pin.

6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The

system clock period must be kept within the minimum and maximum defined ranges. For values see Section 20. ”Clocking”

on page 85.

7. The setup and hold time is with respect to the rising edge of HRESET.

8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus

Specifications.

9. The reset assertion timing requirement for HRESET is 100 ⎧s.

10. Guaranteed by characterization.

11. Guaranteed by design.

Figure 15-1 provides the AC test load for PCI and PCI-X.

Figure 15-1. PCI/PCI-X AC Test Load

Table 15-2. PCI AC Timing Specifications at 66 MHz

Parameter Symbol(1) Min Max Unit Notes

SYSCLK to output valid tPCKHOV –6ns

(2)(3)

Output hold from SYSCLK tPCKHOX 2–ns

(2)(10)

SYSCLK to output high impedance tPCKHOZ –14ns

(2)(4)(11)

Input setup to SYSCLK tPCIVKH 3–ns

(2)(5)(10)

Input hold from SYSCLK tPCIXKH 0–ns

(2)(5)(10)

REQ64 to HRESET(9) setup time tPCRVRH 10 × tSYS –clocks

(6)(7)(11)

HRESET to REQ64 hold time tPCRHRX 050ns

(7)(11)

HRESET high to first FRAME assertion tPCRHFV 10 – clocks (8)(11)

OVDD/2

Output Z0 = 50Ω

RL = 50Ω

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Figure 15-2 shows the PCI/PCI-X input AC timing conditions.

Figure 15-2. PCI/PCI-X Input AC Timing Measurement Conditions

Figure 15-3 shows the PCI/PCI-X output AC timing conditions.

Figure 15-3. PCI/PCI-X Output AC Timing Measurement Condition

Table 15-3 provides the PCI-X AC timing specifications at 66 MHz.

Notes: 1. See the timing measurement conditions in the PCI-X 1.0a Specification.

2. Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and

load circuit.

3. Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.

PCIVKH

CLK

Input

PCIXKH

CLK

High-Impedance

Output

Output Delay

tPCKHOV

tPCKHOZ

Table 15-3. PCI-X AC Timing Specifications at 66 MHz

Parameter Symbol Min Max Unit Notes

SYSCLK to signal valid delay tPCKHOV –3.8ns

(1)(2)(3)(7)(8)

Output hold from SYSCLK tPCKHOX 0.7 – ns (1)(10)

SYSCLK to output high impedance tPCKHOZ –7ns

(1)(4)(8)(11)

Input setup time to SYSCLK tPCIVKH 1.7 – ns (3)(5)

Input hold time from SYSCLK tPCIXKH 0.5 – ns (10)

REQ64 to HRESETsetup time tPCRVRH 10 – clocks (11)

HRESET to REQ64 hold time tPCRHRX 050ns

(11)

HRESET high to first FRAME assertion tPCRHFV 10 – clocks (9)(11)

PCI-X initialization pattern to HRESET setup time tPCIVRH 10 – clocks (11)

HRESET to PCI-X initialization pattern hold time tPCRHIX 050ns

(6)(11)

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4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

5. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.

6. Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, tPCRHFV).

The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks

before the first FRAME and must be floated no later than one clock before FRAME is asserted.

7. A PCI-X device is permitted to have the minimum values shown for tPCKHOV and tCYC only in PCI-X mode. In conventional

mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency.

8. Device must meet this specification independent of how many outputs switch simultaneously.

9. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification.

10. Guaranteed by characterization.

11. Guaranteed by design.

Table 15-4 provides the PCI-X AC timing specifications at 133 MHz.

Note that the maximum PCI-X frequency in synchronous mode is 110 MHz.