Programmable FemtoClock(R) NG 3.3V, 2.5V LVPECL Oscillator Replacement 83PN15639 Datasheet General Description Features The 83PN15639 is a programmable LVPECL synthesizer that is "forward" footprint compatible with standard 5mm x 7mm oscillators. The device uses IDT's fourth generation FemtoClock(R) NG technology for an optimum of high clock frequency and low phase noise performance. Forward footprint compatibility means that a board designed to accommodate the crystal oscillator interface and the optional control pins are also fully compatible with a canned oscillator footprint - the canned oscillator will drop onto the 10-VFQFN footprint for second sourcing purposes. This capability provides designers with programability and lead time advantages of silicon/crystal based solutions while maintaining compatibility with industry standard 5mm x 7mm oscillator footprints for ease of supply chain management. Oscillator-level performance is maintained with IDT's 4th Generation FemtoClock(R) NG PLL technology, which delivers sub 0.2ps RMS phase jitter. * * * * Fourth Generation FemtoClock(R) NG technology * * * * * * * Output frequency: 100MHz - 156.25390625MHz Footprint compatible with 5mm x 7mm differential oscillators One differential LVPECL output pair Crystal oscillator interface which can also be overdriven using a single-ended reference clock Crystal/input frequency: 25MHz, 12pF parallel resonant crystal VCO range: 2GHz - 2.5GHz RMS phase jitter @ 156.25MHz, 10kHz - 1MHz: 0.179ps (typical) Full 3.3V or 2.5V operating supply -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging The 83PN15639 defaults to 156.25MHz using a 25MHz crystal but can also be set to one of four different frequency multiplier settings to support a wide variety of applications. The table below shows some of the more common application settings. Common Applications and Settings Application(s) 25 100 PCI Express 01 25 125 Ethernet 10 25 150 SAS, Embedded Processor 11 (default) 25 156.25 10 Gigabit Ethernet (default) 11 (default) 25.000625 156.25390625 Pin Assignment 10 GbE, Frequency Margining (+25ppm) OE 1 Block Diagram OE XTAL_IN 25MHz XTAL_OUT Pullup OSC PFD & LPF FemtoClock(R) NG VCO 2 - 2.5GHz /N FSEL1 Control Logic (c)2016 Integrated Device Technology, Inc VEE 3 4 5 8 VCC 7 nQ 6 Q 10-Lead VFQFN 5mm x 7mm x 1mm package body NR Package Top View Pullup Pullup 2 9 83PN15639 /M FSEL0 Q nQ RESERVED 10 XTAL_IN 00 XTAL_OUT Output Frequency (MHz) FSEL0 XTAL (MHz) FSEL1 FSEL1, FSEL0 1 Revision B August 16, 2016 83PN15639 Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 OE Input 2 RESERVED Reserve Pullup Output enable. LVCMOS/LVTTL interface levels. 3 VEE Power 4, 5 XTAL_OUT XTAL_IN Input 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8 VCC Power Power supply pin. 9 FSEL0 Input Pullup Output divider control inputs. Sets the output divider value to one of four values. LVCMOS/LVTTL interface levels. 10 FSEL1 Input Pullup Output divider control inputs. Sets the output divider value to one of four values. LVCMOS/LVTTL interface levels. Reserved pin. Do not connect. Negative supply pin. Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance RPULLUP Input Pullup Resistor (c)2016 Integrated Device Technology, Inc. Test Conditions OE, FSEL0, FSEL1 2 Minimum Typical Maximum Units 3.5 pF 51 k Revision B August 16, 2016 83PN15639 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 36.8C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 120 140 mA Table 4B. Power Supply DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 117 135 mA Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current OE, FSEL[1:0] VCC = VIN = 3.465V or 2.625V IIL Input Low Current OE, FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V (c)2016 Integrated Device Technology, Inc. Test Conditions Minimum VCC = 3.465V Maximum Units 2 VCC + 0.3 V VCC = 2.625V 1.7 VCC + 0.3 V VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V 5 A 3 -150 Typical A Revision B August 16, 2016 83PN15639 Datasheet Table 4D. LVPECL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL VSWING Test Conditions Minimum Typical Maximum Units VCC - 1.3 VCC - 0.8 V Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.6 V Peak-to-Peak Output Voltage Swing 0.5 1.0 V Maximum Units NOTE 1: Outputs termination with 50 to VCC - 2V. Table 5. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Fundamental 25 MHz 25.000625 MHz Frequency Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF (c)2016 Integrated Device Technology, Inc. 4 Revision B August 16, 2016 83PN15639 Datasheet AC Electrical Characteristics Table 6. AC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter fOUT Output Frequency tjit(O) RMS Phase Jitter (Random); NOTE 1 tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 100 Maximum Units 156.25390625 MHz 156.25MHz, Integration Range: 10kHz - 1MHz 0.179 0.220 ps 150MHz, Integration Range: 12kHz - 20MHz 0.249 0.316 ps 125MHz, Integration Range: 12kHz - 20MHz 0.241 0.306 ps 100MHz, Integration Range: 12kHz - 20MHz 0.249 0.316 ps 20 ps 100 400 ps 48 52 % 20% to 80% NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz, 12pF resonant crystal. NOTE 1: Please refer to the Phase Noise plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. (c)2016 Integrated Device Technology, Inc. 5 Revision B August 16, 2016 83PN15639 Datasheet Parameter Measurement Information 2V 2V VCC Q SCOPE VCC LVPECL Q SCOPE LVPECL nQ nQ VEE VEE -0.5V0.125V -1.3V0.165V 3.3V LVPECL Output Load AC Test Circuit 2.5V LVPECL Output Load AC Test Circuit nQ Q tcycle n tcycle n+1 tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles RMS Phase Jitter Cycle-to-Cycle Jitter nQ nQ Q Q Output Rise/Fall Time (c)2016 Integrated Device Technology, Inc. Output Duty Cycle/Pulse Width/Period 6 Revision B August 16, 2016 83PN15639 Datasheet Applications Information Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullup resistor; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 1. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12mils to 13mils (0.30mm to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 1. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) (c)2016 Integrated Device Technology, Inc. 7 Revision B August 16, 2016 83PN15639 Datasheet Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 2A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 2B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. VCC XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface (c)2016 Integrated Device Technology, Inc. 8 Revision B August 16, 2016 83PN15639 Datasheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 R2 84 Figure 3B. 3.3V LVPECL Output Termination (c)2016 Integrated Device Technology, Inc. 9 Revision B August 16, 2016 83PN15639 Datasheet Termination for 2.5V LVPECL Outputs Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V 2.5V VCC = 2.5V R1 250 R3 250 50 + 50 - 2.5V LVPECL Driver R2 62.5 R4 62.5 Figure 4A. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50 + 50 - 2.5V LVPECL Driver R1 50 R2 50 Figure 4C. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50 + 50 - 2.5V LVPECL Driver R1 50 R2 50 R3 18 Figure 4B. 2.5V LVPECL Driver Termination Example (c)2016 Integrated Device Technology, Inc. 10 Revision B August 16, 2016 83PN15639 Datasheet Schematic Example Figure 5 shows an example 83PN15639 application schematic in which the device is operated at VCC = +3.3V. The schematic example focuses on functional connections and is intended as an example only and may not represent the exact user configuration. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. For example OE and FSEL[1:0] can be configured from an FPGA instead of set with pull up and pull down resistors as shown. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the VCC pin from power supply is required. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1F capacitor on the VCC pin must be placed on the device side with direct return to the ground plane though vias. The remaining filter components can be on the opposite side of the PCB. Power supply filter component recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. Logic Control Input Ex amples VCC Set Logic Input to '1' VCC RU1 1K S et Logic Input to '0' RU2 Not Install 3.3V To Logic Input pins To Logic Input pins RD1 Not Install 2 VCC RD2 1K FB1 C4 10uF 1 BLM18BB221SN1 C5 0.1uF P lace 0.1 uF b ypas s cap dir ectl y ad jace nt to the V CC p in a nd o n th e com pone nt s ide. VCC 9 10 FSEL0 FSEL1 1 OE 2 5 25MHz (12pf ) 4 8 FSEL0 FSEL1 Zo = 50 Ohm OE Q 6 + RESERVED XTAL_IN nQ 7 Zo = 50 Ohm +3.3V PECL Receiver XTAL_OUT R1 50 VEE X1 C2 4pF R2 50 R3 50 3 C1 4pF C3 0.1uF VCC U1 For AC termination options consult the IDT Applications Note "Termination - LVPECL" Figure 5. 83PN15639 Application Schematic (c)2016 Integrated Device Technology, Inc. 11 Revision B August 16, 2016 83PN15639 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 83PN15639. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 83PN15639 is the sum of the core power plus the power dissipation due to the load. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation due to th e load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW * Power (outputs)MAX = 32mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 32mW = 517.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 36.8C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.517W * 36.8C/W = 104C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 10-Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards (c)2016 Integrated Device Technology, Inc. 0 1 2 36.8C/W 31.7C/W 30.1C/W 12 Revision B August 16, 2016 83PN15639 Datasheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. The LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate power dissipation due to the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V. * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.8V (VCC_MAX - VOH_MAX) = 0.8V * For logic low, VOUT = VOL_MAX = VCC_MAX - 1.6V (VCC_MAX - VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.8V)/50] * 0.8V = 19.2mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.6V)/50] * 1.6V = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW (c)2016 Integrated Device Technology, Inc. 13 Revision B August 16, 2016 83PN15639 Datasheet Reliability Information Table 8. JA vs. Air Flow Table for a 10-Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 36.8C/W 31.7C/W 30.1C/W Transistor Count The transistor count for 83PN15639 is: 47,515 (c)2016 Integrated Device Technology, Inc. 14 Revision B August 16, 2016 83PN15639 Datasheet 10-Lead VFQFN, NR Suffix Package Outline D A B aaa C 2x E 4 INDEX AREA (D/2 xE/2) aaa C 2x 9 TOP VIEW A1 ccc C A C 8 SEATING PLANE SIDE VIEW 3.70 0.08 C e1 NX L2 7 NX b1 bbb C A B NX b2 7 C A B e2 E2 6.25 bbb 4 INDEX AREA (D/2 xE/2) D2 BOTTOM VIEW NX L1 PIN#1 ID FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES. ORIGINATOR ZAHRUL DWG. NO : PKGML00305 DRAFT 1 MLP QUAD PACKAGE OUTLINE ENGINEERING MANAGER TOOLING MANAGER ARAVEN TECH. SALES MANAGER KANDA DATE 2007-APR-18 (c)2016 Integrated Device Technology, Inc. 5.00x7.00 MLPQ 10LD 1.00/2.54 Pitch Page 1 Of 4 15 Revision B August 16, 2016 83PN15639 Datasheet 10-Lead VFQFN, NR Suffix Package Outline, continued COMMON DIMENSION TOLERANCE OF FORM AND POSITION 0.15 0.10 0.10 aaa bbb ccc SYMBOL MIN 0.80 0.00 1, 2 A A1 NOTES COMMON DIMENSION V : Very thin NOM 0.90 0.02 1, 2 Summary Table Body Size 5.00X7.00 Lead Count 10 Lead Pitch (e1 & e2) 1.00/2.54 MAX 1.00 0.05 1, 2 Very Very Thin Variation Pin #1 ID VNJR-1 R0.30 FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES. ORIGINATOR ZAHRUL DWG. NO : PKGML00305 DRAFT 1 MLP QUAD PACKAGE OUTLINE ENGINEERING MANAGER TOOLING MANAGER ARAVEN TECH. SALES MANAGER KANDA DATE 2007-APR-18 (c)2016 Integrated Device Technology, Inc. 5.00x7.00 MLPQ 10LD 1.00/2.54 Pitch PAGE: 2 of 4 16 Revision B August 16, 2016 83PN15639 Datasheet 10-Lead VFQFN, NR Suffix Package Outline, continued NOTE: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters, angles are in degrees(). 3. N is the total number of terminals. 4. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SPP-002. 5. ND and NE refer to the number of terminals on each D and E side respectively. 6. NJR refers to NON JEDEC REGISTERED 7. Dimension b applies to metallized terminal and is measured between 0.10mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 8. Coplanarity applies to the terminals and all other bottom surface metallization. 9. Drawing shown are for illustration only. FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES. ORIGINATOR ZAHRUL DWG. NO : PKGML00305 DRAFT 1 MLP QUAD PACKAGE OUTLINE ENGINEERING MANAGER TOOLING MANAGER ARAVEN TECH. SALES MANAGER KANDA DATE 2007-APR-18 (c)2016 Integrated Device Technology, Inc. 5.00x7.00 MLPQ 10LD 1.00/2.54 Pitch PAGE: 3 of 4 17 Revision B August 16, 2016 83PN15639 Datasheet 10-Lead VFQFN, NR Suffix Package Outline, continued Var ia Sym tion VNJR-1 bol D BSC 5.00 7.00 E BSC MIN 0.35 b1 NOM 0.40 MAX 0.45 MIN 1.35 b2 NOM 1.40 MAX 1.45 MIN 1.55 D2 NOM 1.70 MAX 1.80 3.55 MIN 3.70 E2 NOM 3.80 MAX 0.45 MIN 0.55 L1 NOM 0.65 MAX MIN 1.00 L2 NOM 1.10 MAX 1.20 N 10 ND 2 NE 3 NOTES PAD DESIGN Not e FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES. ORIGINATOR ZAHRUL DWG. NO : PKGML00305 DRAFT 1 MLP QUAD PACKAGE OUTLINE ENGINEERING MANAGER TOOLING MANAGER ARAVEN TECH. SALES MANAGER KANDA DATE 2007-APR-18 (c)2016 Integrated Device Technology, Inc. 5.00x7.00 MLPQ 10LD 1.00/2.54 Pitch PAGE: 4 of 4 18 Revision B August 16, 2016 83PN15639 Datasheet Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 83PN15639ANRGI IDT83PN15639ANRGI "Lead-Free" 10-Lead VFQFN Tray -40C to 85C 83PN15639ANRGI8 IDT83PN15639ANRGI "Lead-Free" 10Lead VFQFN Tape & Reel -40C to 85C (c)2016 Integrated Device Technology, Inc. 19 Revision B August 16, 2016 83PN15639 Datasheet Revision History] Revision Date August 16, 2016 Description of Change Added package dimensions to package outline. (c)2016 Integrated Device Technology, Inc. 20 Revision B August 16, 2016 83PN15639 Datasheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved. (c)2016 Integrated Device Technology, Inc 21 August 16, 2016