83PN15639ANRGI8 - IDT - Datasheet.Directory

General Description

The 83PN15639 is a programmable LVPECL synthesizer that is “for-

ward” footprint compatible with standard 5mm x 7mm oscillators.

The device uses IDT’s fourth generation FemtoClock® NG technolo-

gy for an optimum of high clock frequency and low phase noise per-

formance. Forward footprint compatibility means that a board

designed to accommodate the crystal oscillator interface and the op-

tional control pins are also fully compatible with a canned oscillator

footprint - the canned oscillator will drop onto the 10-VFQFN foot-

print for second sourcing purposes. This capability provides design-

ers with programability and lead time advantages of silicon/crystal

based solutions while maintaining compatibility with industry stan-

dard 5mm x 7mm oscillator footprints for ease of supply chain man-

agement. Oscillator-level performance is maintai ned with IDT’s 4th

Generation FemtoClock® NG PLL technology, which delivers sub

0.2ps RMS phase jitter.

The 83PN15639 defaults to 156.25MHz using a 25MHz crystal but

can also be set to one of four different frequency multiplier settings

to support a wide variety of applications. The table below shows

some of the more common application settings.

Features

•Fourth Generation FemtoClock® NG technology

•Footprint compatible with 5mm x 7mm differential oscillators

•One differential LVPECL output pair

•Crystal oscillator interface which can also be overdriven using a

single-ended reference clock

•Output frequency: 100MHz - 156.25390625MHz

•Crystal/input frequency: 25MHz, 12pF parallel resonant crystal

•VCO range: 2GHz – 2.5GHz

•RMS phase jitter @ 156.25MHz, 10kHz – 1MHz: 0.179ps (typical)

•Full 3.3V or 2.5V operating supply

•-40°C to 85°C ambient operating temperature

•Lead-free (RoHS 6) packaging

Common Applications and Settings

Block Diagram

FSEL1, FSEL0 XTAL (MHz) Output Frequency (MHz) Application(s)

00 25 100 PCI Express

01 25 125 Ethernet

10 25 150 SAS, Embedded Processor

11 (default) 25 156.25 10 Gigabit Ethernet (defau lt)

11 (default) 25.000625 156.25390625 10 GbE, Frequency

Margining (+25ppm)

Pullup

Pullup Control

Logic

OSC

÷M

÷N

FemtoClock® NG

VCO

2 - 2.5GHz

XTAL_IN

25MHz

XTAL_OUT

FSEL0

FSEL1

PFD

LPF Q

VCC

RESERVED

XTAL_IN

XTAL_OUT

FSEL0

FSEL1

345

VEE

Pin Assignment

83PN15639

10-Lead VFQFN

5mm x 7mm x 1mm

package body

NR Package

Top View

83PN15639

Datasheet

Programmable FemtoClock® NG 3.3V,

2.5V LVPECL Oscillator Replacement

83PN15639 Datasheet

Pin Descriptions and Characteristics

Table 1. Pin Descriptions

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1 OE Input Pullup Output enable. LVCMOS/LVTTL interface levels.

2 RESERVED Reserve Reserved pin. Do not connect.

EE Power Negative supply pin.

5XTAL_OUT

XTAL_IN Input Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.

6, 7 Q, nQ Output Differential output pair. LVPECL interface levels.

CC Power Power supply pin.

9 FSEL0 Input Pullup Output divider control inputs. Sets the output divider value to one of four

values. LVCMOS/LVTTL interface levels.

10 FSEL1 Input Pullup Output divider control inputs. Sets the output divider value to one of four

values. LVCMOS/LVTTL interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance OE, FSEL0, FSEL1 3.5 pF

RPULLUP Input Pullup Resistor 51 k

83PN15639 Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Fu nctional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC

Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C

Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C

Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C

Item Rating

Supply Voltage, VCC 3.63V

Inputs, VI

XTAL_IN

Other Inputs 0V to 2V

-0.5V to VCC + 0.5V

Outputs, IO

Continuous Current

Surge Current 50mA

100mA

Package Thermal Impedance, JA 36.8C/W (0 mps)

Storage Temperature, TSTG -65C to 150C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VCC Power Supply Voltage 3.135 3.3 3.465 V

IEE Power Supply Current 120 140 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VCC Power Supply Voltage 2.375 2.5 2.625 V

IEE Power Supply Current 117 135 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage VCC = 3.465V 2 VCC + 0.3 V

VCC = 2.625V 1.7 VCC + 0.3 V

VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V

VCC = 2.625V -0.3 0.7 V

IIH Input

High Current OE,

FSEL[1:0] VCC = VIN = 3.465V or 2.625V 5 µA

IIL Input

Low Current OE,

FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -150 µA

83PN15639 Datasheet

Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C

NOTE 1: Outputs termination with 50 to VCC – 2V.

Table 5. Crystal Characteristics

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOH Output High Voltage;

NOTE 1 VCC – 1.3 VCC – 0.8 V

VOL Output Low Voltage;

NOTE 1 VCC – 2.0 VCC – 1.6 V

VSWING Peak-to-Peak Output

Voltage Swing 0.5 1.0 V

Parameter Test Conditions Minimum Typical Maximum Units

Mode of Oscillation Fundamental

Frequency 25 MHz

25.000625 MHz

Equivalent Series Resistance (ESR) 50 

Shunt Capacitance 7pF

83PN15639 Datasheet

AC Electrical Characteristics

Table 6. AC Charact eri st ics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: Characterized using a 25MHz, 12pF resonant crystal.

NOTE 1: Please refer to the Phase Noise plots.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 100 156.25390625 MHz

tjit(Ø) RMS Phase Jitter (Random);

NOTE 1

156.25MHz,

Integration Range: 10kHz – 1MHz 0.179 0.220 ps

150MHz,

Integration Range: 12kHz – 20MHz 0.249 0.316 ps

125MHz,

Integration Range: 12kHz – 20MHz 0.241 0.306 ps

100MHz,

Integration Range: 12kHz – 20MHz 0.249 0.316 ps

tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 20 ps

tR / tFOutput Rise/Fall Time 20% to 80% 100 400 ps

odc Output Duty Cycle 48 52 %

83PN15639 Datasheet

Parameter Measurement Information

3.3V LVPECL Output Load AC Test Circuit

RMS Phase Jitter

Output Rise/Fall Time

2.5V LVPECL Output Load AC Test Circuit

Cycle-to-Cycle Jitter

Output Duty Cycle/Pulse Width/Period

SCOPE

LVPECL

VEE

VCC

-1.3V±0.165V

SCOPE

LVPECL

VEE

VCC

-0.5V±0.125V

tcycle n tcycle n+1

tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

83PN15639 Datasheet

Applications Information

Recommendations for Unused Input Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pullup resistor; additional resistance is not required but can be added for additional protection. A 1k resistor can

be used.

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the

Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package,

as shown in Figure 1. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed

pad/slug area on the package to maximize the thermal/electrica l performance. Sufficient clearance should be designed on the PCB betwe en

the outer edges of the land pattern and the inner edges of pa d pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder

joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected

to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon

the package power dissipatio n as well as el ectrical conductivity requirements. Thus, thermal and electrical analysis and/or testi ng are

recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is

incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via

diameter should be

12mils to 13mils (0.30mm to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the exposed pad/slug and the therma l land. Precautions should be taken to

eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline

only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance

Leadframe Base Package, Amkor Technology.

Figure 1. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

SOLDERSOLDER PINPIN EXPOSED HEAT SLUG

PIN PAD PIN PADGROUND PLANE LAND PATTERN

(GROUND PAD)

THERMAL VIA

83PN15639 Datasheet

Overdriving the XTAL Interface

The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor . The

XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less

than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prev ent signal

interference with the power rail and to reduce internal noise. Figure 2A shows an example of the interface diagram for a high speed 3.3V

LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the

transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of

two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This

can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a

slower and weaker LVCMOS driver. Figure 2B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL

termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the

layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specificati ons are

characterized and guaranteed by using a quartz crystal as the input.

Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface

VCC XTAL_OUT

XTAL_IN

100

Z o = 50 ohmsRs

Zo = Ro + Rs

.1uf

LVCMOS Driver

XTAL_OUT

XTAL_IN

Z o = 50 ohm s C2

.1uf

LV P ECL Driver

Z o = 50 ohm s

50 R2

83PN15639 Datasheet

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended

only as guidelines.

The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors

(DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines.

Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two

different layouts which are recommended only as guidelines. Other suitable clo ck layouts may exist and it would be recommended that the

board designers simulate to guara ntee compatibility across all printed circuit and clock component process variations.

Figure 3A. 3.3V LVPECL Output Termination

Figure 3B. 3.3V LVPECL Output Termination

84

3.3V

125

Zo = 50

Zo = 50Input

3.3V

83PN15639 Datasheet

Termination for 2.5V LVPECL Outputs

Figure 4A and Figu re 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC

– 2V. For VCC = 2.5V, the VCC – 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure

4C.

Figure 4A. 2.5V LVPECL Driver Termination Example

Figure 4C. 2.5V LVPECL Driver Termination Example

Figure 4B. 2.5V LVPECL Driver Termination Example

2.5V LVPECL Driver

VCC = 2.5V 2.5V

2.5V

50Ω

250Ω

62.5Ω

–

2.5V LVPECL Driver

VCC = 2.5V 2.5V

50Ω

–

2.5V LVPECL Driver

VCC = 2.5V 2.5V

50Ω

18Ω

–

83PN15639 Datasheet

Schematic Example

Figure 5 shows an example 83PN15639 application schematic in which the device is operated at VCC = +3.3V . The schematic example focuses

on functional connections and is intended as an example only and may not represent the exact user configuration. Refer to the pin description

and functional tables in the datasheet to ensure the logic control inputs are properly set. For example OE and FSEL[1:0] can be config ured from

an FPGA instead of set with pull up and pull down resistors as shown.

As with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to ac hieve optimum jitter performance

isolation of the VCC pin from power supply is required. In order to achieve the best possible filtering, it is recommended that the placement of

the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor on the

VCC pin must be placed on the device side with direct return to the ground plane though vias. The remaining filter components can be on the

opposite side of the PCB.

Power supply filter component recommendations are a general guideline to be used for reducing external noise from coupling into the devices.

The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be

adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests

adding bulk capacita nce in the local area of all devices.

Figure 5. 83PN15639 Application Schematic



3.3V

0.1uF

10uF

VCC

RU2

Not In stall

T o Logic

Input

pins

FB1

BLM18BB221SN1

Place 0.1uF bypass cap directly adjacent to the

VCC pin and on the component side.

RU1

RD2

0.1uF

T o Logic

Input

pins

RD1

Not I n stal l

S e t Log ic

Inp ut t o '1' Set Log ic

Inp ut t o '0'

Logi c Contro l Input E xam pl es

4pF

25MHz (12pf )

RESERVED

VEE

nQ 7

VCC 8

XTAL _OU T

XTAL _I N

FSEL0

FSEL1

FSEL0

FSEL1

For AC terminati on options consult the ID T Applications Note

"Term ination - LVP EC L"

+3 .3 V PE C L Re ce iver

Zo = 5 0 Ohm

83PN15639 Datasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 83PN15639.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 83PN15639 is the sum of the core power plus the power dissipation due to the load.

The following is the power dissipa tion for VCC = 3.3V + 5% = 3.465 V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipation due to th e load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW

• Po w er (o ut pu ts)MAX = 32mW/Loaded Outpu t pair

Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 32mW = 517.1mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = JA * Pd_total + T A

Tj = Junction Temperature

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 36.8°C/W per Tabl e 7 below.

Therefore, Tj for an ambient temp erature of 85°C with all outputs switching is:

85°C + 0.517W * 36.8°C/W = 104°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance JA for 10-Lead VFQFN, Forced Convection

JA by Velocity

Meters per Second 012

Multi-Layer PCB, JEDEC Standard Test Boards 36.8°C/W 31.7°C/W 30.1°C/W

83PN15639 Datasheet

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

The LVPECL output driver circuit and termination are shown in Figure 6.

Figure 6. LVPECL Driver Circuit and Termination

To calcu late power dissipation due to the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V

(VCC_MAX – VOH_MAX) = 0.8V

• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V

(VCC_MAX – VOL_MAX) = 1.6V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =

[(2V – 0.8V)/5 0] * 0.8V = 19.2mW

Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/R L] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =

[(2V – 1.6V)/5 0] * 1.6V = 12.8mW

Total Powe r Dissipation per output pair = Pd_H + Pd_L = 32mW

VOUT

VCC

VCC - 2V

50Ω

83PN15639 Datasheet

Reliability Information

Table 8. JA vs. Air Flow Table for a 10-Lead VFQFN

Transistor Count

The transistor count for 83PN15639 is: 47 ,515

JA vs. Air Flow

Meters per Second 012

Multi-Layer PCB, JEDEC Standard Test Boards 36.8°C/W 31.7°C/W 30.1°C/W

83PN15639 Datasheet

10-Lead VFQFN, NR Suffix Package Outline

ccc C

PLANE

SEATING

5.00x7.00 MLPQ 10LD

1.00/2.54 Pitch

Page 1 Of 4

PACKAGE OUTLINE

MLP QUAD

0.08 C

bbb C A B

INDEX AREA

(D/2 xE/2)

INDEX AREA

aaa C2x

TOP VIEW9

aaa C2x

SIDE VIEW

BOTTOM VIEW

PIN#1 ID

FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.

ENGINEERING MANAGER

DATE

TOOLING MANAGER

TECH. SALES MANAGER

ORIGINATOR DWG. NO : PKGML00305

DRAFT

ZAHRUL

ARAVEN

KANDA

2007-APR-18

3.70

NX b1

NX b2

bbb C A B

NX L1

NX L2

6.25

83PN15639 Datasheet

10-Lead VFQFN, NR Suffix Package Outline, continued

PAGE: 2 of 4

aaa 0.15

bbb 0.10

ccc 0.10

TOLERANCE OF FORM AND POSITION

COMMON DIMENSION

5.00x7.00 MLPQ 10LD

1.00/2.54 Pitch

PACKAGE OUTLINE

MLP QUAD

FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.

ENGINEERING MANAGER

DATE

TOOLING MANAGER

TECH. SALES MANAGER

ORIGINATOR DWG. NO : PKGML00305

DRAFT

ZAHRUL

ARAVEN

KANDA

2007-APR-18

Size

Body

5.00X7.00

Pitch (e1 & e2)

1.00/2.54

Lead Count

Lead Summary Table

Variation

VNJR-1

Very Very Thin

R0.30

Pin #1 ID

NOMMIN MAX

1.00

0.05

1, 2

NOTES

1, 2

0.00

0.80

1, 2

0.02

0.90

COMMON DIMENSION

SYMBOL V : Very thin

83PN15639 Datasheet

10-Lead VFQFN, NR Suffix Package Outline, continued

PAGE: 3 of 4

5.00x7.00 MLPQ 10LD

1.00/2.54 Pitch

PACKAGE OUTLINE

MLP QUAD

NOTE:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

2. All dimensions are in millimeters, angles are in degrees(°).

3. N is the total number of terminals.

4. The location of the terminal #1 identifier and terminal numbering convention

conforms to JEDEC publication 95 SPP-002.

5. ND and NE refer to the number of terminals on each D and E side respectively.

6. NJR refers to NON JEDEC REGISTERED

7. Dimension b applies to metallized terminal and is measured between 0.10mm

and 0.30mm from the terminal tip. If the terminal has the optional radius

on the other end of the terminal, the dimension b should not be measured

in that radius area.

8. Coplanarity applies to the terminals and all other bottom surface metallization.

9. Drawing shown are for illustration only.

FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.

ENGINEERING MANAGER

DATE

TOOLING MANAGER

TECH. SALES MANAGER

ORIGINATOR DWG. NO : PKGML00305

DRAFT

ZAHRUL

ARAVEN

KANDA

2007-APR-18

83PN15639 Datasheet

10-Lead VFQFN, NR Suffix Package Outline, continued

5.00x7.00 MLPQ 10LD

1.00/2.54 Pitch

PACKAGE OUTLINE

MLP QUAD

PAGE: 4 of 4

PAD DESIGN

NOTES

Symbol

Variation

0.65

0.55

0.45

3.80

3.70

3.55

1.80

1.70

1.55

MIN

NOML1 MAX

NOM

MIN

MAX

E BSC

MIN

NOM

MAX

Note

MIN

NOM

MAX

b1 0.45

0.40

0.35

5.00

7.00

D BSC

FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.

ENGINEERING MANAGER

DATE

TOOLING MANAGER

TECH. SALES MANAGER

ORIGINATOR DWG. NO : PKGML00305

DRAFT

ZAHRUL

ARAVEN

KANDA

2007-APR-18

VNJR-1

1.40NOM

MAX 1.45

MIN 1.35

1.10NOML2 MAX 1.20

MIN 1.00

83PN15639 Datasheet

Ordering Information

Table 9. Ordering Information

Part/Order Number Marking Package Shipping Packaging Temperature

83PN15639ANRGI IDT83PN15639ANRGI “Lead-Free” 10-Lead VFQFN Tray -40C to 85C

83PN15639ANRGI8 IDT83PN15639ANRGI “Lead-Free” 10Lead VFQFN Tape & Reel -40C to 85C

83PN15639 Datasheet

Revision History]

Revision Date Description of Change

August 16, 2016 ▪Added package dimensions to package outline.

▪

83PN15639 Datasheet

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications

and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein

is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,

or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

Tech Support

www.idt.com/go/support

Sales

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA