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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3102
SNVS515I –SEPTEMBER 2007–REVISED JANUARY 2018
LM3102 Synchronous 1-MHz, 2.5-A Step-Down Voltage Regulator
1
1 Features
1• Low Component Count and Small Solution Size
• Stable With Ceramic and Other Low-ESR
Capacitors
• No Loop Compensation Required
• High Efficiency at a Light Load by DCM Operation
• Prebias Start-Up
• Ultra-Fast Transient Response
• Programmable Soft-Start
• Programmable Switching Frequency up to 1 MHz
• Valley Current Limit
• Output Overvoltage Protection
• Precision Internal Reference for an Adjustable
Output Voltage Down to 0.8 V
• Thermal Shutdown
• Key Specifications
– Input Voltage Range 4.5 V to 42 V
– 2.5-A Output Current
– 0.8 V, ±1.5% Reference
– Integrated Dual N-Channel Main and
Synchronous MOSFETs
– Thermally Enhanced HTSSOP-20 Package
2 Applications
• 5-VDC, 12-VDC, 24-VDC, 12-VAC, and 24-VAC
Systems
• Embedded Systems and Industrial Control
• Automotive Telematics and Body Electronics
• Point of Load Regulators
• Storage Systems
• Broadband Infrastructure
• Direct Conversion from 2-, 3-, and 4-Cell Lithium
Batteries Systems
3 Description
The LM3102 Synchronously Rectified Buck Converter
features all required functions to implement a highly
efficient and cost-effective buck regulator. The device
can supply 2.5 A to loads with an output voltage as
low as 0.8 V. Dual N-channel synchronous MOSFET
switches allow a low component count, thus reducing
complexity and minimizing board size.
Different from most other COT regulators, the
LM3102 does not rely on output capacitor ESR for
stability, and is designed to work exceptionally well
with ceramic and other very low-ESR output
capacitors. The device requires no loop
compensation, results in a fast load transient
response and simple circuit implementation. The
operating frequency remains nearly constant with line
variations due to the inverse relationship between the
input voltage and the ON-time. The operating
frequency can be externally programmed up to
1 MHz. Protection features include VCC undervoltage
lockout (UVLO), output overvoltage protection,
thermal shutdown, and gate drive UVLO. The
LM3102 is available in the thermally enhanced
HTSSOP-20 package, and LM3102 is also available
in a DSBGA low-profile chip-scale package with
reduced output current.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM3102 DSBGA (28) 3.645 mm × 2.45 mm
LM3102 HTSSOP (20) 6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic Efficiency vs Load Current (VOUT = 3.3 V)
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 11
7.1 Overview................................................................. 11
7.2 Functional Block Diagram....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 14
8 Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application.................................................. 16
8.3 System Examples ................................................... 20
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support................. 23
11.1 Community Resources.......................................... 23
11.2 Trademarks........................................................... 23
11.3 Electrostatic Discharge Caution............................ 23
11.4 Glossary................................................................ 23
12 Mechanical, Packaging, and Orderable
Information........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (June 2015) to Revision I Page
• Changed LM3102 and LM3102-Q1 to Stand Alone data sheets .......................................................................................... 1
Changes from Revision G (January 2012) to Revision H Page
• Updated the LM3102Q part number to LM3102-Q1 ............................................................................................................. 1
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
VIN VIN BST SW AGND RON EN
SW SW SW SW AGND AGND AGND
SW SW SW SW VCC AGND SS
PGND PGND PGND VCC AGND FB
A B C D E F G
4
3
2
1PGND
Top Mark
3
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5 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP
Top View YPA Package
28–Ball DSBGA
Top View
Pin Functions
PIN TYPE DESCRIPTION
NAME PIN NO. BALL NO.
N/C
1
— — No Connection
9
10
12
19
20
SW
2
A2
Power Switching Node
A3
B2
B3
C2
3
C3
D2
D3
D4
VIN 4 A4 Power Input supply voltage
5 B4
BST 6 C4 Power Connection for bootstrap capacitor
AGND 7
E3
Ground Analog Ground
E4
F1
F2
F3
G3
SS 8 G2 Analog Soft-Start
GND 11 — Ground Ground
FB 13 G1 Analog Feedback
EN 14 G4 Analog Enable
RON 15 F4 Analog ON-time Control
VCC 16 E1 Power Start-up regulator Output
E2
4
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Pin Functions (continued)
PIN TYPE DESCRIPTION
NAME PIN NO. BALL NO.
PGND 17 A1
Ground Power Ground
B1
18 C1
D1
EP EP — Ground Exposed Pad
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN, RON to AGND –0.3 43.5 V
SW to AGND –0.3 43.5 V
SW to AGND (Transient) –2 (< 100 ns) V
VIN to SW –0.3 43.5 V
BST to SW –0.3 7 V
All Other Inputs to AGND –0.3 7 V
Junction Temperature, TJ150 °C
Storage Temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Ratings are conditions
under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical
Characteristics.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply Voltage Range (VIN) 4.5 42 V
Junction Temperature Range (TJ)−40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1) LM3102 LM3102
UNITPWP (HTSSOP) YPA (DSBGA)
20 PINS 28 PINS
RθJA Junction-to-ambient thermal resistance 30 50 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 6.5 — °C/W
5
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(1) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
6.5 Electrical Characteristics
Specifications with standard type are for TJ= 25°C unless otherwise specified. Minimum and Maximum limits are specified
through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are
provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 18 V, VOUT = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
START-UP REGULATOR, VCC
VCC VCC output voltage CCC = 680 nF, no load
6
V
over the full Operating
Junction Temperature
(TJ) range 5 7.2
VIN – VCC VIN – VCC dropout voltage
ICC = 2 mA
50
mV
over the full Operating
Junction Temperature
(TJ) range 200
ICC = 20 mA
350
over the full Operating
Junction Temperature
(TJ) range 570
IVCCL VCC current limit(1) VCC = 0 V
65
mA
over the full Operating
Junction Temperature
(TJ) range 40
VCC-UVLO VCC undervoltage lockout
threshold (UVLO) VIN increasing
3.75
V
over the full Operating
Junction Temperature
(TJ) range 3.6 3.9
VCC-UVLO-HYS VCC UVLO hysteresis VIN decreasing – HTSSOP package 130 mV
VCC-UVLO-HYS VCC UVLO hysteresis VIN decreasing – DSBGA package 150 mV
tVCC-UVLO-D VCC UVLO filter delay 3 µs
IIN IIN operating current No switching, VFB = 1
V
0.7
mA
over the full Operating
Junction Temperature
(TJ) range 1
IIN-SD IIN operating current, Device
shutdown VEN = 0 V
25
µA
over the full Operating
Junction Temperature
(TJ) range 40
SWITCHING CHARACTERISTICS
RDS-UP-ON Main MOSFET RDS(on)
0.18
Ω
over the full Operating Junction Temperature (TJ)
range 0.375
RDS- DN-ON Syn. MOSFET RDS(on)
0.11
Ω
over the full Operating Junction Temperature (TJ)
range 0.225
VG-UVLO Gate drive voltage UVLO VBST - VSW increasing
3.3
V
over the full Operating
Junction Temperature
(TJ) range 4
SOFT-START
ISS SS pin source current VSS = 0.5 V
8
µA
over the full Operating
Junction Temperature
(TJ) range 6 10
6
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Electrical Characteristics (continued)
Specifications with standard type are for TJ= 25°C unless otherwise specified. Minimum and Maximum limits are specified
through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are
provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 18 V, VOUT = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT
ICL Syn. MOSFET current limit
threshold LM3102 2.7 A
ICL Syn. MOSFET current limit
threshold LM3102TLX–1 1.5 A
ON/OFF TIMER
ton ON timer pulse width VIN = 10 V, RON = 100 kΩ1.38 µs
VIN = 30 V, RON = 100 kΩ0.47
ton-MIN ON timer minimum pulse
width 150 ns
toff OFF timer pulse width 260 ns
ENABLE INPUT
VEN
EN Pin input threshold
VEN rising
1.18
V
over the full Operating
Junction Temperature
(TJ) range 1.13 1.23
VEN-HYS Enable threshold hysteresis VEN falling 90 mV
REGULATION AND OVERVOLTAGE COMPARATOR
VFB In-regulation feedback voltage
VSS ≥0.8 V
TJ=−40°C to +125°C
0.8
V
over the full Operating
Junction Temperature
(TJ) range 0.784 0.816
VSS ≥0.8 V
TJ= 0°C to +125°C over the full Operating
Junction Temperature
(TJ) range 0.788 0.812
VFB-OV Feedback overvoltage
threshold
0.92 V
over the full Operating Junction Temperature (TJ)
range 0.888 0.945
IFB 5 nA
THERMAL SHUTDOWN
TSD Thermal shutdown
temperature TJrising 165 °C
TSD-HYS Thermal shutdown
temperature hysteresis TJfalling 20 °C
7
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6.6 Typical Characteristics
All curves are taken at VIN = 18 V with the configuration in the typical application circuit for VOUT = 3.3 V shown in this data
sheet. TA= 25°C, unless otherwise specified.
Figure 1. Quiescent Current, IIN vs VIN Figure 2. VCC vs ICC
Figure 3. VCC vs VIN Figure 4. ton vs VIN
Figure 5. Switching Frequency, fSW vs VIN Figure 6. VFB vs Temperature
8
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Typical Characteristics (continued)
All curves are taken at VIN = 18 V with the configuration in the typical application circuit for VOUT = 3.3 V shown in this data
sheet. TA= 25°C, unless otherwise specified.
Figure 7. RDS(on) vs Temperature Figure 8. Efficiency vs Load Current (VOUT = 3.3 V)
Figure 9. VOUT Regulation vs Load Current (VOUT = 3.3 V) Figure 10. Efficiency vs Load Current (VOUT = 0.8 V)
Figure 11. VOUT Regulation vs Load Current (VOUT = 0.8 V) Figure 12. Power Up (VOUT = 3.3 V, 2.5 A Loaded)
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Typical Characteristics (continued)
All curves are taken at VIN = 18 V with the configuration in the typical application circuit for VOUT = 3.3 V shown in this data
sheet. TA= 25°C, unless otherwise specified.
Figure 13. Enable Transient (VOUT = 3.3 V, 2.5 A Loaded) Figure 14. Shutdown Transient (VOUT = 3.3 V, 2.5 A Loaded)
Figure 15. Continuous Mode Operation (VOUT = 3.3 V, 2.5 A
Loaded) Figure 16. Discontinuous Mode Operation (VOUT = 3.3 V,
0.025 A Loaded)
Figure 17. DCM to CCM Transition (VOUT = 3.3 V,
0.15-A - 2.5-A Load) Figure 18. Load Transient (VOUT = 3.3 V, 0.25-A - 2.5-A Load,
Current Slew Rate: 2.5 A/µs)
1.5
1.55
1.6
1.65
1.7
1.75
1.8
0 10 20 30 40 50
INPUT VOLTAGE (V)
VALLEY CURRENT LIMIT (A)
25°C
10
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Typical Characteristics (continued)
All curves are taken at VIN = 18 V with the configuration in the typical application circuit for VOUT = 3.3 V shown in this data
sheet. TA= 25°C, unless otherwise specified.
Figure 19. DSBGA Valley Current Limit VOUT = 5 V at 25°C
11
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7 Detailed Description
7.1 Overview
The LM3102 Step-Down Switching Regulator features all required functions to implement a cost-effective,
efficient buck power converter capable of supplying 2.5 A to a load. It contains Dual N-channel main and
synchronous MOSFETs. The Constant ON-Time (COT) regulation scheme requires no loop compensation,
results in fast load transient response and simple circuit implementation. The regulator can function properly
even with an all ceramic output capacitor network, and does not rely on the ESR of the output capacitor for
stability. The operating frequency remains constant with line variations due to the inverse relationship between
the input voltage and the ON-time. The valley current limit detection circuit, with the limit set internally at 2.7 A,
inhibits the main MOSFET until the inductor current level subsides.
The LM3102 can be applied in numerous applications and can operate efficiently for inputs as high as 42 V.
Protection features include output overvoltage protection, thermal shutdown, VCC UVLO, gate drive UVLO. The
LM3102 is available in the thermally enhanced HTSSOP-20 package.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 COT Control Circuit Overview
COT control is based on a comparator and a one-shot ON-timer, with the output voltage feedback (feeding to the
FB pin) compared with an internal reference of 0.8 V. If the voltage of the FB pin is below the reference, the main
MOSFET is turned on for a fixed ON-time determined by a programming resistor RON and the input voltage VIN,
upon which the ON-time varies inversely. Following the ON-time, the main MOSFET remains off for a minimum
of 260 ns. Then, if the voltage of the FB pin is below the reference, the main MOSFET is turned on again for
another ON-time period. The switching will continue to achieve regulation.
VOUT
1.3 x 10-10 x RON
fSW =
(VIN ± VOUT) x RON2
VOUT (VIN - 1) x L x 1.18 x 1020 x IOUT
fSW =
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Feature Description (continued)
The regulator will operate in the discontinuous conduction mode (DCM) at a light load, and the continuous
conduction mode (CCM) with a heavy load. In the DCM, the current through the inductor starts at zero and
ramps up to a peak during the ON-time, and then ramps back to zero before the end of the OFF-time. It remains
zero and the load current is supplied entirely by the output capacitor. The next ON-time period starts when the
voltage at the FB pin falls below the internal reference. The operating frequency in the DCM is lower and varies
larger with the load current as compared with the CCM. Conversion efficiency is maintained because conduction
loss and switching loss are reduced with the reduction in the load and the switching frequency, respectively. The
operating frequency in the DCM can be calculated approximately as follows:
(1)
In the continuous conduction mode (CCM), the current flows through the inductor in the entire switching cycle,
and never reaches zero during the OFF-time. The operating frequency remains relatively constant with load and
line variations. The CCM operating frequency can be calculated approximately as follows:
(2)
The output voltage is set by two external resistors RFB1 and RFB2. The regulated output voltage is
VOUT = 0.8V x (RFB1 + RFB2)/RFB2 (3)
7.3.2 Start-Up Regulator (VCC)
A startup regulator is integrated within the LM3102. The input pin VIN can be connected directly to a line voltage
up to 42 V. The VCC output regulates at 6 V, and is current limited to 65 mA. Upon power up, the regulator
sources current into an external capacitor CVCC, which is connected to the VCC pin. For stability, CVCC must be at
least 680 nF. When the voltage on the VCC pin is higher than the UVLO threshold of 3.75 V, the main MOSFET
is enabled and the SS pin is released to allow the soft-start capacitor CSS to charge.
The minimum input voltage is determined by the dropout voltage of the regulator and the VCC UVLO falling
threshold (≊3.7 V). If VIN is less than ≊4.0 V, the regulator shuts off and VCC goes to zero.
7.3.3 Regulation Comparator
The feedback voltage at the FB pin is compared to a 0.8-V internal reference. In normal operation (the output
voltage is regulated), an ON-time period is initiated when the voltage at the FB pin falls below 0.8 V. The main
MOSFET stays on for the ON-time, causing the output voltage and consequently the voltage of the FB pin to rise
above 0.8 V. After the ON-time period, the main MOSFET stays off until the voltage of the FB pin falls below 0.8
V again. Bias current at the FB pin is nominally 5 nA.
7.3.4 Zero Coil Current Detect
The current of the synchronous MOSFET is monitored by a zero coil current detection circuit which inhibits the
synchronous MOSFET when its current reaches zero until the next ON-time. This circuit enables the DCM
operation, which improves the efficiency at a light load.
7.3.5 Overvoltage Comparator
The voltage at the FB pin is compared to a 0.92-V internal reference. If the voltage rises above 0.92 V, the ON-
time is immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input
voltage or the output load changes suddenly. Once the OVP is activated, the main MOSFET remains off until the
voltage at the FB pin falls below 0.92 V. The synchronous MOSFET will stay on to discharge the inductor until
the inductor current reduces to zero, and then switch off.
ILR = (VIN - VOUT) x ton
L
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Feature Description (continued)
7.3.6 Current Limit
Current limit detection is carried out during the OFF-time by monitoring the re-circulating current through the
synchronous MOSFET. Referring to the Functional Block Diagram, when the main MOSFET is turned off, the
inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current
exceeds 2.7 A, the current limit comparator toggles, and as a result disabling the start of the next ON-time
period. The next switching cycle starts when the re-circulating current falls back below 2.7 A (and the voltage at
the FB pin is below 0.8V). The inductor current is monitored during the ON-time of the synchronous MOSFET. As
long as the inductor current exceeds 2.7 A, the main MOSFET will remain inhibited to achieve current limit. The
operating frequency is lower during current limit due to a longer OFF-time.
Figure 20 illustrates an inductor current waveform. On average, the output current IOUT is the same as the
inductor current IL, which is the average of the rippled inductor current. In case of current limit (the current limit
portion of Figure 20), the next ON-time will not initiate until that the current drops below 2.7 A (assume the
voltage at the FB pin is lower than 0.8 V). During each ON-time the current ramps up an amount equal to:
(4)
During current limit, the LM3102 operates in a constant current mode with an average output current IOUT(CL)
equal to 2.7 A + ILR / 2.
Figure 20. Inductor Current - Current Limit Operation
7.3.7 N-Channel MOSFET and Driver
The LM3102 integrates an N-channel main MOSFET and an associated floating high voltage main MOSFET
gate driver. The gate drive circuit works in conjunction with an external bootstrap capacitor CBST and an internal
high voltage diode. CBST connecting between the BST and SW pins powers the main MOSFET gate driver during
the main MOSFET ON-time. During each OFF-time, the voltage of the SW pin falls to approximately –1 V, and
CBST charges from VCC through the internal diode. The minimum OFF-time of 260 ns provides enough time for
charging CBST in each cycle.
7.3.8 Soft-Start
The soft-start feature allows the converter to gradually reach a steady-state operating point, thereby reducing
startup stresses and current surges. Upon turnon, after VCC reaches the undervoltage threshold, an 8-µA internal
current source charges up an external capacitor CSS connecting to the SS pin. The ramping voltage at the SS pin
(and the non-inverting input of the regulation comparator as well) ramps up the output voltage VOUT in a
controlled manner.
VIN
1.3 x 10-10 x RON
ton =
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Feature Description (continued)
An internal switch grounds the SS pin if any of the following three cases happens: (i) VCC is below the UVLO
threshold; (ii) a thermal shutdown occurs; or (iii) the EN pin is grounded. Alternatively, the output voltage can be
shut off by connecting the SS pin to ground using an external switch. Releasing the switch allows the SS pin to
ramp up and the output voltage to return to normal. The shutdown configuration is shown in Figure 21.
Figure 21. Alternate Shutdown Implementation
7.3.9 Thermal Protection
The junction temperature of the LM3102 should not exceed the maximum limit. Thermal protection is
implemented by an internal Thermal Shutdown circuit, which activates (typically) at 165°C to make the controller
enter a low power reset state by disabling the main MOSFET, disabling the ON-timer, and grounding the SS pin.
Thermal protection helps prevent catastrophic failures from accidental device overheating. When the junction
temperature falls back below 145°C (typical hysteresis = 20°C), the SS pin is released and normal operation
resumes.
7.3.10 Thermal Derating
The LM3102 can supply 2.5 A below an ambient temperature of 100°C. Under worst-case operation, with either
input voltage up to 42 V, operating frequency up to 1 MHz, or voltage of the RON pin below the absolute
maximum of 7 V, the LM3102 can deliver a minimum of 1.9-A output current without thermal shutdown with a
PCB ground plane copper area of 40 cm2, 2 oz/Cu. Figure 22 shows a thermal derating curve for the minimum
output current without thermal shutdown against ambient temperature up to 125°C. Obtaining 2.5-A output
current is possible by increasing the PCB ground plane area, or reducing the input voltage or operating
frequency.
Figure 22. Thermal Derating Curve
7.4 Device Functional Modes
7.4.1 ON-Time Timer, Shutdown
The ON-time of the LM3102 main MOSFET is determined by the resistor RON and the input voltage VIN. It is
calculated as follows:
(5)
fSW(MAX) = VOUT
VIN(MAX) x 150 ns
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Device Functional Modes (continued)
The inverse relationship of ton and VIN gives a nearly constant frequency as VIN is varied. RON should be selected
such that the ON-time at maximum VIN is greater than 150 ns. The ON-timer has a limiter to ensure a minimum
of 150 ns for ton. This limits the maximum operating frequency, which is governed by Equation 6:
(6)
The LM3102 can be remotely shutdown by pulling the voltage of the EN pin below 1 V. In this shutdown mode,
the SS pin is internally grounded, the ON-timer is disabled, and bias currents are reduced. Releasing the EN pin
allows normal operation to resume because the EN pin is internally pulled up.
Figure 23. Shutdown Implementation
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM3102 is a step-down DC-to-DC controller. It is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 2.5 A. The following design procedure can be used to select
components for the LM3102. Alternately, the WEBENCH software may be used to generate complete designs.
When generating a design, the WEBENCH®software uses iterative design procedure and accesses
comprehensive databases of components. For more details, go to www.ti.com.
8.2 Typical Application
Figure 24. Typical Application Schematic
8.2.1 Design Requirements
For this example the following application parameters exist.
• VIN Range = 8 V to 42 V
• VOUT = 3.3 V
• IOUT = 2.5 A
Refer to Detailed Design Procedure for more information on operational guidelines and limits.
8.2.2 Detailed Design Procedure
8.2.2.1 Design Steps for the LM3102 Application
The LM3102 is fully supported by WEBENCH which offers the following: component selection, electrical
simulation, thermal simulation, as well as the build-it prototype board for a reduction in design time. The following
list of steps can be used to manually design the LM3102 application.
1. Program VOwith divider resistor selection.
2. Program turnon time with soft-start capacitor selection.
3. Select CO.
4. Select CIN.
5. Set operating frequency with RON.
6. Determine thermal dissipation.
7. Lay out PCB for required thermal performance.
L = ILR x fSW x VIN
VOUT x (VIN - VOUT)
1.3 x 10-10
VIN(MAX) x 150 ns
RON t
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Typical Application (continued)
8.2.2.2 External Components
The following guidelines can be used to select external components.
RFB1 and RFB2: These resistors should be chosen from standard values in the range of 1.0 kΩto 10 kΩ,
satisfying the following ratio:
RFB1/RFB2 = (VOUT/0.8 V) – 1 (7)
For VOUT = 0.8 V, the FB pin can be connected to the output directly with a pre-load resistor drawing more than
20 µA. It is because the converter operation needs a minimum inductor current ripple to maintain good regulation
when no load is connected.
RON:Equation 2 can be used to select RON if a desired operating frequency is selected. But the minimum value
of RON is determined by the minimum ON-time. It can be calculated as follows:
(8)
If RON calculated from Equation 2 is smaller than the minimum value determined in Equation 8, a lower frequency
should be selected to recalculate RON by Equation 2. Alternatively, VIN(MAX) can also be limited to keep the
frequency unchanged. The relationship of VIN(MAX) and RON is shown in Figure 25.
On the other hand, the minimum OFF-time of 260 ns can limit the maximum duty ratio. Larger RON should be
selected in any application requiring large duty ratio.
Figure 25. Maximum VIN for Selected RON
L: The main parameter affected by the inductor is the amplitude of inductor current ripple (ILR). Once ILR is
selected, L can be determined by:
where
• VIN is the maximum input voltage
• fSW is determined from Equation 2 (9)
If the output current IOUT is determined, by assuming that IOUT = IL, the higher and lower peak of ILR can be
determined. Beware that the higher peak of ILR should not be larger than the saturation current of the inductor
and current limits of the main and synchronous MOSFETs. Also, the lower peak of ILR must be positive if CCM
operation is required.
Figure 26 and Figure 27 show curves on inductor selection for various VOUT and RON. For small RON, according
to (8), VIN is limited. Some curves are therefore limited as shown in the figures.
tSS = 8 PA
CSS x 0.8V
CIN = 'VIN
IOUT x ton
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Typical Application (continued)
Figure 26. Inductor Selection for VOUT = 3.3 V Figure 27. Inductor Selection for VOUT = 0.8 V
CVCC:The capacitor on the VCC output provides not only noise filtering and stability, but also prevents false
triggering of the VCC UVLO at the main MOSFET on/off transitions. CVCC should be no smaller than 680 nF for
stability, and should be a good quality, low-ESR, ceramic capacitor.
COUT and COUT3:COUT should generally be no smaller than 10 µF. Experimentation is usually necessary to
determine the minimum value for COUT, as the nature of the load may require a larger value. A load which
creates significant transients requires a larger COUT than a fixed load.
COUT3 is a small value ceramic capacitor located close to the LM3102 to further suppress high frequency noise at
VOUT. A 100-nF capacitor is recommended.
CIN and CIN3:The function of CIN is to supply most of the main MOSFET current during the ON-time, and limit
the voltage ripple at the VIN pin, assuming that the voltage source connecting to the VIN pin has finite output
impedance. If the voltage source’s dynamic impedance is high (effectively a current source), CIN supplies the
average input current, but not the ripple current.
At the maximum load current, when the main MOSFET turns on, the current to the VIN pin suddenly increases
from zero to the lower peak of the inductor’s ripple current and ramps up to the higher peak value. It then drops
to zero at turnoff. The average current during the ON-time is the load current. For a worst case calculation, CIN
must be capable of supplying this average load current during the maximum ON-time. CIN is calculated from:
where
• IOUT is the load current
• ton is the maximum ON-time
•ΔVIN is the allowable ripple voltage at VIN (10)
The purpose of CIN3 is to help avoid transients and ringing due to long lead inductance at the VIN pin. A low ESR
0.1-µF ceramic chip capacitor located close to the LM3102 is recommended.
CBST:A 33-nF, high-quality ceramic capacitor with low ESR is recommended for CBST because it supplies a
surge current to charge the main MOSFET gate driver at turnon. Low ESR also helps ensure a complete
recharge during each OFF-time.
CSS:The capacitor at the SS pin determines the soft-start time, that is, the time for the reference voltage at the
regulation comparator and the output voltage to reach their final value. The time is determined from the following
equation:
(11)
CFB:If the output voltage is higher than 1.6 V, CFB is needed in the Discontinuous Conduction Mode to reduce
the output ripple. The recommended value for CFB is 10 nF.
20
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8.3 System Examples
Figure 29. Typical Application Schematic for VOUT = 3.3 V
Figure 30. Typical Application Schematic for VOUT = 0.8 V
+
-
L
COUT
CIN LOADVSUPPLY
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9 Power Supply Recommendations
The LM3102 device is designed to operate from an input voltage supply range between 4.5 V and 42 V. This
input supply should be well regulated and able to withstand maximum input current and maintain a stable
voltage. The resistance of the input supply rail should be low enough that an input current transient does not
cause a high enough drop at the LM3102 supply voltage that can cause a false UVLO fault triggering and system
reset. If the input supply is more than a few inches from the LM3102, additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF
or 100-μF electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
The LM3102 regulation, overvoltage, and current limit comparators are very fast so they will respond to short
duration noise pulses. Layout is therefore critical for optimum performance. It must be as neat and compact as
possible, and all external components must be as close to their associated pins of the LM3102 as possible.
Refer to Layout Example, the loop formed by CIN, the main and synchronous MOSFET internal to the LM3102,
and the PGND pin should be as small as possible. The connection from the PGND pin to CIN should be as short
and direct as possible. Vias should be added to connect the ground of CIN to a ground plane, located as close to
the capacitor as possible. The bootstrap capacitor CBST should be connected as close to the SW and BST pins
as possible, and the connecting traces should be thick. The feedback resistors and capacitor RFB1, RFB2, and CFB
should be close to the FB pin.
A long trace running from VOUT to RFB1 is generally acceptable because this is a low-impedance node. Ground
RFB2 directly to the AGND pin (pin 7). The output capacitor COUT should be connected close to the load and tied
directly to the ground plane. The inductor L should be connected close to the SW pin with as short a trace as
possible to reduce the potential for EMI (electromagnetic interference) generation.
If it is expected that the internal dissipation of the LM3102 will produce excessive junction temperature during
normal operation, making good use of the PCB ground plane can help considerably to dissipate heat. The
exposed pad on the bottom of the LM3102 IC package can be soldered to the ground plane, which should
extend out from beneath the LM3102 to help dissipate heat.
The exposed pad is internally connected to the LM3102 IC substrate. Additionally the use of thick traces, where
possible, can help conduct heat away from the LM3102. Using numerous vias to connect the die attached pad to
the ground plane is a good practice. Judicious positioning of the PCB within the end product, along with the use
of any available air flow (forced or natural convection) can help reduce the junction temperature.
10.2 Layout Example
Figure 31. Minimize Area of Current Loops in Buck Regulators
NC
PGND
NC
SW
VIN
VIN
BST
AGND
SS
VCC
RON
EN
FB
SW NC
PGND
PAD
(21)
120
2
3
4
5
6
813
19
18
17
16
15
14
Thermal Vias under DAP
NC
NC 10
9NC
GND
12
11
CBOOT RON
PGND
L
RFBT
CFF
VOUT sense point
is away from
inductor and
past COUT
VOUT distribution
point is away
from inductor
and past COUT
TO LOAD
Route VOUT sense trace away from
SW and VIN nodes. Preferably
shielded in an alternative layer
GND Plane
Add as much copper area as possible to enhance overall thermal
performance
VIN
CIN
RFBB
Connect RON
to VIN
COUT
VOUT
GND
SW
CVCC
CSS
7Refer Data sheet
for EN options
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Layout Example (continued)
Figure 32. PCB Layout Example - Top View
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM3102MH/NOPB ACTIVE HTSSOP PWP 20 73 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM3102
MH
LM3102MHX/NOPB ACTIVE HTSSOP PWP 20 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM3102
MH
LM3102TL-1/NOPB ACTIVE DSBGA YPA 28 250 RoHS & Green SNAGCU Level-1-260C-UNLIM 3102
LM3102TLX-1/NOPB ACTIVE DSBGA YPA 28 1000 RoHS & Green SNAGCU Level-1-260C-UNLIM 3102
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM3102 :
•Automotive: LM3102-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM3102MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LM3102TL-1/NOPB DSBGA YPA 28 250 178.0 12.4 2.64 3.84 0.76 8.0 12.0 Q1
LM3102TLX-1/NOPB DSBGA YPA 28 1000 178.0 12.4 2.64 3.84 0.76 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-May-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM3102MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0
LM3102TL-1/NOPB DSBGA YPA 28 250 210.0 185.0 35.0
LM3102TLX-1/NOPB DSBGA YPA 28 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-May-2019
Pack Materials-Page 2
MECHANICAL DATA
PWP0020A
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MXA20A (Rev C)
MECHANICAL DATA
YPA0028
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TLC28XXX (Rev A)
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
4215064/A 12/12
NOTES:
0.600
±0.075
E
D
D: Max =
E: Max =
3.676 mm, Min =
2.48 mm, Min =
3.615 mm
2.419 mm
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