Features Fast Read Access Time - 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms maximum 1 to 64 Byte Page Write Operation Low Power Dissipation 50 mA Active Current 200 pA CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 10 or 10 Cycles Data Retention: 10 years Single 5 V+ 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout Full Military, Commercial, and Industrial Temperature Ranges Description The AT28C256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 200 WA. (continued) Pin Configurations . TSOP Pin Name Function A Top View AO -A14 Addresses ~ = OF 1 28, B AIO CE Chip Enable an gd 2, op B var Cf Ag 4 25 B Woes OE Output Enable we *%d 6 24 BO om ; vec S) 7 22~ B vos WE Write Enable AM wid 2 9 20 7 B vo2 GND 10 vO OO - 1/07 Data Inputs/Outputs ne AG F yo"! 1B . B Oo a NC No Connect ag M1488 Bis BAT ag CERDIP, PDIP, PGA FLATPACK, SOIC Lec, PLCC Top View Top View Top View 4 3 1 27 | 26 A? A14VCC_At3 Ae | A7 | Ata | WE | A13 Al2 NG WE 5 2 28) 24 | 25 AS | A12| VCC} AS | AB 7/16 22 | 23 A3 | A4 GE | Ait 9 | 38: 20 | 21 At | a2 CE | A10 nu | 10; 14] 16 | 19 VOO | AO | GND] VO4 | VO7 12 | 13 | 16] 17 | 18 VO1 | VO2 | VO3] V/O5 | YO VO's 12 NC345 GND Note: PLCC package pins 1 and 17 are DONT CONNECT. AIMEL AT28C256 Paged CMOS EPROM 256K (32K x 8) 2-169Alt Description (Continued) The AT28C256 is accessed like a Static RAM for the read or write cycle without the need for external components. The de- vice contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be de- tected by DATA polling of 1/07. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmels 28C256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correc- tion for extended endurance and improved data retention char- acteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EPROM for device identification or tracking. Block Diagram vec DATA INPUTS/OUTPUTS GND > 00 - /O7 _, _ tetteete o-[ _ dt WE OE, CE AND WE DATA LATCH LOGIC _,[_ INPUT/OUTPUT cE * BUFFERS =] Y DECODER >| Y-GATING ADDRESS | ~~} . INPUTS CELL MATRIX X DECODER IDENTIFICATION Absolute Maximum Ratings* Temperature Under Bias................. -55C to +125C Storage Temperature... cee -65C to +150C All Input Voltages {including N.C. Pins) with Respect to Ground ................. -0.6 V to +6.25 V All Output Voltages with Respect to Ground ............ -0.6 V to Voc +0.6 V Voltage on OE and AQ with Respect to Ground ................ -0.6 V to +13.5V 2-170 *NOTICE: Stresses beyond those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the de- vice at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT28C256 squeuees AT 28 C256 Device Operation READ: The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the mem- ory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of twc, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28C256 al- lows one to sixty-four bytes of data to be written into the device during a single internal programming period. A page write op- eration is initiated in the same manner as a byte write; the first byte written can then be followed by one to sixty-three addi- tional bytes. Each successive byte must be written within 150 ps (tpLc) of the previous byte. If the tp_c limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6- A14 inputs. For each WE high to Jow transition during the page write operation, A6 - Al4 must be the same. The AO to AS inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all out- puts, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28C256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in /O6 toggling between one and zero. Once the write has completed, 1/06 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power Pin Capacitance (f= 1 MHz, T = 25C) supply. Atmel has incorporated both hardware and software fea- tures that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C256 in the following ways: (a) Vcc sense - if Vcc is below 3.8 V (typical) the write function is inhibited; (b) Vcc power-on delay - once Vcc has reached 3.8 V the device will automatically time out 5 ms (typ- ical) before allowing a write: (c) write inhibit - holding any one of OF tow, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be en- abled or disabled by the user; the AT28C256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three spe- cific addresses (refer to Software Data Protection Algorithm). After writing the three byte command sequence and after twc the entire AT28C256 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C256. This is done by preceding the data to be written by the same three byte com- mand sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C256 during power-up and power- down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and dis- able command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write tim- ers. No data will be written to the device; however, for the dura- tion of twc, read operations will effectively be polling opera- tions. DEVICE IDENTIFICATION: An extra 64 bytes of EPROM memory are available to the user for device identification. By raising A9 to 12 V 0.5 V and using address locations 7FCOH to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a six byte software code. Please see Software Chip Erase application note for details. Typ Max Units Conditions CIN 4 6 pF Vin=O0V Cout 8 12 pF Vout =0V Note: 1. This parameter is characterized and is not 100% tested. AIMEL 2-171ATMEL D.C. and A.C. Operating Range AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35 Com. 0C - 70C 0C - 70C 0C - 70C Fomperure (Casey Ind. -40C - 85C -A0C - 85C -40C - 85C Mil. -55C - 125C -55C - 125C -55C - 125C -55C - 125C Voc Power Supply 5V+10% 5V+10% 5 V+ 10% 5V+10% Operating Modes Mode CE OE WE vo Read VIL VIL VIH Dout Write!) VIL VIH VIL DIN StandbyMrite Inhibit Vin x) x High Z Write Inhibit x xX VIH Write Inhibit Xx VIL Xx Output Disable Xx Vin X High Z Chip Erase VIL Vo O VIL High Z Notes: 1. X can be Vir or Vm. 2. Refer to A.C. Programming Waveforms. D.C. Characteristics 3. Vo = 12.0V 40.5 V. | Symbol Parameter Condition Min Max Units I Input Load Current ViIN=OVtoVec+1V 10 HA ILo Output Leakage Current Vio = 0 V to Vcc 10 pA IsB1 Voc Standby Current CMOS GE=Veo-0.3V to Voc + 1 2m Ind: 200 __wA Mil. 300 HA Isp2 Voc Standby Current TTL CE =2.0VtoVec+1V 3 mA loc Vcc Active Current f = 5 MHz; lour = 0 mA 50 mA ViL Input Low Voltage 0.8 Vv VIH Input High Voltage 2.0 Vv | VoL Output Low Voltage loL = 2.1 mA 45 Vv VOH Output High Voltage OH = -400 HA 2.4 Vv 2-172 AT28C256 numeenees A128 C256 A.C. Read Characteristics AT28C256-15 | AT28C256-20 | AT28C256-25 | AT28C256-35 Symbol | Parameter Min Max Min Max Min Max Min Max Units tacc Address to Output Delay 150 200 250 350 ns Ea tce | CE to Output Delay 150 200 250 350 ns toe | OE to Output Delay 0 70 80 0 100 0 100 ns tor @4) | CE or OE to Output Float 0 50 55 0 60 0 70 ns Output Hold from OE, CE toH or Address, whichever 0 0 0 0 ns occurred first A.C. Read Waveforms"??? ADDRESS >< ADDRESS VALID CE tCcE ~+ __| t0E -! OE tDF 4ACC 10H OUTPUT HIGH Z OUTPUT VALID Notes: 1. CE may be delayed up to tacc - tcg after the address transition without impact on tacc. 2. OE may be delayed up to tce - tog after the falling edge of CE without impact on tcg or by tacc - tog after an address change without impact on tacc. Input Test Waveforms and Measurement Level 3.0V AC AC DRIVING 1.5V MEASUREMENT LEVELS LEVEL 0.0V tr, tF< S5ns 3. tor is specified from OE or CE whichever occurs first (CL= 5 pF). 4. This parameter is characterized and is not 100% tested. Output Test Load 5.0V OUTPUT PIN 1.3K Tt 100pF ANNE 2172A A.C. Write Characteristics Symbol Parameter Min Max Units tas, toes Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tes Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns twe Write Pulse Width (WE or CE) 400 ns tos Data Set-up Time 50 ns {DH,tOEH Data, OE Hold Time 0 ns tov Time to Data Valid NRO Note: 1. NR=No Restiction A.C. Write Waveforms- WE Controlled OE 4 NS tOES 1OEH ADDRESS x tAS | |.tAH CE | tCH tes _ WE XY ON tWPH }->-___- tWP I- tDV tDS4 |-_tDH DATA IN pt A.C. Write Waveforms- CE Controlled OE - \ tOES iOEH ADDRESS tAS | |+tAH WE -p tCH __ tCs] CE NX |. tWPH |~_____twp_____- |- tDV. tDS }-_tDH DATA IN oo 2-174 AT28C256es AT 2S C256 Page Mode Characteristics Symbol Parameter Min Max Units tweo Write Cycle Time AT26C256 10 ms AT28C256F 3.0 ms tas Address Set-up Time 0 ns tAH Address Hold Time 50 ns tos Data Set-up Time 50 ns tbH Data Hold Time 0 ns twp Write Pulse Width 100 ns tBLc Byte Load Cycle Time 150 ps twPH Write Pulse Width High 50 ns Page Mode Write Waveforms 7 b OE __ CE tWPH _ tBLC WE {DH AO-AS Ds --_ DATA Xvaun vats, x / a7 < a BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 62 BYTE 63 { |.1wC Notes: 1. A6 through Al4 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. Chip Erase Waveforms Vi CE VH OE Vi VIH ts = ty = 5 psec (min.) tw = 10 msec (min.) viL Vu=12.0V+05V AIMEL 27sSoftware Data w Protection Enable Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 ADDRESS 2AAA LOAD DATA AO TO ADDRESS 5555 LOAD DATA XX TO 4) ANY ADDRESS LOAD LAST BYTE TO LAST ADDRESS WRITES ENABLED ENTER DATA PROTECT STATE Notes for software program code: 1. Data Format: 1/07 - I/O0 (Hex); Address Format: Ai4 - AO (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. AIMET 2) Software Data w Protection Disable Algorithm Software Protected Write Cycle Waveforms LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE LOAD DATA XX TO (4) ANY ADDRESS LOAD LAST BYTE TO LAST ADDRESS L OE (~ ce (NUS NS NS NIN SNS _ tWPH tBLC iL WE tDH (A~ A0-A5 BYTE ADDRESS xX fa 5555 YL AG-A14 x PAGE ADDRESS L tDS - - DATA x AA 55 AO x x x L BYTE 0 BYTE 62 BYTE 63 e two- Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the 2-176 software code has been entered. 2. GE must be high only when WE and CE are both low. AT28C256 | GB)ees AT OSC 256 Data Polling Characteristics Symbol Parameter Min Typ Max Units tbH Data Hoid Time 0 ns tOEH OE Hold Time 0 ns toe OE to Output Delay) ns twr Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See A.C. Read Characteristics. Data Polling Waveforms Toggle Bit Characteristics Symbol Parameter Min Typ Max Units toH Data Hold Time 10 ns toEH OE Hold Time 10 ns toe OE to Output Delay) ns toEHP OE High Pulse 150 ns twr Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See A.C. Read Characteristics. Toggle Bit Waveforms") WE Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of 1/06 will vary. 3. Any address location may be used but the address should not vary. ANTIEL 2ar7AIMEL NORMALIZED SUPPLY CURRENT vs. NORMALIZED SUPPLY CURRENT vs. 1s TEMPERATURE va SUPPLY VOLTAGE x} nt " 1.2 fy : aw a hoa ww bo a a d _ de > , 09 < ; c SC os c 0.6 -55 +25 5 35 65 95 125 4.50 4.76 5.00 5.25 5.50 Temperature (C} Supply Voltage (V) NORMALIZED SUPPLY CURRENT vs. ADDRESS FREQUENCY N oO ' 1.0 m a Ln ! ag eal 1 Zz g 08 d Vec = 5V T = 25C | 0.7 Cc os 0 1 2 3 4 5 Frequency (MHz) 2-178 AT28C256 ummmees ATSC 256 Ordering Information tacc lec (mA) . : (ns) Active | Standby Ordering Code Package Operation Range 150 50 0.2 AT28C256(E,F)-15DC 28D6 Commercial AT28C256(E,F)-15JC 32J (0C to 70C) AT28C256(E,F)-15PC 28P6 AT28C256(E,F)-15SC 28S AT28C256(E,F)-15TC 28T AT28C256(E,F)-15UC 28U AT28C256(E,F)-15DI 28D6 Industrial AT28C256(E,F)-15ul 32J (-40C to 85C) AT28C256(E,F)-15P4 28P6 AT28C256(E,F)-15SI 28S AT28C256(E,F)-15T 28T AT28C256(E,F)-15Ul 28U 150 50 0.3 AT28C256(E,F)-15DM/883 28D6 Military/883C AT28C256(E,F)-15FM/883 28F Class B, Fully Compliant AT28C256(E,F)-15LM/883 32L (-55C to 125C) AT28C256(E,F)-15UM/883 28U 200 50 0.2 AT28C256(E,F)-20DC 28D6 Commercial AT28C256(E,F)-20JC 32J (0C to 70C) AT28C256(E,F)-20PC 28P6 AT28C256(E,F)-20SC 28S AT28C256(E,F)-20TC 28T AT28C256(E,F)-20UC 28U AT28C256(E,F)-20D! 28D6 Industrial AT28C256(E,F)-20J1 32J (-40C to 85C) AT28C256(E,F)-20PI 28P6 AT28C256(E,F)-20SI 28S AT28C256(E,F)-20T| 28T AT28C256(E,F)-20UI 28U 200 50 0.3 AT28C256(E,F)-20DM/883 28D6 Military/883C AT28C256(E,F)-20FM/883 28F Class B, Fully Compliant AT28C256(E,F)-20LM/883 32L (-55C to 125C) AT28C256(E,F)-20UM/883 28U 250 50 0.2 AT28C256(E,F)-25DC 28D6 Commercial AT28C256(E,F)-25JC 32J (0C to 70C) AT28C256(E,F)-25PC 28P6 AT28C256(E,F)-25UC 28U AT28C256-W DIE AT28C256(E,F)-25DI 28D6 Industrial AT28C256(E,F)-25u1 32J (-40C to 85C) AT28C256(E,F)-25P1 28P6 AT28C256(E,F)-25Ul 28U 250 50 0.3 AT28C256(E,F)-25DM/883 28D6 Military/883C AT28C256(E,F)-25FM/883 28F Class B, Fully Compliant AT28C256(E,F)-25LM/883 32L (-55C to 125C) AT28C256(E,F)-25UM/883 28U 300) 50 0.3 AT28C256(E,F)-30DM/883 28D6 Military/883C AT28C256(E,F)-30FM/883 28F Class B, Fully Compliant AT28C256(E,F)-30LM/883 32L (-55C to 125C) AT28C256(E,F)-30UM/883 28U ATMEL 2-179AImMEt Ordering Information ie A tee (mA) Ordering Code Package Operation Range ctive Standby 350 50 0.3 AT28C256(E,F)-35DM/883 28D6 Military/883C AT28C256(E,F)-35FM/883 28F Class B, Fully Compliant AT28C256(E,F)-35LM/883 32L (-55C to 125C) AT28C256(E,F)-35UM/883 28U 150) 50 0.35 5962-88525 16 UX 28U Military/883C 5962-88525 16 XX 28D6 Class B, Fully Compliant 5962-88525 16 YX 32L (-55C to 125C) 5962-88525 16 ZX 28F 5962-88525 15 UX 28U Military/883C 5962-88525 15 XX 28D6 Class B, Fully Compliant 5962-88525 15 YX 32L (-55C to 125C) 5962-88525 15 ZX 28F 5962-88525 14 UX 28U Military/883C 5962-88525 14 XX 28D6 Class B, Fully Compliant 5962-88525 14 YX 32L (-55C to 125C) 5962-88525 14 ZX 28F 150 50 0.35 5962-88525 08 UX 28U Military/883C 5962-88525 08 XX 28D6 Class B, Fully Compliant 5962-88525 08 YX 32L (-55C to 125C) 5962-88525 08 ZX | 28F 5962-88525 07 UX 28U Military/883C 5962-88525 07 XX 28D6 Class B, Fully Compliant 5962-88525 07 YX 32L (-55C to 125C) 5962-88525 07 ZX 28F 5962-88525 06 UX 28U Military/883C 5962-88525 06 XX 28D6 Class B, Fully Compliant 5962-88525 06 YX 32L (-55C to 125C) 5962-88525 06 ZX 28F 2008) 50 0.35 5962-88525 12 UX 28U Military/883C 5962-88525 12 XX 28D6 Class B, Fully Compliant 5962-88525 12 YX 32L (-55C to 125C) 5962-88525 12 ZX 28F 200 50 0.35 5962-88525 04 UX 28U Military/883C 5962-88525 04 XX 28D6 Class B, Fully Compliant 5962-88525 04 YX 32L (-55C to 125C) 5962-88525 04 ZX 28F 250) 50 0.35 5962-88525 13 UX 28uU Military/883C 5962-88525 13 XX 28D6 Class B, Fully Compliant 5962-88525 13 YX 32L (-55C to 125C) 5962-88525 13 ZX 28F 5962-88525 11 UX 28U Military/883C 5962-88525 11 XX 28D6 Class B, Fully Compliant 5962-88525 11 YX 32L (-55C to 125C) 5962-88525 11 ZX 28F 2-180 AT28C256 cuumeees AT 28 C256 Ordering Information tacc Icc (mA) . Ordering Code Package Operation Range (ns) Active | Standby g g P 9 2 | 250 50 0.35 5962-88525 05 UX 28U Military/883C 5962-88525 05 XX 28D6 Class B, Fully Compliant 5962-88525 05 YX 32L (-55C to 125C) 5962-88525 05 ZX 28F 5962-88525 03 UX 28U Military/883C 5962-88525 03 XX 28D6 Class B, Fully Compliant 5962-88525 03 YX 32L (-55C to 125C) 5962-88525 03 ZX 28F 300) 50 0.35 5962-88525 10 UX 28U Military/883C 5962-88525 10 XX 28D6 Class B, Fully Compliant 5962-88525 10 YX 32L (-55C to 125C) 5962-88525 10 ZX 28F 300") 50 0.35 5962-88525 02 UX 28U Military/883C 5962-88525 02 XX 28D6 Class B, Fully Compliant 5962-88525 02 YX 32L {-55C to 125C) 5962-88525 02 ZX 28F 350) 50 0.35 5962-88525 09 UX 28U Military/883C 5962-88525 09 XX 28D6 Class B, Fully Compliant 5962-88525 09 YX 32L (-55C to 125C) 5962-88525 09 ZX 28F 350 50 0.35 5962-88525 01 UX 28U Military/883C 5962-88525 01 XX 28D6 Class B, Fully Compliant 5962-88525 01 YX 32L (-55C to 125C) 5962-88525 01 ZX 28F Note: 1. Electrical specifications for these speeds are defined by Standard Microcircuit Drawing 5962-88525. 2. See Walid Part Number table below. 3. SMD specifies Software Data Protection feature for device type. although Atmel product supplied to every device type in the SMD is 100% tested for this feature. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28C256 15 DC, DI, JC, JI, PC, Pl, SC, SI, TC, TI, UC, Ui, DM/883, FM/883, LM/883, UM/883 AT28C256E 15 DC, DI, JC, Jl, PC, PI, SC, SI, TC, TI, UC, Ul, DM/883, FM/883, LM/883, UM/883 AT28C256F 15 DC, DI, JC, Jl, PC, Pl, SC, SI, TC, TI, UC, UI, DM/883, FM/883, LM/883, UM/883 AT28C256 20 DC, DI, JC, JI, PC, Pl, SC, SI, TC, TI, UC, UI, DM/883, FM/883, LM/883, UM/883 AT28C256E 20 DC, DI, JC, JI, PC, Pi, SC, SI, TC, Ti, UC, UI, DM/883, FM/883, LM/883, UM/883 AT28C256F 20 DC, Dt, JC, JI, PC, Pl, SC, SI, TC, TI, UC, UI, DM/883, FM/883, LM/883, UM/883 AT28C256 25 DC, DI, JC, JI, PC, Pl, SC, SI, TC, Tl, UC, Ul, DM/883, FM/883, LM/883, UM/883 AT28C256E 25 DC, DI, JC, JI, PC, Pl, SC, SI, TC, TI, UC, UI, DM/883, FM/883, LM/883, UM/883 AT28C256F 25 DC, DI, JC, JI, PC, Pl, SC, SI, TC, Ti, UC, UI, DM/883, FM/883, LM/883, UM/883 ANEL 20AIMEL Ordering Information Package Type 28D6 28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip) 28F 28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 325 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28 Lead, Plastic Thin Small Outline Package (TSOP) 28U | 28 Pin, Ceramic Pin Grid Array (PGA) Ww Die Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 2-182 AT28C256 mumeeee