CY7C1347
Document #: 38-05086 Rev. ** Page 4 of 16
Introduction
Functional Overview
All syn chrono us in puts p ass through input regist ers co ntrolle d
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (tCO) is 3.5 ns
(166-MHz device).
The CY7C1347 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst o rder supp orts Pentium an d i 48 6 p roc es so rs. The linear
burst sequence is suited for processors that utilize a linear
burst s equ enc e. The bu rst order is user se lec tab le, and is d e-
termined by sampling the MODE input. Accesses can be initi-
ated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captu res the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byt e Write S elect (BW[3:0]) inputs. A Global Write
Enable (G W) overri des all byte write inp uts and wri tes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self- t imed w rite ci rcu itry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynch ro nous Ou tp ut En able ( O E) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asse rted active, and (3) the writ e signals
(GW, B W E) are all deasserted HIGH. ADSP is ignor e d if CE1
is HIGH . The address presented to the address inputs (A[16:0])
is stored into the addre ss advancem ent logic and the Addres s
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the ris ing edge of th e nex t clo ck t he da ta
is allowed to propagate through the OutputRegister and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW . The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the f irs t cy cl e of t h e a cc ess, t h e ou t pu ts a r e co nt ro ll e d by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is in itiat ed whe n both of t he foll owing condi tions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asser ted active. The ad dress presente d
to A[16:0] is loaded into the Address Register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW[3:0]) and ADV inputs are ig-
nored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data pres ented to the DQ[31:0] and DP[3:0] i nputs is written into
the corres pon di ng address loc ati on i n the RAM co re. If G W is
HIGH, then the write operation is controlled by BWE and
BW[3:0] signals. Th e CY7 C134 7 prov id es by te w rite cap abi lity
that is described in the Write Cycle Description table. Assert-
ing the Byte Write Enable input (BWE) with the selected Byte
Write ( BW[3:0]) input will selectively write to only the desired
bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] and DP[3:0] inputs. Doin g so wil l three-s tate th e
output driv ers. As a safety preca ution, DQ[31:0] and DP[3:0] are
automat icall y t hree-sta ted whenev er a w rite c ycle is d etecte d,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW[3:0]) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A[16:0] is loaded into th e add res s re gis ter a nd th e ad dres s a d-
vancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ[31:0] and DP[3:0] is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] and DP[3:0] inputs. Doin g so wil l three-s tate th e
output driv ers. As a safety preca ution, DQ[31:0] and DP[3:0] are
automat icall y t hree-sta ted whenev er a w rite c ycle is d etecte d,
regardless of the state of OE.
31 MODE Input-
Static Selects burst order. When tied to GND selects linear burst sequence. When tied
to VDDQ or left fl oating sele cts i nterlea ved b urst s equen ce. Th is is a str ap pin an d
should remain static during device operation.
14, 16, 38, 39,
42, 43, 66 NC No Connects.
Pin Definitions
Pin Number Name I/O Description