74HC/HCT273 MSI OCTAL D-TYPE FLIP-FLOP WITH RESET; POSITIVE-EDGE TRIGGER FEATURES TYPICAL ideal buffer for MOS microprocessor SYMBOL | PARAMETER CONDITIONS UNIT or memory HC HCT Common clock and master reset i iti tri \a ropagation delay Eight positive edge-triggered D-type tpHL/ POP te a, - 15 15 ng flip-flops tPLH NMA to Cy_ = 15 pF 15 20 ns See 377" for clock enable version n Vec=5 See 373" for transparent latch fmax maximum clock frequency 66 | 36 | MHz version See 374 for 3-state version Cy input capacitance 3.5 3.5 pF @ Output capability; standard dissipati . power dissipation Icc category: MSI Cpp capacitance per flip-flop notes 1 and 2 20 23 pF GENERAL DESCRIPTION The 74HC/HCT273 are high-speed Si-gate CMOS devices and are pin Notes compatible with low power Schottky 1 TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT273 have eight edge- triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset 2. (MR) inputs toad and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Q,,) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs GND =0 V: Tamb = 25 Ci ty = te = 6 ns . CPpp is used to determine the dynamic power dissipation (Pp in pW): Pp =Cppx Vcc? x f+ 5 (CL x Vcc? x fo} where: fj = input frequency in MHz CL = output load capacitance in pF fo = output frequency in MHz Vcc = supply voltage in V = (Cy x Voc? x fg) = sum of outputs For HC the condition is V| = GND to Vcc For HCT the condition is V} = GND to Vcc 1.6 V PACKAGE OUTLINES 20-lead DIL; plastic (SOT146), 20-iead mini-pack; plastic (SO20; SOT163A). PIN DESCRIPTION by a LOW voltage level on the PIN NO. SYMBOL NAME AND FUNCTION MR input. _ ; t lective LOW! The device is usefui for applications ' MR master reset Input active where the true output only is required 2, 5, 6, 9, 12, Qo to Q7 flip-flop outputs and the clock and master reset are 15, 16, 19 common to all storage elements. 3, 4,7, 8, 13, inout 14, 17.18 Dg to D7 data inputs 10 GND ground (0 V) 11 cP clock input {LOW-to-HIGH, edge-triggered) 20 Vec positive supply voltage mn (| u 20] Yee oof Fao, s o9{3| [18] 7 310y f-2 o1[4] 7] 6 44D; Qh 5 74D, ag b 6 a GB 273 16] Os sjo, 3/9 2 [6 | 15} 95 13 | 04 Og 12 D va] 0 1405 Qs -~ 15 4 fs) 17-4 Dg Og 16 ea [e | 13] wo, o;--19 a3 [9] inn Ma Gnb [10 fii] cp % 7293287 7293258 FZ93256 Fig. 1 Pin configuration. Fig. 2 Logic symbol. Fig. 3 IEC logic symbol. September 1993 551 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. 74HC/HCT273 MSI Fig. 4 Functional diagram, 7293259 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES MA cP D QO H = HIGH voltage level n n h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition x L reset (clear) L x L = LOW voltage level Darque ! = LOW voltage level one set-up time prior to the load 1 H th 4 LOW-to-HIGH CP transition une T = LOW-to-HIGH transition load O H t | L X = dont care Do Dy a9 D3 Dy Os Dg Dy D ak dD ah o ak op ak doa Da D oh, boo ce cp ce cP ce ce cp ce FFI FF2 FF3 FF4 FFS FF6 FF? FF8 Rp [ Rp 1 Rp [ Rp [ Rp [ Rp [ Ro i Rp cP : > + + g . MR >o 0 "1 2 3 6 7293260 2 Fig. 5 Logic diagram. 52 September 1993 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. Octal D-type flip-flop with reset; positive-edge trigger 74HC/HCT273 MS! DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard lec category: MS! AC CHARACTERISTICS FOR 74HC GND =O V;t, =tg=6ns;C_ = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Vcc | WAVEFORMS +25 40 to +85 | 40 to +125 Vv min. | typ. | max.| min. | max. | min, | max. : 41 150 185 225 2.0 fPHLY | Propageyon delay 1s | 30 37 45 |ns | 45 | Fig.6 PLH n 13 | 26 31 38 6.0 . 44 | 150 185 225 2.0 tPHL RO, delay 16 | 30 37 45 | ns 4.5 | Fig.7 n 14 | 26 31 38 6.0 t / 19 | 75 95 110 2.0 yt L output transition time 7 | 15 19 22. | ns 4.5 | Fig.6 TLH 6 | 13 15 19 6.0 . 80 114 100 120 2.0 clock pulse width ; tw 16 {5 20 24 ns 4.5 Fig. 6 HIGH or LOW 14/4 17 20 6.0 . 60 |17 75 90 2.0 tw me pulse width =) 42 |6 15 18 ns 45 | Fig.7 10 |5 13 15 6.0 . 50 |-6 65 75 2.0 removal time . trem 10 |-2 13 15 ns 4.5 | Fig.7 MR to CP 9 |-2 " 13 6.0 . 60 | 11 75 90 2.0 teu OCP 12 |4 15 18 ns 45 | Fig.8 An 10 |3 13 15 6.0 . 3 6 3 3 2.0 th hola es 3 2 3 3 ns 4.5 Fig. 8 nto 3 |-2 3 3 6.0 : lock put 6.0 | 20.6 4.8 4.0 2.0 fmax maximum clock purse 30 | 103 24 20 MHz | 4.5 | Fig.6 frequency 35 | 122 28 24 6.0 September 1993 553. Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. 74HC/HCT273 MSI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics", section "Family specifications. Output capability: standard lec category: MSI Note to HCT types The value of additional quiescent supply current (Alec) for a unit load of 1 is given in the family specifications. To determine Alcc per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD INPUT | COEFFICIENT MR 1.00 cP 1.75 Dn 0.15 AC CHARACTERISTICS FOR 74HCT GND = 0 V;t, = ty = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT | Veco; WAVEFORMS +25 40 to +85 | 40 to +125 Vv min. | typ. | max.| min. | max.| min. } max. tpHL/ propagation delay 0 45 4. Fig. 6 tPLH CP to O, 16 3 38 ns 5 ig propagation delay : t Ss 23 | 34 43 51 ns 4.5 Fig. 7 PHL MR to OQ, TTHL/ output transition time 7 15 19 22 ns 4.5 Fig. 6 'TLH tw neat 16 |9 20 24 ns 4.5 | Fig 6 tw mee et pulsewidth | ag | g 20 24 ns 4.5 | Fig.7 trem Thao. 10 | -2 13 15 ns | 45 | Fig. 7 tsy sue ie 12 45 15 18 ns 4.5 | Fig.8 n th hee 3 |-4 3 3 ns | 45 | Fig.8 n maximum clock pulse MH 45 Fig. 6 fmax frequency 30 | 56 24 20 z | 4. 9 554 September 1993 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. Octal D-type flip-flop with reset; positive-edge trigger 74HC/HCT273 MSI AC WAVEFORMS CP INPUT OQ, OUTPUT 7ZB7479.1 cel lee TTHE wl le tTLH Fig. 6 Waveforms showing the clock (CP) to output (Q,,) propagation delays, the clock pulse width output transition times and the maximum clock pulse frequency. MR INPUT \ CP INPUT vu Q,, OUTPUT T2R7478 Fig. 7 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q),)} propagation deiays and the master reset to clock {CP) removal time. CP INPUT Q,, OUTPUT Vag 7293142 Fig. 8 Waveforms showing the data set-up and hold times for the data input (Dy). Note to Fig. 8 The shaded areas indicate when the input is permitted to change for predictable output performance, Note to AC waveforms (1} HC: Vpy = 50%; Vy = GND to Voc. HCT: Vx = 1.3V; Vy] = GND to 3 V. Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. September 1993 555