IC61C1024-15TIG - Integrated Circuit Solution, Inc.

IC61C1024

IC61C1024L

Integrated Circuit Solution Inc. 1

AHSR008-0B 10/18/2001

Document Title

128K x 8 High-Speed SRAM

Revision History

Revision No History Draft Date Remark

0A Initial Draft March 13,2001

0B Revise typo on page 6 and page 8 October 18,2001

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

IC61C1024

IC61C1024L

2Integrated Circuit Solution Inc.

AHSR008-0B 10/18/2001

128K x 8 HIGH-SPEED

CMOS STATIC RAM

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

DESCRIPTION

The ICSI IC61C1024 and IC61C1024L are very high-speed,

low power, 131,072-word by 8-bit CMOS static RAMs. They

are fabricated using ICSI's high-performance CMOS

technology. This highly reliable process coupled with innovative

circuit design techniques, yields higher performance and low

power consumption devices.

When CE1 is HIGH or CE2 is LOW (deselected), the device

assumes a standby mode at which the power dissipation can

be reduced by using CMOS input levels.

Easy memory expansion is provided by using two Chip Enable

inputs, CE1 and CE2. The active LOW Write Enable (WE)

controls both writing and reading of the memory.

The IC61C1024 and IC61C1024L are available in 32-pin

300mil SOJ, and 8*20mm TSOP-1, and 8*13.4mm TSOP-1

packages.

FUNCTIONAL BLOCK DIAGRAM

A0-A16

CE1

512 x 2048

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

CE2

FEATURES

• High-speed access time: 12, 15, 20, 25 ns

•Low active power: 600 mW (typical)

•Low standby power: 500 µW (typical) CMOS

standby

• Output Enable (OE) and two Chip Enable

(CE1 and CE2) inputs for ease in applications

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single 5V (±10%) power supply

• Low power version available: IC61C1024L

• Commercial and industrial temperature ranges

available

IC61C1024

IC61C1024L

Integrated Circuit Solution Inc. 3

AHSR008-0B 10/18/2001

TRUTH TABLE

Mode WEWE

WEWE

WE CE1CE1

CE1CE1

CE1 CE2 OEOE

OEOE

OE I/O Operation Vcc Current

Not Selected X H X X High-Z ISB1, ISB2

(Power-down) X X L X High-Z ISB1, ISB2

Output Disabled H L H H High-Z ICC1, ICC2

Read H L H L DOUT ICC1, ICC2

Write L L H X DIN ICC1, ICC2

A16

A14

A12

I/O0

I/O1

I/O2

GND

VCC

A15

CE2

A13

A11

A10

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

PIN CONFIGURATION

32-Pin SOJ

PIN DESCRIPTIONS

A0-A16 Address Inputs

CE1 Chip Enable 1 Input

CE2 Chip Enable 2 Input

OE Output Enable Input

WE Write Enable Input

I/O0-I/O7 Input/Output

Vcc Power

GND Ground

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

A11

A13

CE2

A15

VCC

A16

A14

A12

A10

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

PIN CONFIGURATION

32-Pin 8x20mm TSOP-1 and 8x13.4mm TSOP-1

IC61C1024

IC61C1024L

4Integrated Circuit Solution Inc.

AHSR008-0B 10/18/2001

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V

TBIAS Temperature Under Bias –55 to +125 °C

TSTG Storage Temperature –65 to +150 °C

PTPower Dissipation 1.5 W

IOUT DC Output Current (LOW) 20 mA

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

CAPACITANCE(1,2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 5 pF

COUT Output Capacitance VOUT = 0V 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V

VIH Input HIGH Voltage 2.2 VCC + 0.5 V

VIL Input LOW Voltage(1) –0.3 0.8 V

ILI Input Leakage GND ≤ VIN ≤ VCC Com. –2 2 µA

Ind. –5 5

ILO Output Leakage GND ≤ VOUT ≤ V CC Com. –2 2 µA

Outputs Disabled Ind. –5 5

Note:

1. VIL = –3.0V for pulse width less than 10 ns.

IC61C1024

IC61C1024L

Integrated Circuit Solution Inc. 5

AHSR008-0B 10/18/2001

IC61C1024 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

-12 ns -15 ns -20 ns -25 ns

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC1Vcc Operating VCC = VCC MAX., CE = VIL Com. — 85 — 85 — 85 — 85 mA

Supply Current IOUT = 0 mA, f = 0 Ind. — 110 — 110 — 110 — 110

ICC2Vcc Dynamic Operating VCC = VCC MAX., CE = VIL Com. — 170 — 160 — 150 — 140 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 180 — 170 — 160 — 150

ISB1TTL Standby Current VCC = VCC MAX., Com. — 40 — 40 — 40 — 40 mA

(TTL Inputs) VIN = VIH or VIL Ind. — 60 — 60 — 60 — 60

CE1

≥

VIH, f = 0 or

CE2

≤

VIL, f = 0

ISB2CMOS Standby VCC = VCC MAX., Com. — 30 — 30 — 30 — 30 mA

Current (CMOS Inputs) CE1

≥

VCC – 0.2V, Ind. — 40 — 40 — 40 — 40

CE2

≤

0.2V

VIN > V CC – 0.2V, or

VIN

≤

0.2V, f = 0

Note:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

IC61C1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

-15 ns -20 ns -25 ns

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

ICC1Vcc Operating VCC = VCC MAX., CE = VIL Com. — 85 — 85 — 85 mA

Supply Current IOUT = 0 mA, f = 0 Ind. — 110 — 110 — 110

ICC2Vcc Dynamic Operating VCC = VCC MAX., CE = VIL Com. — 160 — 150 — 140 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 170 — 160 — 150

ISB1TTL Standby Current VCC = VCC MAX, Com. — 40 — 40 — 40 mA

(TTL Inputs) VIN = VIH or VIL Ind. — 60 — 60 — 60

CE1

≥

VIH, f = 0 or

CE2

≤

VIL, f = 0

ISB2CMOS Standby VCC = VCC MAX., Com. — 500 — 500 — 500 µA

Current (CMOS Inputs) CE1

≥

VCC – 0.2V, Ind. — 750 — 750 — 750

CE2

≤

0.2V

VIN > V CC – 0.2V, or

VIN

≤

0.2V, f = 0

Note:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

IC61C1024

IC61C1024L

6Integrated Circuit Solution Inc.

AHSR008-0B 10/18/2001

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

-12

(2)

-15 ns -20 ns -25 ns

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 12 — 15 — 20 — 25 — ns

tAA Address Access Time — 12 — 15 — 20 — 25 ns

tOHA Output Hold Time 3 — 3 — 3 — 3 — ns

tACE1CE1 Access Time — 12 — 15 — 20 — 25 ns

tACE2CE2 Access Time — 12 — 15 — 20 — 25 ns

tDOE OE Access Time — 6 — 7 — 9 — 9 ns

tLZOE

(3)

OE to Low-Z Output 0 — 0 — 0 — 0 — ns

tHZOE

(3)

OE to High-Z Output 0 6 0 6 0 7 0 10 ns

tLZCE1

(3)

CE1 to Low-Z Output 2 — 2 — 3 — 3 — ns

tLZCE2

(3)

CE2 to Low-Z Output 2 — 2 — 3 — 3 — ns

tHZCE

(3)

CE1 or CE2 to High-Z Output 0 7 0 8 0 9 0 10 ns

tPU

(4)

CE1 or CE2 to Power-Up 0 — 0 — 0 — 0 — ns

tPD

(4)

CE1 or CE2 to Power-Down — 12 — 12 — 18 — 20 n s

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. -12 ns device for IC61C1024 only.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

4. Not 100% tested.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V

Input Rise and Fall Times 3 ns

Input and Output Timing 1.5V

and Reference Level

Output Load See Figures 1 and 2

AC TEST LOADS

Figure 1 Figure 2

480 Ω

5 pF

Including

jig and

scope

255 Ω

OUTPUT

480 Ω

30 pF

Including

jig and

scope

255 Ω

OUTPUT

IC61C1024

IC61C1024L

Integrated Circuit Solution Inc. 7

AHSR008-0B 10/18/2001

DATA VALID

PREVIOUS DATA VALID

OHA

DOUT

ADDRESS

t RC

t OHA

t AA

t DOE

t LZOE

t ACE

t LZCE

t HZOE

HIGH-Z DATA VALID

ADDRESS

OUT

t HZCE

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.

READ CYCLE NO. 2(1,3)

AC WAVEFORMS

READ CYCLE NO. 1(1,2)

IC61C1024

IC61C1024L

8Integrated Circuit Solution Inc.

AHSR008-0B 10/18/2001

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low

Power)

-12 ns

(3)

-15 ns -20 ns -25 ns

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 12 — 15 — 20 — 25 — ns

tSCE1CE1 to Write End 10 — 12 — 15 — 20 — ns

tSCE2CE2 to Write End 10 — 12 — 15 — 20 — ns

tAW Address Setup Time to Write End 10 — 12 — 15 — 20 — ns

tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns

tSA Address Setup Time 0 — 0 — 0 — 0 — ns

tPWE

(4)

WE Pulse Width 10 — 10 — 12 — 15 — ns

tSD Data Setup to Write End 7 — 8 — 10 — 12 — ns

tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns

tHZWE

(5)

WE LOW to High-Z Output — 7 — 7 — 10 — 12 n s

tLZWE

(5)

WE HIGH to Low-Z Output 2 — 2 — 2 — 2 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

3. -12 ns device for IC61C1024 only.

4. Tested with OE HIGH.

5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

IC61C1024

IC61C1024L

Integrated Circuit Solution Inc. 9

AHSR008-0B 10/18/2001

WRITE CYCLE NO. 2

(OE is HIGH During Write Cycle)

(1,2)

DATA UNDEFINED

LOW

t WC

VALID ADDRESS

t PWE1

t AW

t HA

HIGH-Z

t HD

t SA t HZWE

ADDRESS

OUT

DATAIN VALID

t LZWE

t SD

Notes:

1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states

to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced

to the rising or falling edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE = VIH.

DATA UNDEFINED

t WC

VALID ADDRESS

t SCE

t PWE1

t PWE2

t AW

t HA

HIGH-Z

t HD

t SA

t HZWE

ADDRESS

OUT

IN DATAIN VALID

t LZWE

t SD

AC WAVEFORMS

WRITE CYCLE NO. 1

(CE Controlled, OE is HIGH or LOW)

(1 )

IC61C1024

IC61C1024L

10 Integrated Circuit Solution Inc.

AHSR008-0B 10/18/2001

WRITE CYCLE NO. 3

(OE is LOW During Write Cycle)

(1)

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

HZWE

ADDRESS

DOUT

DIN

DATA

VALID

LZWE

IC61C1024 STANDARD VERSION

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

12 IC61C1024-12J 300mil SOJ

12 IC61C1024-12K 400mil SOJ

12 IC61C1024-12H 8*13.4mm TSOP-1

12 IC61C1024-12T 8*20mm TSOP-1

15 IC61C1024-15J 300mil SOJ

15 IC61C1024-15K 400mil SOJ

15 IC61C1024-15H 8*13.4mm TSOP-1

15 IC61C1024-15T 8*20mm TSOP-1

20 IC61C1024-20J 300mil SOJ

20 IC61C1024-20K 400mil SOJ

20 IC61C1024-20H 88*13.4mm TSOP-1

20 IC61C1024-20T 8*20mm TSOP-1

25 IC61C1024-25J 300mil SOJ

25 IC61C1024-25K 400mil SOJ

25 IC61C1024-25H 8*13.4mm TSOP-1

25 IC61C1024-25T 8*20mm TSOP-1

IC61C1024 STANDARD VERSION

ORDERING INFORMATION

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

12 IC61C1024-12JI 300mil SOJ

12 IC61C1024-12KI 400mil SOJ

12 IC61C1024-12HI 8*13.4mm TSOP-1

12 IC61C1024-12TI 8*20mm TSOP-1

15 IC61C1024-15JI 300mil SOJ

15 IC61C1024-15KI 400mil SOJ

15 IC61C1024-15HI 8*13.4mm TSOP-1

15 IC61C1024-15TI 8*20mm TSOP-1

20 IC61C1024-20JI 300mil SOJ

20 IC61C1024-20KI 400mil SOJ

20 IC61C1024-20HI 8*13.4mm TSOP-1

20 IC61C1024-20TI 8*20mm TSOP-1

25 IC61C1024-25JI 300mil SOJ

25 IC61C1024-25KI 400mil SOJ

25 IC61C1024-25HI 8*13.4mm TSOP-1

25 IC61C1024-25TI 8*20mm TSOP-1

IC61C1024

IC61C1024L

Integrated Circuit Solution Inc. 11

AHSR008-0B 10/18/2001

IC61C1024L LOW POWER VERSION

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

15 IC61C1024L-15J 300mil SOJ

IC61C1024L-15K 400mil SOJ

IC61C1024L-15H 8*13.4mm TSOP-1

IC61C1024L-15T 8*20mm TSOP-1

20 IC61C1024L-20J 300mil SOJ

IC61C1024L-20K 400mil SOJ

IC61C1024L-20H 8*13.4mm TSOP-1

IC61C1024L-20T 8*20mm TSOP-1

25 IC61C1024L-25J 300mil SOJ

IC61C1024L-25K 400mil SOJ

IC61C1024L-25H 8*13.4mm TSOP-1

IC61C1024L-25T 8*20mm TSOP-1

IC61C1024L LOW POWER VERSION

ORDERING INFORMATION

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

15 IC61C1024L-15JI 300mil SOJ

IC61C1024L-15KI 400mil SOJ

IC61C1024L-12HI 8*13.4mm TSOP-1

IC61C1024L-15TI 8*20mm TSOP-1

20 IC61C1024L-20JI 300mil SOJ

IC61C1024L-20KI 400mil SOJ

IC61C1024L-12HI 8*13.4mm TSOP-1

IC61C1024L-20TI 8*20mm TSOP-1

25 IC61C1024L-25JI 300mil SOJ

IC61C1024L-25KI 400mil SOJ

IC61C1024L-12HI 8*13.4mm TSOP-1

IC61C1024L-25TI 8*20mm TSOP-1

Integrated Circuit Solution Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: 886-3-5780333

Fax: 886-3-5783000

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: 886-2-26962140

FAX: 886-2-26962252

http://www.icsi.com.tw