18-Bit, 2 MSPS SAR ADC AD7641 FEATURES APPLICATIONS Medical instruments High speed data acquisition/high dynamic data acquisition Digital signal processing Spectrum analysis Instrumentation Communications ATE GENERAL DESCRIPTION The AD7641 is an 18-bit, 2 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. The part contains a high speed, 18-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. It features two very high sampling rate modes (wideband warp and warp) and a fast mode (normal) for asynchronous rate applications. The AD7641 is hardware factory calibrated and tested to ensure ac parameters, such as signal-to-noise ratio (SNR), in addition to the more traditional dc parameters of gain, offset, and linearity. The AD7641 is available in Pb-free only packages with operation specified from -40C to +85C. FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND AGND DVDD DGND OVDD AD7641 AVDD OGND REF REF AMP IN+ SERIAL PORT SWITCHED CAP DAC IN- 18 PARALLEL INTERFACE PDREF MODE0 MODE1 BUSY CLOCK PDBUF PD D[17:0] RD CONTROL LOGIC AND CALIBRATION CIRCUITRY CS RESET D0/OB/2C WARP 04761-001 Throughput 2 MSPS (wideband warp and warp mode) 1.5 MSPS (normal mode) INL: 2 LSB typical, 3 LSB max; 8 ppm of full scale 18-bit resolution with no missing codes Dynamic range: 95.5 dB SNR: 93.5 dB typical @ 20 kHz (VREF = 2.5 V) THD: -112 dB typical @ 20 kHz (VREF = 2.5 V) 2.048 V internal reference: typ drift 10 ppm/C; TEMP output Differential input range: VREF (VREF up to 2.5 V) No pipeline delay (SAR architecture) Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface SPI(R)/QSPITM/MICROWIRETM/DSP compatible Single 2.5 V supply operation Power dissipation 75 mW typical @ 2 MSPS with internal REF 2 W in power-down mode Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ Speed upgrade of the AD7674, AD7678, AD7679 NORMAL CNVST Figure 1. Table 1. PulSAR(R) Selection Type/kSPS Pseudo Differential True Bipolar True Differential 18-Bit Multichannel/ Simultaneous 100 to 250 AD7651, AD7660, AD7661 AD7610, AD7663 AD7675 AD7631, AD7678 500 to 570 AD7650, AD7652, AD7664, AD7666 AD7665 AD7676 AD7679 AD7654 650 to 1000 AD7653, AD7667 AD7612, AD7671 AD7677 AD7634, AD7674 AD7655 >1000 AD7621, AD7622, AD7623 AD7641, AD7643 PRODUCT HIGHLIGHTS 1. Fast Throughput. The AD7641 is a 2 MSPS, charge redistribution, 18-bit SAR ADC. 2. Superior Linearity. The AD7641 has no missing 18-bit code. 3. Internal Reference. The AD7641 has a 2.048 V internal reference with a typical drift of 10 ppm/C and an on-chip TEMP sensor. 4. Single-Supply Operation. The AD7641 operates from a 2.5 V single supply. 5. Serial or Parallel Interface. Versatile parallel (16- or 8-bit bus) or 2-wire serial interface arrangement compatible with 2.5 V, 3.3 V, or 5 V logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. AD7641 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 17 Applications....................................................................................... 1 Multiplexed Inputs ..................................................................... 17 General Description ......................................................................... 1 Driver Amplifier Choice ........................................................... 17 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 18 Product Highlights ........................................................................... 1 Power Supply............................................................................... 20 Revision History ............................................................................... 2 Conversion Control ................................................................... 20 Specifications..................................................................................... 3 Interfaces.......................................................................................... 21 Timing Specifications....................................................................... 5 Digital Interface.......................................................................... 21 Absolute Maximum Ratings............................................................ 7 Parallel Interface......................................................................... 21 ESD Caution.................................................................................. 7 Serial interface ............................................................................ 22 Pin Configuration and Function Descriptions............................. 8 Master Serial Interface............................................................... 22 Terminology .................................................................................... 11 Slave Serial Interface .................................................................. 24 Typical Performance Characteristics ........................................... 12 Microprocessor Interfacing....................................................... 26 Appplications Information ............................................................ 15 Application Hints ........................................................................... 27 Circuit Information.................................................................... 15 Layout .......................................................................................... 27 Converter Operation.................................................................. 15 Evaluating the AD7641 Performance ...................................... 27 Modes of Operation ................................................................... 15 Outline Dimensions ....................................................................... 28 Transfer Functions...................................................................... 16 Ordering Guide .......................................................................... 28 Typical Connection Diagram........................................................ 17 REVISION HISTORY 1/06--Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7641 SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance 2 THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error 3 Integral Linearity Error No Missing Codes Differential Linearity Error Transition Noise Transition Noise Zero Error, TMIN to TMAX 5 Zero Error Temperature Drift Gain Error, TMIN to TMAX5 Gain Error Temperature Drift Power Supply Sensitivity AC ACCURACY Dynamic Range Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) -3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Conditions Min 18 VIN+ - VIN- VIN+, VIN- to AGND fIN = 100 kHz 2 MSPS throughput -VREF -0.1 Wideband warp, warp modes Wideband warp, warp modes Wideband warp, warp modes Normal mode Normal mode TMIN to TMAX = -40C to +70C TMIN to TMAX = -40C to +85C Typ Max Unit Bits +VREF AVDD 1 V V dB A 500 2 1 667 1.5 ns MSPS ms ns MSPS +3 +3.5 1 16 LSB 4 LSB4 Bits LSB LSB LSB LSB ppm/C % of FSR ppm/C LSB 95.5 93.5 92 93 112 113 101 -115 -116 -101 93.5 92 92.5 50 dB 6 dB dB dB dB dB dB dB dB dB dB dB dB MHz 1 5 ns ps rms ns 58 18 0.001 0 -3 -3.5 18 -1 VREF = 2.5 V VREF = 2.048 V 2 2 +2 1.6 2.0 -15 +15 0.5 -0.25 AVDD = 2.5 V 5% VREF = 2.5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, VREF = 2.5 V fIN = 20 kHz, , VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, , VREF = 2.5 V Full-scale step PDREF = PDBUF = low REF @ 25C -40C to +85C AVDD = 2.5 V 5% Rev. 0 | Page 3 of 28 +0.25 115 2.038 2.048 10 15 2.058 V ppm/C ppm/V AD7641 Parameter Turn-On Settling Time REFBUFIN Output Voltage REFBUFIN Output Resistance EXTERNAL REFERENCE Voltage Range Current Drain REFERENCE BUFFER REFBUFIN Input Voltage Range REFBUFIN Input Current TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format 7 Pipeline Delay 8 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current 10 AVDD 11 DVDD OVDD12 Power Dissipation11 With Internal Reference10 Without Internal Reference10 In Power-Down Mode 12 TEMPERATURE RANGE 13 Specified Performance Conditions CREF = 10 F REFBUFIN @ 25C PDREF = PDBUF = high REF 2 MSPS throughput PDREF = high, PDBUF = low REF = 2.048 V typ REFBUFIN = 1.2 V Min Typ 5 1.19 6.33 Max Unit ms V k 1.8 2.048 180 AVDD + 0.1 V A 1.05 1.2 1 1.30 V nA @ 25C 278 1 4.7 -0.3 1.7 -1 -1 ISINK = 500 A ISOURCE = -500 A mV mV/C k +0.6 5.25 +1 +1 V V A A 0.4 V V 2.63 2.63 3.6 V V V OVDD - 0.3 2.37 2.37 2.30 9 2 MSPS throughput With internal reference 23 2.5 0.5 2 MSPS throughput 2 MSPS throughput PD = high TMIN to TMAX 75 68 2 -40 1 2.5 2.5 mA mA mA 92 85 mW mW W +85 C When using an external reference. With the internal reference, the input range is -0.1 V to VREF. See Analog Inputs section. 3 Linearity is tested using endnotes, not best fit. 4 LSB means least significant bit. With the 2.048 V input range, 1 LSB is 15.63 V. 5 See Voltage Reference Input section. These specifications do not include the error contribution from the external reference. 6 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 7 Parallel or serial 18-bit. 8 Conversion results are available immediately after completed conversion. 9 See the Absolute Maximum Ratings section. 10 In warp mode. Tested in parallel reading mode. 11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high. 12 With all digital inputs forced to OVDD. 13 Consult sales for extended temperature range. 2 Rev. 0 | Page 4 of 28 AD7641 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter CONVERSION AND RESET (Refer to Figure 29 and Figure 30) Convert Pulse Width Time Between Conversions (Warp Mode 2 /Normal Mode 3 ) CNVST Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) Aperture Delay End of Conversion to BUSY Low Delay Conversion Time (Warp Mode/Normal Mode) Acquisition Time (Warp Mode/Normal Mode) RESET Pulse Width RESET Low to BUSY High Delay 4 BUSY High Time from RESET Low4 PARALLEL INTERFACE MODES (Refer to Figure 31 to Figure 34 ) CNVST Low to Data Valid Delay (Warp Mode/Normal Mode) Data Valid to BUSY Low Delay Bus Access Request to Data Valid Bus Relinquish Time MASTER SERIAL INTERFACE MODES 5 (Refer to Figure 35 and Figure 36) CS Low to SYNC Valid Delay CS Low to Internal SCLK Valid Delay5 Symbol Min t1 t2 t3 15 500/667 t4 t5 t6 t7 t8 t9 t38 t39 Typ Unit 70 1 ns ns ns 23 385/520 1 10 385/520 115 15 10 600 t10 t11 t12 t13 Max 385/520 ns 20 15 ns ns ns 2 2 ns ns ns ns ns ns ns ns t14 10 ns t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay (Warp Mode/Normal Mode) SYNC Asserted to SCLK First Edge Delay Internal SCLK Period 6 Internal SCLK High6 Internal SCLK Low6 SDOUT Valid Setup Time6 SDOUT Valid Hold Time6 SCLK Last Edge to SYNC Delay6 CS High to SYNC HI-Z t17 10 ns ns ns ns ns ns ns ns CS High to Internal SCLK HI-Z t26 10 ns CS High to SDOUT HI-Z t27 10 ns t18 t19 t20 t21 t22 t23 t24 t25 6 BUSY High in Master Serial Read After Convert CNVST Low to SYNC Asserted Delay (All Modes) SYNC Deasserted to BUSY Low Delay SLAVE SERIAL INTERFACE MODES (Refer to Figure 38 and Figure 39) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK High External SCLK Low 1 14/137 0.5 8 2 3 1 0 0 ns 14 t28 t29 See Table 4 383/500 ns ns t30 13 ns t31 t32 t33 t34 t35 t36 t37 5 1 5 5 12.5 5 5 8 See the Conversion Control section. All timings for wideband warp mode are the same as warp mode. In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 4 See the Digital Interface section and the RESET section. 5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications. 2 3 Rev. 0 | Page 5 of 28 ns ns ns ns ns ns ns AD7641 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK High Minimum Internal SCLK Low Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY High Width Maximum 500A 0 0 0.5 8 14 2 3 1 0 0 0.630 0 1 3 16 26 6 7 5 0.5 0.5 0.870 1 0 3 32 52 15 16 5 10 9 1.350 1 1 3 64 103 31 32 5 28 26 2.28 Unit ns ns ns ns ns ns ns ns s IOL 1.4V CL 50pF 2V IOH NOTE IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. tDELAY tDELAY 2V 0.8V 2V 0.8V Figure 3. Voltage Reference Levels for Timing Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. 0 | Page 6 of 28 04761-003 500A 0.8V 04761-002 TO OUTPUT PIN Symbol t18 t19 t19 t20 t21 t22 t23 t24 t24 AD7641 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs/Outputs IN+ 1 , IN-, REF, REFBUFIN, TEMP, INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD OVDD AVDD to DVDD AVDD, DVDD to OVDD Digital Inputs PDREF, PDBUF 2 Internal Power Dissipation 3 Internal Power Dissipation 4 Junction Temperature Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating AVDD + 0.3 V to AGND - 0.3 V 0.3 V -0.3 V to +2.7 V -0.3 V to +3.8 V 2.8 V -3.8 V to +2.8 V -0.3 V to +5.5 V 20 mA 700 mW 2.5 W 125C -65C to +125C 1 See Analog Inputs section. See Voltage Reference Input section. 3 Specification is for the device in free air: 48-Lead LQFP; JA = 91C/W, JC = 30C/W. 4 Specification is for the device in free air: 48-Lead LFCSP; JA = 26C/W. 2 ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 28 AD7641 REFGND REF IN- NC AGND IN+ AGND AVDD PDBUF PDREF REFBUFIN TEMP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 35 AGND CNVST MODE0 3 MODE1 4 34 PD 33 D0/OB/2C 5 32 RESET CS 31 RD 30 29 DGND BUSY D2/A1 9 D3 10 28 D17 27 D16 D4/DIVSCLK[0] 11 D5/DIVSCLK[1] 12 26 D15 D14 AD7641 WARP 6 TOP VIEW (Not to Scale) NORMAL 7 D1/A0 8 25 04761-004 D13/RDERROR D11/SCLK D12/SYNC D10/SDOUT DVDD DGND OVDD D8/INVSCLK D9/RDC/SDIN OGND 13 14 15 16 17 18 19 20 21 22 23 24 D6/EXT/INT D7/INVSYNC NC = NO CONNECT 36 PIN 1 IDENTIFIER Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 36, 41, 42 2, 44 3, 4 Mnemonic AGND Type 1 P Description Analog Power Ground Pin. AVDD MODE[0:1] P DI 5 D0/OB/2C DI/O 6 WARP DI 7 NORMAL DI 8 D1/A0 DI/O 9 D2/A1 DI/O 10 D3 D0 11, 12 D[4:5] or DIVSCLK[0:1] DI/O Input Analog Power Pins. Nominally 2.5 V. Data Output Interface Mode Selection. Interface MODE# MODE1 MODE0 Description 0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 8-bit (byte) interface 3 1 1 Serial interface When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight binary/twos complement. When OB/2C is high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied to guarantee full specified accuracy. Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate. When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output as shown in Table 7. When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus. When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. Rev. 0 | Page 8 of 28 AD7641 Pin No. 13 Mnemonic D6 or EXT/INT Type 1 DI/O 14 D7 or INVSYNC DI/O 15 D8 or INVSCLK DI/O 16 D9 or RDC DI/O or SDIN 17 18 OGND OVDD P P 19 20 21 DVDD DGND D10 or SDOUT P P DO 22 D11 or SCLK DI/O 23 D12 or SYNC DO 24 D13 or RDERROR DO Description When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus. When MODE[1:0] = 3, (serial mode), serial clock source select. This input is used to select the internally generated (master) or external (slave) serial data clock. When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus. When MODE[1:0] = 3, (serial mode), invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus. When MODE[1:0] = 3, (serial mode), invert SCLK select. In all serial modes, this input is used to invert the SCLK signal. When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus. When MODE[1:0] = 3, (serial mode), read during convert. When using serial master mode (EXT/INT = low), RDC is used to select the read mode. When RDC = high, the previous conversion result is output on SDOUT during conversion and the period of SCLK changes (see the Master Serial Interface section). When RDC = low (read after convert), the current result can be output on SDOUT only when the conversion is complete. When MODE[1:0] = 3, (serial mode), serial data in. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence. Input/Output Interface Digital Power Ground. Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V). Digital Power. Nominally at 2.5 V. Digital Power Ground. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus. When MODE[1:0] = 3, (serial mode), serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7641 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In master mode, EXT/INT = low. SDOUT is valid on both edges of SCLK. In slave mode, EXT/INT = high: When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus. When MODE[1:0] = 3, (serial mode), serial clock. In all serial modes, this pin is used as the serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus. When MODE[1:0] = 3, (serial mode), frame synchronization. In serial master mode (EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus. When MODE[1:0] = 3, (serial mode), read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. Rev. 0 | Page 9 of 28 AD7641 Pin No. 25 to 28 29 Mnemonic D[14:17] Type 1 DO BUSY DO 30 31 DGND RD P DI 32 CS DI 33 RESET DI 34 PD DI 35 CNVST DI 37 REF AI/O 38 39 40 43 45 46 REFGND IN- NC IN+ TEMP REFBUFIN AI AI AI AO AI/O 47 PDREF DI 48 PDBUF DI 1 Description Bit 14 to Bit 17 of the parallel port data output bus. These pins are always outputs, regardless of the interface mode. Busy Output. Transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. Digital Power Ground. Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode. Reset Input. When high, resets the AD7641. Current conversion, if any, is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If not used, this pin can be tied to DGND. Power-Down Input. When high, power downs the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Refer to the Voltage Reference Input section. Reference Input Analog Ground. Differential Negative Analog Input. No Connect. Differential Positive Analog Input. Temperature Sensor Analog Output. Internal Reference Output/Reference Buffer Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical) band gap output on this pin, which needs external decoupling. The internal fixed gain reference buffer uses this to produce 2.048 V on the REF pin. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section. Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must been used. Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. Table 7. Data Bus Interface Definition MODE MODE1 MODE0 0 1 0 0 0 1 1 0 1 2 1 0 2 1 0 2 1 0 2 1 0 3 1 1 D0/OB/2C R[0] OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description R[1] A0 = 0 R[2] R[2] R[3] R[3] R[4:9] R[4:9] R[10:11] R[10:11] R[12:15] R[12:15] R[16:17] R[16:17] 18-Bit Parallel 16-Bit High Word OB/2C OB/2C A0 = 1 R[0] R[1] A0 = 0 A1 = 0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit High Byte OB/2C OB/2C A0 = 0 A1 = 1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit Mid Byte A0 = 1 A1 = 0 All Hi-Z R[0:1] OB/2C OB/2C A0 = 1 A1 = 1 All Hi-Z All Hi-Z Rev. 0 | Page 10 of 28 All Zeros 16-Bit Low Word All Zeros All Zeros Serial Interface R[0:1] 8-Bit Low Byte 8-Bit Low Byte Serial Interface AD7641 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Gain Error The first transition (from 000...00 to 000...01) should occur for an analog voltage 1/2 LSB above the nominal negative full scale (-2.0479922 V for the 2.048 V range). The last transition (from 111...10 to 111...11) should occur for an analog voltage 11/2 LSB below the nominal full scale (+2.0479766 V for the 2.048 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Signal to (Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINADdB - 1.76)/6.02] Aperture Delay Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Zero Error The zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Transient Response The time required for the AD7641 to achieve its rated accuracy after a full-scale step function is applied to its input. Dynamic Range It is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. It is derived from the typical shift of output voltage at 25C on a sample of parts maximum and minimum reference output voltage (VREF) measured at TMIN, T(25C), and TMAX. It is expressed in ppm/C using Reference Voltage Temperature Coefficient Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. TCVREF (ppm/C ) = VREF ( Max ) - VREF ( Min) x 10 6 VREF (25C ) x (TMAX - TMIN ) where: VREF (Max) = Maximum VREF at TMIN, T(25C), or TMAX VREF (Min) = Minimum VREF at TMIN, T(25C), or TMAX VREF (25C) = VREF at 25C TMAX = +85C TMIN = -40C Rev. 0 | Page 11 of 28 AD7641 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 2.0 2.5 1.5 2.0 1.5 1.0 0.5 DNL (LSB) INL (LSB) 1.0 0 -0.5 -1.0 -1.5 0.5 0 -0.5 -1.0 -2.0 65536 0 131072 196608 -2.0 262144 04761-008 -3.0 -1.5 04761-005 -2.5 0 65536 131072 CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 40000 30000 = 1.55 34844 35000 = 2.02 24731 23436 22225 25000 31003 30000 18995 20000 COUNTS 24739 25000 COUNTS 262144 196608 CODE 20000 16207 15000 15000 12922 10846 10000 10938 8219 10000 CODE IN HEX VREF (V) 2.0515 2.0510 2.0505 2.0500 2.0495 04761-007 2.0490 2.0485 5 25 45 65 85 105 125 TEMPERATURE (C) 20 18 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -55 04761-009 1FEEB 1FEE9 1FEEA 1FEE8 1FEE7 1FEE6 1FEE5 1FEE4 1FEE3 -FS ZERO-ERROR 04761-010 2.0520 ZERO-ERROR, FULL-SCALE ERROR (LSB) 2.0525 -15 1FEE2 Figure 9. Histogram of 261,120 Conversions of a DC Input at the Code Center (Internal Reference) 2.0530 -35 1FEE1 CODE IN HEX Figure 6. Histogram of 261,120 Conversions of a DC Input at the Code Center (External Reference) 2.0480 -55 1171 589 51 10 1 1FEE0 1FEDF 1FEDE 1FEDD 1FEDC 0 1FEDB 20000 1 1FED9 0 2105 912 1 52 117 1FEDA 0 1FFFF 1FFFE 1FFFD 1FFFC 1FFFB 1FFF9 1FFFA 1FFF8 1FFF7 1FFF6 1FFF5 1FFF1 232 39 1FFF4 1FFF0 2124 272 1FFF3 2 1FFF2 0 1FFEF 0 11 0 4688 5000 5248 683 04761-006 4730 5000 +FS -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) Figure 7. Typical Reference Voltage Output vs. Temperature (3 Units) Rev. 0 | Page 12 of 28 Figure 10. Zero Error, Positive and Negative Full Scale vs. Temperature AD7641 -60 -80 -100 -120 -140 100 200 300 400 500 600 700 800 900 04761-014 500 600 85 14.0 83 13.6 81 13.2 79 12.8 77 12.4 10 100 SNR, SINAD (dB) 14.4 ENOB (Bits) 87 12.0 1000 FREQUENCY (kHz) -80 -90 18 93 17 92 90 -55 -90 110 -95 100 -100 SFDR (dB) 60 50 -130 SECOND HARMONIC 10 100 FREQUENCY (kHz) 15 -35 -15 5 25 45 65 85 105 14 125 -110 110 105 THIRD HARMONIC THD 100 -115 95 -120 90 -125 40 30 -135 20 1000 120 115 SFDR -105 -130 04761-013 THIRD HARMONIC 16 SINAD TEMPERATURE (C) 120 70 THD 1000 Figure 15. SNR, SINAD, and ENOB vs. Temperature 80 -110 900 91 90 -100 800 19 ENOB THD, HARMONICS (dB) SFDR 700 94 Figure 12. SNR, SINAD, and ENOB vs. Frequency THD, HARMONICS (dB) 400 SNR 04761-012 SNR, SINAD (dB) 14.8 1 300 95 15.6 SNR SINAD 15.2 -140 200 Figure 14. FFT 100 kHz 89 -120 100 Figure 11. FFT 20 kHz ENOB -70 0 FREQUENCY (kHz) 16.0 1 -140 -180 1000 91 75 -120 FREQUENCY (kHz) 95 93 -100 ENOB (Bits) 0 -80 04761-015 -180 -60 -160 04761-011 -160 -40 -140 -55 85 SECOND HARMONIC 80 75 -35 -15 5 25 45 65 85 105 70 125 TEMPERATURE (C) Figure 16. THD, Harmonics, and SFDR vs. Temperature Figure 13. THD, Harmonics, and SFDR vs. Frequency Rev. 0 | Page 13 of 28 SFDR (dB) -40 fS = 2MSPS fIN = 100.8kHz SNR = 93dB THD = -101dB SFDR = 101dB SINAD = 92.5dB -20 AMPLITUDE (dB of Full Scale) -20 AMPLITUDE (dB of Full Scale) 0 fS = 2MSPS fIN = 20.1kHz SNR = 93.6dB THD = -116dB SFDR = 112dB SINAD = 93.5dB 04761-016 0 AD7641 100000 AVDD 10000 OPERATING CURRENTS (A) 95.0 SNR 94.5 SINAD 94.0 1000 93.5 93.0 -60 -50 -40 -30 -20 OVDD = 2.5V, ALL MODES 10 1 OVDD = 3.3V, ALL MODES 0.1 0.01 10 0 -10 DVDD 100 PDREF = PDBUF = HIGH 100 1k INPUT LEVEL (dB) 10k 100k 1M 10M SAMPLING RATE (SPS) Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 19. Operating Current vs. Sample Rate 16 20 14 18 12 16 OVDD = 2.5V @ 85C t12 DELAY (ns) OVDD = 2.5V @ 25C 10 DVDD 8 OVDD, 3.3V 6 14 12 10 OVDD = 3.3V @ 25C OVDD, 2.5V 8 2 6 0 -55 AVDD -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 4 OVDD = 3.3V @ 85C 04761-020 4 04761-018 DVDD, OVDD (A) 04761-019 95.5 04761-017 SNR, SINAD REFERRED TO FULL SCALE (dB) 96.0 4 50 100 150 200 CL (pF) Figure 18. Power-Down Operating Currents vs. Temperature Figure 20. Typical Delay vs. Load Capacitance CL Rev. 0 | Page 14 of 28 AD7641 APPPLICATIONS INFORMATION IN+ AGND LSB MSB 131,072C 65,536C 4C 2C C SW+ SWITCHES CONTROL C BUSY REF COMP REFGND 4C 2C C OUTPUT CODE C MSB SW- LSB CNVST AGND IN- 04761-021 131,072C 65,536C CONTROL LOGIC Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7641 is a very fast, low power, single-supply, precise 18-bit ADC using successive approximation architecture. The AD7641 features different modes to optimize performances according to the applications. In warp mode, the AD7641 is capable of converting 2,000,000 samples per second (2 MSPS). The AD7641 provides the user with an on-chip track-and-hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7641 can operate from a single 2.5 V supply and interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed in a 48-lead LQFP package or a tiny 48-lead LFCSP package, which combines space savings with flexibility and allows the AD7641 to be configured as either a serial or a parallel interface. The AD7641 is pin-to-pin-compatible and is a speed upgrade of the AD7674, AD7678, and AD7679. CONVERTER OPERATION The AD7641 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors that are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator's input are connected to AGND via SW+ and SW-. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN- inputs. A conversion phase is initiated once the acquisition phase is complete and the CNVST input goes low. When the conversion phase begins, SW+ and SW- are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN-) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 throughVREF/131072). The control logic toggles these switches, starting with the MSB first, to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low. MODES OF OPERATION The AD7641 features three modes of operations: wideband warp, warp, and normal. Each of these modes is more suitable for specific applications. The wideband warp (WARP = high, NORMAL = high) and warp (WARP = high, NORMAL = low) modes allow the fastest conversion rate of up to 2 MSPS. However, in these modes, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (for instance after power-up), the first conversion result should be ignored. These modes make the AD7641 ideal for applications where both high accuracy and fast sample rates are required. Wideband warp mode offers slightly improved linearity and THD over warp mode. Normal mode (NORMAL = low, WARP = low) is the fastest mode (1.5 MSPS) without any limitation on time between conversions. This mode makes the AD7641 ideal for asynchronous applications, such as data acquisition systems, where both high accuracy and fast sample rates are required. Rev. 0 | Page 15 of 28 AD7641 TRANSFER FUNCTIONS Table 8. Output Codes and Ideal Input Voltages Description FSR -1 LSB FSR - 2 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR 111...111 111...110 111...101 1 2 000...010 000...001 000...000 -FSR -FSR + 1 LSB -FSR + 0.5 LSB Digital Output Code (Hex) Straight Twos Binary Complement 1 0x3FFFF 0x1FFFF1 0x3FFFE 0x1FFFE 0x20001 0x00001 0x20000 0x00000 0x1FFFF 0x3FFFF 0x30001 0x20001 0x30000 2 0x200002 Analog Input VREF = 2.048 V +2.0479844 V +2.0479688 V +15.625 V 0V -15.625 V -2.0479844 V -2.048 V This is also the code for overrange analog input (VIN+ - VIN- above +VREF - VREFGND). This is also the code for underrange analog input (VIN+ - VIN- below -VREF + VREFGND). +FSR - 1 LSB 04761-022 ADC CODE (Straight Binary) Using the OB/2C digital input, except in 18-bit interface mode, the AD7641 offers two output codings: straight binary and twos complement. The LSB size with VREF = 2.048 V is 2 x VREF/ 262,144, which is 15.623 V. Refer to Figure 22 and Table 8 for the ideal transfer characteristic. +FSR - 1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function DIGITAL SUPPLY (2.5V) NOTE 5 DIGITAL INTERFACE SUPPLY (2.5V OR 3.3V) 10 ANALOG SUPPLY (2.5V) 100nF 10F 10F AVDD REF CREF 10F 100nF AGND 100nF 10F 100nF DGND DVDD OVDD NOTE 3 OGND SERIAL PORT SCLK REFBUFIN SDOUT REFGND NOTE 4 BUSY NOTE 2 ANALOG INPUT + U1 15 CNVST IN+ AD7641 CC 2.7nF 50 MICROCONVERTER/ MICROPROCESSOR/ DSP NOTE 7 D 50pF D0/OB/2C MODE0 MODE1 NOTE 1 OVDD WARP NORMAL NOTE 2 ANALOG INPUT - U2 CC 15 2.7nF NOTE 1 CS IN- CLOCK RD NOTE 3 PD PDREF PDBUF RESET 50pF 10k 1. SEE ANALOG INPUTS SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 10F CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTION, SEE POWER-UP SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 23. Typical Connection Diagram Rev. 0 | Page 16 of 28 04761-023 NOTE 6 AD7641 TYPICAL CONNECTION DIAGRAM Figure 23 shows a typical connection diagram for the AD7641. Different circuitry shown in this diagram is optional and is discussed in the following sections. ANALOG INPUTS Figure 24 shows an equivalent circuit of the input structure of the AD7641. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN-. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this causes the diodes to become forwardbiased and start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For instance, these conditions could eventually occur when the input buffer's U1 or U2 supplies are different from AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. Because the input impedance of the AD7641 is very high, the AD7641 can be directly driven by a low impedance source without gain error. To further improve the noise filtering achieved by the AD7641 analog input circuit, an external 1-pole RC filter between the amplifier's outputs and the ADC analog inputs can be used, as shown in Figure 23. However, large source impedances significantly affect the ac performance, especially the total harmonic distortion (THD). The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. MULTIPLEXED INPUTS AVDD D1 RIN IN+ OR IN- CIN D2 04761-024 CPIN switches. CIN is typically 12 pF and is mainly the ADC sampling capacitor. During the conversion phase, when the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that has a typical -3 dB cutoff frequency of 50 MHz, thereby reducing an undesirable aliasing effect and limiting the noise coming from the inputs. AGND Figure 24. AD7641 Simplified Analog Input The analog input of the AD7641 is a true differential structure. By using this differential input, small signals common to both inputs are rejected, as shown in Figure 25, representing the typical CMRR over frequency with internal and external references. 65 When using the full 2 MSPS throughput in multiplexed applications for a full-scale step, the RC filter, as shown in Figure 23, does not settle in the required acquisition time, t8. These values are chosen to optimize the best SNR perform-ance of the AD7641. To use the full 2 MSPS throughput in multiplexed applicaitons, the RC should be adjusted to satisfy t8 (which is ~ 8.5 x RC time constant). However, lowering R and C increases the RC filter bandwidth and allows more noise into the AD7641, which degrades SNR. To preserve the SNR performance in these applications using the RC filter shown in Figure 23, the AD7641 should be run with t8 > 350 ns; or approximately 1/(t7 + t8) ~ 1.35 MSPS in wideband and warp modes. DRIVER AMPLIFIER CHOICE 60 Although the AD7641 is easy to drive, the driver amplifier needs to meet the following requirements: CMRR (dB) EXT REF INT REF * 55 45 04761-025 50 1 10 100 1000 10000 FREQUENCY (kHz) Figure 25. Analog Input CMRR vs. Frequency During the acquisition phase for ac signals, the impedance of the analog inputs, IN+ and IN-, can be modeled as a parallel combination of capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 175 and is a lumped component comprised of some serial resistors and the on resistance of the Rev. 0 | Page 17 of 28 For multichannel, multiplexed applications, the driver amplifier and the AD7641 analog input circuit must be able to settle for a full-scale step of the capacitor array at an 18-bit level (0.0004%). In the amplifier's data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 18-bit level and should be verified prior to driver selection. The AD8021 op amp, which combines ultralow noise and high gain bandwidth, meets this settling time requirement even when used with gains up to 13. AD7641 Single-to-Differential Driver The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7641. The noise coming from the driver is filtered by the AD7641 analog input circuit 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. The SNR degradation due to the amplifier is SNRLOSS 30 = 20log f -3dB f 900 + (Ne N + )2 + -3dB (Ne N - )2 2 2 For applications using unipolar analog signals, a single-endedto-differential driver, as shown in Figure 26, allows for a differential input into the part. This configuration, when provided an input signal of 0 to VREF, produces a differential VREF with midscale at VREF/2. The 1-pole filter using R = 10 and C = 1 nF provides a corner frequency of 16 MHz. If the application can tolerate more noise, the AD8139 differential driver can be used. U1 ANALOG INPUT (UNIPOLAR 0V TO 2.048V) where: f-3dB is the input bandwidth of the AD7641 (50 MHz) or the cutoff frequency of the input RC filter shown in Figure 23 (3.9 MHz), if one is used. N is the noise factor of the amplifier (1 in buffer configuration). For instance, when using op amps with an equivalent input noise density of 2.1 nV/Hz, such as the AD8021, with a noise gain of 1 when configured as a buffer, degrades the SNR by only 0.25 dB when using the RC filter in Figure 23, and by 2.5 dB without it. * The driver needs to have a THD performance suitable to that of the AD7641. Figure 13 gives the THD vs. frequency that the driver should exceed. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting 1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. The AD8022 can also be used when a dual version is needed and a gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not required. In applications with a gain of 1, an 82 pF compensation capacitor is required. The AD8610 is an option when low bias current is needed in low frequency applications. 5k 590 15 590 2.7nF 15 U2 5k eN+ and eN- are the equivalent input voltage noise densities of the op amps connected to IN+ and IN-, in nV/Hz. This approximation can be used when the resistances used around the amplifier are small. If larger resistances are used, their noise contributions should also be root-sum squared. AD8021 10pF AD8021 100nF IN+ AD7641 IN- 2.7nF REF 10pF 10F 04761-027 * Figure 26. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) VOLTAGE REFERENCE INPUT The AD7641 allows the choice of either a very low temperature drift internal voltage reference or an external reference. Unlike many ADCs with internal references, the internal reference of the AD7641 provides excellent performance and can be used in almost all applications. Internal Reference (PDBUF = Low, PDREF = Low) To use the internal reference, the PDREF and PDBUF inputs must both be low. This produces a 1.2 V band gap output on REFBUFIN, which is amplified by the internal buffer and results in a 2.048 V reference on the REF pin. The internal reference is temperature compensated to 2.048 V 10 mV. The reference is trimmed to provide a typical drift of 10 ppm/C. This typical drift characteristic is shown in Figure 7. The output resistance of REFBUFIN is 6.33 k (minimum) when the internal reference is enabled. It is necessary to decouple this with a ceramic capacitor greater than 100 nF. Therefore, the capacitor provides an RC filter for noise reduction. Because the output impedance of REFBUFIN is typically 6.33 k, relative humidity (among other industrial contaminates) can directly affect the drift characteristics of the reference. Typically, a guard ring is used to reduce the effects of drift under such circumstances. Rev. 0 | Page 18 of 28 AD7641 External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) To use an external reference along with the internal buffer, PDREF should be high and PDBUF should be low. This powers down the internal reference and allows the 1.2 V reference to be applied to REFBUFIN, producing 2.048 V (typically) on the REF pin. External 2.5 V Reference (PDBUF = High, PDREF = High) To use an external 2.5 V reference directly on the REF pin, PDREF and PDBUF should both be high. For improved drift performance, an external reference, such as the AD780 or ADR431, can be used. The advantages of directly using the external voltage reference are: * The SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a reference voltage very close to the supply (2.5 V) instead of a typical 2.048 V reference when the internal reference is used. This is calculated by For applications that use multiple AD7641 devices, it is more effective to use an external reference with the internal reference buffer to buffer the reference voltage. However, because the reference buffers are not unity gain, ratiometric, simultaneously sampled designs should use an external reference and external buffer, such as the AD8031/AD8032; therefore, preserving the same reference level for all converters. The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a 4 ppm/C TC of the reference changes full scale by 1 LSB/C. Note that VREF can be increased to AVDD + 0.1 V. Because the input range is defined in terms of VREF, this would essentially increase the range to 0 V to 2.8 V with an AVDD = 2.7 V. Temperature Sensor The TEMP pin measures the temperature of the AD7641. To improve the calibration accuracy over the temperature range, the output of the TEMP pin is applied to one of the inputs of the analog switch (such as, ADG779), and the ADC itself is used to measure its own temperature. This configuration is shown in Figure 27. 2.048 SNR = 20 log 2.50 * TEMP ADG779 The power savings when the internal reference is powered down (PDREF high). IN+ ANALOG INPUT (UNIPOLAR) PDREF and PDBUF power down the internal reference and the internal reference buffer, respectively. The input current of PDREF and PDBUF should never exceed 20 mA. This can occur when the driving voltage is above AVDD (for instance, at power-up). In this case, a 125 series resistor is recommended. Reference Decoupling Whether using an internal or external reference, the AD7641 voltage reference input (REF) has a dynamic input impedance; therefore, it should be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and REFGND with minimum parasitic inductance. A 10 F (X5R, 1206 size) ceramic chip capacitor (or 47 F tantalum capacitor) is appropriate when using either the internal reference or one of the recommended reference voltages. The placement of the reference decoupling is also important to the performance of the AD7641. The decoupling capacitor should be mounted on the same side as the ADC right at the REF pin with a thick PCB trace. The REFGND should also connect to the reference decoupling capacitor with the shortest distance. Rev. 0 | Page 19 of 28 AD8021 CC TEMPERATURE SENSOR AD7641 Figure 27. Use of the Temperature Sensor 04761-028 However, because the AD7641 has a fine lead pitch, guarding this node is not practical. Therefore, in these industrial and other types of applications, it is recommended to use a conformal coating, such as Dow Corning(R) 1-2577 or HumiSeal(R) 1B73. AD7641 POWER SUPPLY The AD7641 uses three sets of power supply pins: an analog 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.3 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 23. Power Sequencing The AD7641 is independent of power supply sequencing and thus free from supply induced voltage latch-up. In addition, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 28. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, drive the digital inputs close to the power rails (that is, OVDD and OGND). CONVERSION CONTROL The AD7641 is controlled by the CNVST input. A falling edge on CNVST is all that is necessary to initiate a conversion. Detailed timing diagrams of the conversion process are shown in Figure 29. Once initiated, it cannot be restarted or aborted, even by the power-down input, PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. t2 t1 65.0 62.5 CNVST 57.5 BUSY EXT REF t6 t5 52.5 INT REF MODE 50.0 ACQUIRE CONVERT t7 04761-029 47.5 45.0 t4 t3 55.0 1 10 100 1000 10000 FREQUENCY (MHz) Figure 28. PSRR vs. Frequency Power-Up At power-up, or returning to operational mode from the powerdown mode (PD = high), the AD7641 engages an initialization process. During this time, the first 128 conversions should be ignored or the RESET input could be pulsed to engage a faster initialization process. Refer to the Digital Interface section for RESET and timing details. A simple power-on reset circuit, as shown in Figure 23, can be used to minimize the digital interface. As OVDD powers up, the capacitor is shorted and brings RESET high; it is then charged returning RESET to low. However, this circuit only works when powering up the AD7641 because the power-down mode (PD = high) does not power down any of the supplies and as a result, RESET is low. ACQUIRE CONVERT t8 04761-030 PSRR (dB) 60.0 Figure 29. Basic Conversion Timing For optimal performance, the rising edge of CNVST should not occur after the maximum CNVST low time, t1, or until the end of conversion. Although CNVST is a digital signal, it should be designed with special care with fast, clean edges and levels with minimum overshoot and undershoot or ringing. The CNVST trace should be shielded with ground and a low value serial resistor (for example, 50 ) termination should be added close to the output of the component that drives this line. In addition, a 50 pF capacitor is recommended to further reduce the effects of overshoot and undershoot as shown in Figure 23. For applications where SNR is critical, the CNVST signal should have very low jitter. This can be achieved by using a dedicated oscillator for CNVST generation, or by clocking CNVST with a high frequency, low jitter clock, as shown in Figure 23. Rev. 0 | Page 20 of 28 AD7641 INTERFACES DIGITAL INTERFACE PARALLEL INTERFACE The AD7641 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The serial interface is multiplexed on the parallel data bus. The AD7641 digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic high output voltage. In most applications, the OVDD supply pin of the AD7641 is connected to the host system interface 2.5 V or 3.3 V digital supply. By using the D0/OB/2C input pin, either twos complement or straight binary coding can be used. The AD7641 is configured to use the parallel interface for an 18-bit, 16-bit, or 8-bit bus width according to Table 7. Data can be continuously read by tying CS and RD low, thus requiring minimal microprocessor connections. However, in this mode, the data bus is always driven and cannot be used in shared bus applications, unless the device is held in RESET. Figure 31 details the timing for this mode. CS = RD = 0 t10 BUSY The RESET input is used to reset the AD7641 and generate a fast initialization. A rising edge on RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET clears the data bus and engages the initialization process indicated by pulsing BUSY high. Conversions can take place after the falling edge of BUSY. Refer to Figure 30 for the RESET timing details. t9 RESET t4 t3 DATA BUS RESET t1 CNVST t11 PREVIOUS CONVERSION DATA 04761-032 The two signals CS and RD control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7641 in multicircuit applications and is held low in a single AD7641 design. RD is generally used to enable the conversion result on the data bus. Master Parallel Interface NEW DATA Figure 31. Master Parallel Data Timing for Reading (Continuous Read) Slave Parallel Interface In slave parallel reading mode, the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 32 and Figure 33, respectively. When the data is read during the conversion, it is recommended that it is read-only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. CNVST CS DATA BUSY t39 Figure 30. RESET Timing t8 BUSY DATA BUS CURRENT CONVERSION t12 t13 Figure 32. Slave Parallel Data Timing for Reading (Read After Convert) Rev. 0 | Page 21 of 28 04761-033 t38 04761-031 RD AD7641 CS = 0 SERIAL INTERFACE t1 CNVST, RD BUSY The AD7641 is configured to use the serial interface when MODE[1:0] = 3. The AD7641 outputs 18 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. t4 t3 DATA BUS MASTER SERIAL INTERFACE Internal Clock t12 045761-034 PREVIOUS CONVERSION t13 Figure 33. Slave Parallel Data Timing for Reading (Read During Convert) 16-Bit and 8-Bit Interface (Master or Slave) In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2) interfaces, the A0/A1 pins allow a glueless interface to a 16- or 8-bit bus, as shown in Figure 34. By connecting A0/A1 to an address line(s), the data can be read in two words for a 16-bit interface, or three bytes for an 8-bit interface. This interface can be used in both master and slave parallel reading modes. Refer to Table 7 for the full details of the interface. CS, RD A1 HI-Z HIGH WORD HIGH BYTE t12 MID BYTE t12 LOW WORD HI-Z LOW BYTE HI-Z t12 Figure 34. 8-Bit and 16-Bit Parallel Interface t13 04761-035 D[17:10] HI-Z Usually, because the AD7641 is used with a fast throughput, the master read during conversion mode is the most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. In this mode, the SCLK period changes because the LSBs require more time to settle and the SCLK is derived from the SAR conversion cycle. In read after conversion mode, it should be noted that unlike other modes, the BUSY signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase, resulting in a longer BUSY width. As a result, the maximum throughput cannot be achieved in this mode. A0 D[17:2] The AD7641 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7641 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted. Depending on the read during convert input, RDC/SDIN, the data can be read after each conversion or during the following conversion. Figure 35 and Figure 36 show detailed timing diagrams of these two modes. In addition, in read after convert mode, the SCLK frequency can be slowed down to accommodate different hosts using the DIVSCLK[1:0] inputs. Refer to Table 4 for the SCLK timing details when using these inputs. Rev. 0 | Page 22 of 28 AD7641 EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 DIVSCLK[1:0] = 0 CS, RD t3 CNVST t28 BUSY t30 t29 t25 SYNC t18 t19 t14 t20 1 SCLK t24 t21 2 3 16 17 t26 18 t15 t27 D17 X t16 D16 D2 D1 D0 04761-036 SDOUT t23 t22 Figure 35. Master Serial Data Timing for Reading (Read After Convert) RDC/SDIN = 1 EXT/INT = 0 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t17 t25 SYNC t19 t20 t21 t14 SCLK t15 1 t24 2 3 16 17 t18 t16 X t22 t27 D17 D16 D2 D1 D0 04761-037 SDOUT t26 18 t23 Figure 36. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 23 of 28 AD7641 SLAVE SERIAL INTERFACE The AD7641 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 38 and Figure 39 show the detailed timing diagrams of these methods. While the AD7641 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7641 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, a discontinuous clock is toggled only when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high. External Discontinuous Clock Data Read After Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 38 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the conversion result can be read while both CS and RD are low. Data is shifted out MSB first with 18 clock pulses and is valid on the rising and falling edges of the clock. Among the advantages of this method is the fact that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 80 MHz, which accommodates both the slow digital host interface and the fast serial reading. Finally, in this mode only, the AD7641 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 37. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the edge of SCLK opposite to the one used to shift out the data on SDOUT. Therefore, the MSB of the upstream converter just follows the LSB of the downstream converter on the next SCLK cycle. BUSY OUT BUSY BUSY AD7641 AD7641 #2 (UPSTREAM) #1 (DOWNSTREAM) RDC/SDIN SDOUT RDC/SDIN SDOUT CNVST CNVST CS CS SCLK SCLK DATA OUT SCLK IN CS IN CNVST IN 04761-038 External Clock Figure 37.Two AD7641 Devices in a Daisy-Chain Configuration External Clock Data Read During Previous Conversion Figure 39 shows the detailed timing diagrams of this method. During a conversion, while CS and RD are both low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses and is valid on both the rising and falling edge of the clock. The 18 bits have to be read before the current conversion is complete; otherwise, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no daisy-chain feature in this mode, and the RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock (at least 60 MHz when normal mode is used, or 80 MHz when warp mode is used) is recommended to ensure that all the bits are read during the first half of the SAR conversion phase. It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion is initiated. However, this is not recommended when using the fastest throughput of any mode because the acquisition time, t8, is only 115 ns. If the maximum throughput is not used, thus allowing more acquisition time, then the use of a slower clock speed can be used to read the data. Rev. 0 | Page 24 of 28 AD7641 RD = 0 INVSCLK = 0 EXT/INT = 1 CS BUSY t35 t36 t37 SCLK 1 2 t31 3 16 17 18 19 20 t32 X SDOUT D17 t16 D16 D15 D1 D0 X17 X16 X16 X15 X1 X0 Y17 Y16 SDIN X17 t33 04761-039 t34 Figure 38. Slave Serial Data Timing for Reading (Read After Convert) t31 EXT/INT = 1 RD = 0 INVSCLK = 0 CS t3 CNVST t35 BUSY t36 SCLK t37 2 1 4 3 16 17 18 SDOUT X D17 D16 D15 D2 D1 D0 t16 Figure 39. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 25 of 28 04761-040 t32 AD7641 MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) The AD7641 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7641 is designed to interface with a parallel 8-bit or 16-bit wide interface or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7641 to prevent digital noise from coupling into the ADC. The SPI Interface (ADSP-219x) section illustrates the use of the AD7641 with the ADSP-219x SPI-equipped DSP. Figure 40 shows an interface diagram between the AD7641 and an SPI-equipped DSP, the ADSP-219x. To accommodate the slower speed of the DSP, the AD7641 acts as a slave device and data must be read after conversion. This mode also allows the daisy-chain feature. The convert command can be initiated in response to an internal timer interrupt. The 18-bit output data are read with three SPI byte access. The reading process can be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the DSP. The serial peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) = 00 by writing to the SPI control register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mb/s, allowing it to read an ADC result in less than 1 s. When a higher sampling rate is desired, it is recommended to use one of the parallel interface modes. DVDD AD7641 EXT/INT ADSP-219x1 BUSY CS SDOUT RD SCLK INVSCLK CNVST 1ADDITIONAL PFx SPIxSEL (PFx) MISOx SCKx PFx OR TFSx PINS OMITTED FOR CLARITY. Figure 40. Interfacing the AD7641 to ADSP-219x Rev. 0 | Page 26 of 28 04761-041 MODE0 MODE1 AD7641 APPLICATION HINTS LAYOUT While the AD7641 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the AD7641 so that the analog and digital sections are separated and confined to certain areas of the board. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7641, or as close as possible to the AD7641. If the AD7641 is in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the AD7641. To prevent coupling noise onto the die, to avoid radiating noise, and to reduce feedthrough: * Do not run digital lines under the device. * Run the analog ground plane under the AD7641. * Shield fast switching signals, like CNVST or clocks, with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. * Avoid crossover of digital and analog signals. * Run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. The power supply lines to the AD7641 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7641, and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 F capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD7641 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, and no separate supply is available, it is recommended to connect the DVDD digital supply to the analog supply AVDD through an RC filter, and to connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. Refer to Figure 23 for an example of this configuration. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7641 has four different ground pins: REFGND, AGND, DGND, and OGND. REFGND senses the reference voltage and, because it carries pulsed currents, should have a low impedance return to the reference. AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. To minimize parasitic inductances, place the decoupling capacitor close to the ADC and connect it with short, thick traces. EVALUATING THE AD7641 PERFORMANCE A recommended layout for the AD7641 is outlined in the documentation of the EVAL-AD7641-CB evaluation board for the AD7641. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVALCONTROL BRD3. Rev. 0 | Page 27 of 28 AD7641 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 PIN 1 7.00 BSC SQ TOP VIEW 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY SEATING PLANE (PINS DOWN) 25 12 13 24 0.27 0.22 0.17 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 41. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 12 MAX 48 PIN 1 INDICATOR 1 EXPOSED PAD 6.75 BSC SQ 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 25 24 13 12 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF PADDLE CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 42. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model AD7641BCPZ 1 AD7641BCPZRL1 AD7641BSTZ1 AD7641BSTZRL1 EVAL-AD7641CB 2 EVAL-CONTROLBRD3 3 1 2 3 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Low Profile Quad Flat Package (LQFP) 48-Lead Low Profile Quad Flat Package (LQFP) Evaluation Board Controller Board Package Option CP-48-1 CP-48-1 ST-48 ST-48 Z = Pb-free part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04761-0-1/06(0) Rev. 0 | Page 28 of 28