18-Bit, 2 MSPS SAR ADC
AD7641
Rev. 0
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Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Throughput
2 MSPS (wideband warp and warp mode)
1.5 MSPS (normal mode)
INL: ±2 LSB typical, ±3 LSB max; ±8 ppm of full scale
18-bit resolution with no missing codes
Dynamic range: 95.5 dB
SNR: 93.5 dB typical @ 20 kHz (VREF = 2.5 V)
THD: −112 dB typical @ 20 kHz (VREF = 2.5 V)
2.048 V internal reference: typ drift 10 ppm/°C; TEMP output
Differential input range: ±VREF (VREF up to 2.5 V)
No pipeline delay (SAR architecture)
Parallel (18-, 16-, or 8-bit bus) and
serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation
75 mW typical @ 2 MSPS with internal REF
2 μW in power-down mode
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Speed upgrade of the AD7674, AD7678, AD7679
APPLICATIONS
Medical instruments
High speed data acquisition/high dynamic data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
ATE
GENERAL DESCRIPTION
The AD7641 is an 18-bit, 2 MSPS, charge redistribution SAR,
fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. It features two
very high sampling rate modes (wideband warp and warp) and
a fast mode (normal) for asynchronous rate applications. The
AD7641 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7641 is available in Pb-free only packages with
operation specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
04761-001
18
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CLOCK
AD7641
DGNDD
V
DD
AVDD
AGND
REF REFGND
IN+
IN–
PD
RESET
CNVST
PDBUF
REFBUFIN
PDREF
REF
TEMP
D[17:0]
BUSY
RD
CS
D0/OB/2C
OGND
OVDD
MODE1
MODE0
REF AMP
NORMAL
SERIAL
PORT
PARALLEL
INTERFACE
SWITCHED
CAP DAC
WARP
Figure 1.
Table 1. PulSAR® Selection
Type/kSPS
100 to
250
500 to
570
650 to
1000 >1000
Pseudo
Differential
AD7651,
AD7660,
AD7661
AD7650,
AD7652,
AD7664,
AD7666
AD7653,
AD7667
True Bipolar AD7610,
AD7663
AD7665 AD7612,
AD7671
True
Differential
AD7675 AD7676 AD7677 AD7621,
AD7622,
AD7623
18-Bit
Multichannel/
AD7631,
AD7678
AD7679 AD7634,
AD7674
AD7641,
AD7643
Simultaneous AD7654 AD7655
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7641 is a 2 MSPS, charge redistribution,
18-bit SAR ADC.
2. Superior Linearity.
The AD7641 has no missing 18-bit code.
3. Internal Reference.
The AD7641 has a 2.048 V internal reference with a typical
-chip TEMP sensor.
drift of ±10 ppm/°C and an on
Single-Supply Operation. 4.
2.5 V single supply.
5. ace
arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.
The AD7641 operates from a
Serial or Parallel Interface.
Versatile parallel (16- or 8-bit bus) or 2-wire serial interf
AD7641
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Appplications Information............................................................ 15
Circuit Information....................................................................15
Converter Operation.................................................................. 15
Modes of Operation ................................................................... 15
Transfer Functions...................................................................... 16
Typical Connection Diagram........................................................ 17
Analog Inputs ............................................................................. 17
Multiplexed Inputs..................................................................... 17
Driver Amplifier Choice ........................................................... 17
Voltage Reference Input ............................................................ 18
Power Supply............................................................................... 20
Conversion Control ................................................................... 20
Interfaces.......................................................................................... 21
Digital Interface.......................................................................... 21
Parallel Interface......................................................................... 21
Serial interface ............................................................................ 22
Master Serial Interface............................................................... 22
Slave Serial Interface.................................................................. 24
Microprocessor Interfacing....................................................... 26
Application Hints ........................................................................... 27
Layout .......................................................................................... 27
Evaluating the AD7641 Performance...................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
1/06—Revision 0: Initial Version
AD7641
Rev. 0 | Page 3 of 28
SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 18 Bits
ANALOG INPUT
Voltage Range VIN+VIN −VREF +VREF V
Operating Input Voltage VIN+, VIN− to AGND −0.1 AVDD1V
Analog Input CMRR fIN = 100 kHz 58 dB
Input Current 2 MSPS throughput 18 μA
Input Impedance2
THROUGHPUT SPEED
Complete Cycle Wideband warp, warp modes 500 ns
Throughput Rate Wideband warp, warp modes 0.001 2 MSPS
Time Between Conversions Wideband warp, warp modes 1 ms
Complete Cycle Normal mode 667 ns
Throughput Rate Normal mode 0 1.5 MSPS
DC ACCURACY
Integral Linearity Error3TMIN to TMAX = −40°C to +70°C −3 ±2 +3 LSB4
Integral Linearity Error TMIN to TMAX = −40°C to +85°C −3.5 ±2 +3.5 LSB4
No Missing Codes 18 Bits
Differential Linearity Error −1 +2 LSB
Transition Noise VREF = 2.5 V 1.6 LSB
Transition Noise VREF = 2.048 V 2.0 LSB
Zero Error, TMIN to TMAX5 −15 +15 LSB
Zero Error Temperature Drift ±0.5 ppm/°C
Gain Error, TMIN to TMAX5 −0.25 +0.25 % of FSR
Gain Error Temperature Drift ±1 ppm/°C
Power Supply Sensitivity AVDD = 2.5 V ± 5% ±16 LSB
AC ACCURACY
Dynamic Range VREF = 2.5 V 95.5 dB6
Signal-to-Noise fIN = 20 kHz, VREF = 2.5 V 93.5 dB
f
IN = 20 kHz, VREF = 2.048 V 92 dB
f
IN = 100 kHz, VREF = 2.5 V 93 dB
Spurious-Free Dynamic Range fIN = 20 kHz, VREF = 2.5 V 112 dB
f
IN = 20 kHz, VREF = 2.048 V 113 dB
f
IN = 100 kHz, VREF = 2.5 V 101 dB
Total Harmonic Distortion fIN = 20 kHz, VREF = 2.5 V −115 dB
f
IN = 20 kHz, VREF = 2.048 V −116 dB
f
IN = 100 kHz, VREF = 2.5 V −101 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, , VREF = 2.5 V 93.5 dB
f
IN = 20 kHz, VREF = 2.048 V 92 dB
f
IN = 100 kHz, , VREF = 2.5 V 92.5 dB
−3 dB Input Bandwidth 50 MHz
SAMPLING DYNAMICS
Aperture Delay 1 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 115 ns
INTERNAL REFERENCE PDREF = PDBUF = low
Output Voltage REF @ 25°C 2.038 2.048 2.058 V
Temperature Drift −40°C to +85°C ±10 ppm/°C
Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V
AD7641
Rev. 0 | Page 4 of 28
Parameter Conditions Min Typ Max Unit
Turn-On Settling Time CREF = 10 μF 5 ms
REFBUFIN Output Voltage REFBUFIN @ 25°C 1.19 V
REFBUFIN Output Resistance 6.33
EXTERNAL REFERENCE PDREF = PDBUF = high
Voltage Range REF 1.8 2.048 AVDD + 0.1 V
Current Drain 2 MSPS throughput 180 μA
REFERENCE BUFFER PDREF = high, PDBUF = low
REFBUFIN Input Voltage Range REF = 2.048 V typ 1.05 1.2 1.30 V
REFBUFIN Input Current REFBUFIN = 1.2 V 1 nA
TEMPERATURE PIN
Voltage Output @ 25°C 278 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.7
DIGITAL INPUTS
Logic Levels
VIL −0.3 +0.6 V
VIH 1.7 5.25 V
IIL −1 +1 μA
IIH −1 +1 μA
DIGITAL OUTPUTS
Data Format7
Pipeline Delay8
VOL I
SINK = 500 μA 0.4 V
VOH I
SOURCE = −500 μA OVDD − 0.3 V
POWER SUPPLIES
Specified Performance
AVDD 2.37 2.5 2.63 V
DVDD 2.37 2.5 2.63 V
OVDD 2.309 3.6 V
Operating Current10 2 MSPS throughput
AVDD11 With internal reference 23 mA
DVDD 2.5 mA
OVDD12 0.5 mA
Power Dissipation11
With Internal Reference10 2 MSPS throughput 75 92 mW
Without Internal Reference10 2 MSPS throughput 68 85 mW
In Power-Down Mode12 PD = high 2 μW
TEMPERATURE RANGE13
Specified Performance TMIN to TMAX −40 +85 °C
1 When using an external reference. With the internal reference, the input range is −0.1 V to VREF.
2 See Analog Inputs section.
3 Linearity is tested using endnotes, not best fit.
4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 15.63 μV.
5 See Voltage Reference Input section. These specifications do not include the error contribution from the external reference.
6 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
7 Parallel or serial 18-bit.
8 Conversion results are available immediately after completed conversion.
9 See the Absolute Maximum Ratings section.
10 In warp mode. Tested in parallel reading mode.
11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.
12 With all digital inputs forced to OVDD.
13Consult sales for extended temperature range.
AD7641
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 29 and Figure 30)
Convert Pulse Width t1 15 701ns
Time Between Conversions (Warp Mode2/Normal Mode3) t2 500/667 ns
CNVST Low to BUSY High Delay t3 23 ns
BUSY High All Modes (Except Master Serial Read After Convert) t4 385/520 ns
Aperture Delay t5 1 ns
End of Conversion to BUSY Low Delay t6 10 ns
Conversion Time (Warp Mode/Normal Mode) t7 385/520 ns
Acquisition Time (Warp Mode/Normal Mode) t8 115 ns
RESET Pulse Width t9 15 ns
RESET Low to BUSY High Delay4t38 10 ns
BUSY High Time from RESET Low4t39 600 ns
PARALLEL INTERFACE MODES (Refer to Figure 31 to Figure 34 )
CNVST Low to Data Valid Delay (Warp Mode/Normal Mode) t10 385/520 ns
Data Valid to BUSY Low Delay t11 2 ns
Bus Access Request to Data Valid t12 20 ns
Bus Relinquish Time t13 2 15 ns
MASTER SERIAL INTERFACE MODES5 (Refer to Figure 35 and Figure 36)
CS Low to SYNC Valid Delay t14 10 ns
CS Low to Internal SCLK Valid Delay5t15 10 ns
CS Low to SDOUT Delay t16 10 ns
CNVST Low to SYNC Delay (Warp Mode/Normal Mode) t17 14/137 ns
SYNC Asserted to SCLK First Edge Delay t18 0.5 ns
Internal SCLK Period6t19 8 14 ns
Internal SCLK High6t20 2 ns
Internal SCLK Low6t21 3 ns
SDOUT Valid Setup Time6t22 1 ns
SDOUT Valid Hold Time6t23 0 ns
SCLK Last Edge to SYNC Delay6t24 0 ns
CS High to SYNC HI-Z t25 10 ns
CS High to Internal SCLK HI-Z t26 10 ns
CS High to SDOUT HI-Z t27 10 ns
BUSY High in Master Serial Read After Convert6t28 See Table 4 ns
CNVST Low to SYNC Asserted Delay (All Modes) t29 383/500 ns
SYNC Deasserted to BUSY Low Delay t30 13 ns
SLAVE SERIAL INTERFACE MODES (Refer to Figure 38 and Figure 39)
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 1 8 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 12.5 ns
External SCLK High t36 5 ns
External SCLK Low t37 5 ns
1 See the Conversion Control section.
2 All timings for wideband warp mode are the same as warp mode.
3 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
4 See the Digital Interface section and the RESET section.
5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
AD7641
Rev. 0 | Page 6 of 28
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 0.5 3 3 3 ns
Internal SCLK Period Minimum t19 8 16 32 64 ns
Internal SCLK Period Maximum t19 14 26 52 103 ns
Internal SCLK High Minimum t20 2 6 15 31 ns
Internal SCLK Low Minimum t21 3 7 16 32 ns
SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns
SDOUT Valid Hold Time Minimum t23 0 0.5 10 28 ns
SCLK Last Edge to SYNC Delay Minimum t24 0 0.5 9 26 ns
BUSY High Width Maximum t24 0.630 0.870 1.350 2.28 μs
04761-002
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
500µAI
OL
500µAI
OH
1.4V
TO OUTPUT
PIN C
L
50pF
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
t
DELAY
t
DELAY
04761-003
Figure 3. Voltage Reference Levels for Timing
AD7641
Rev. 0 | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs/Outputs
IN+1, IN−, REF, REFBUFIN, TEMP,
INGND, REFGND to AGND
AVDD + 0.3 V to
AGND − 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD −0.3 V to +2.7 V
OVDD −0.3 V to +3.8 V
AVDD to DVDD ±2.8 V
AVDD, DVDD to OVDD −3.8 V to +2.8 V
Digital Inputs −0.3 V to +5.5 V
PDREF, PDBUF2±20 mA
Internal Power Dissipation3700 mW
Internal Power Dissipation42.5 W
Junction Temperature 125°C
Storage Temperature Range –65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1 See Analog Inputs section.
2 See Voltage Reference Input section.
3 Specification is for the device in free air:
48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W.
4 Specification is for the device in free air:
48-Lead LFCSP; θJA = 26°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7641
Rev. 0 | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
MODE0
MODE1
D0/OB/2C
NC = NO CONNECT
D1/A0
D2/A1
D3
D4/DIVSCLK[0]
BUSY
D17
D16
D15
AD7641
D5/DIVSCLK[1] D14
D6/EXT/INT
D7/INVSYNC
D8/INVSCLK
D9/RDC/SDIN
OGND
OVDD
DVDD
DGND
D10/SDOUT
D11/SCLK
D12/SYNC
D13/RDERROR
PDBUF
PDREF
REFBUFIN
TEMP
AVDD
IN+
AGND
AGND
NC
IN
REFGND
REF
WARP
04761-004
NORMAL
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin
No. Mnemonic Type1Description
1, 36,
41, 42
AGND P Analog Power Ground Pin.
2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V.
3, 4 MODE[0:1] DI Data Output Interface Mode Selection.
Interface MODE# MODE1 MODE0 Description
0 0 0 18-bit interface
1 0 1 16-bit interface
2 1 0 8-bit (byte) interface
3 1 1 Serial interface
5 D0/OB/2C DI/O When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus
and the data coding is straight binary. In all other modes, this pin allows the choice of straight
binary/twos complement. When OB/2C is high, the digital output is straight binary; when low,
the MSB is inverted resulting in a twos complement output from its internal shift register.
6 WARP DI
Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp
mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects
warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and
a minimum conversion rate must be applied to guarantee full specified accuracy.
7 NORMAL DI Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode
where full accuracy is maintained independent of the minimum conversion rate.
8 D1/A0 DI/O
When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this
input pin controls the form in which data is output as shown in Table 7.
9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus.
When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7.
10 D3 D0 When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.
This pin is always an output, regardless of the interface mode.
11, 12 D[4:5] DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
or DIVSCLK[0:1] When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read
after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the
internally generated serial clock that clocks the data output. In other serial modes, these pins are
high impedance outputs.
AD7641
Rev. 0 | Page 9 of 28
Pin
No. Mnemonic Type1Description
13 D6 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.
or EXT/INT When MODE[1:0] = 3, (serial mode), serial clock source select. This input is used to select the
internally generated (master) or external (slave) serial data clock.
When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output.
When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal,
gated by CS, connected to the SCLK input.
14 D7 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.
or INVSYNC When MODE[1:0] = 3, (serial mode), invert sync select. In serial master mode (EXT/INT = low), this
input is used to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15 D8 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.
or INVSCLK When MODE[1:0] = 3, (serial mode), invert SCLK select. In all serial modes, this input is used to
invert the SCLK signal.
16 D9 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus.
or RDC When MODE[1:0] = 3, (serial mode), read during convert. When using serial master mode
(EXT/INT = low), RDC is used to select the read mode.
When RDC = high, the previous conversion result is output on SDOUT during conversion and
the period of SCLK changes (see the Master Serial Interface section).
When RDC = low (read after convert), the current result can be output on SDOUT only when
the conversion is complete.
or SDIN When MODE[1:0] = 3, (serial mode), serial data in. When using serial slave mode, (EXT/INT = high),
SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the
host interface (2.5 V or 3 V).
19 DVDD P Digital Power. Nominally at 2.5 V.
20 DGND P Digital Power Ground.
21 D10 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.
or SDOUT When MODE[1:0] = 3, (serial mode), serial data output. In serial mode, this pin is used as the serial
data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7641
provides the conversion result, MSB first, from its internal shift register. The data format is
determined by the logic level of OB/2C.
In master mode, EXT/INT = low. SDOUT is valid on both edges of SCLK.
In slave mode, EXT/INT = high:
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
22 D11 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.
or SCLK When MODE[1:0] = 3, (serial mode), serial clock. In all serial modes, this pin is used as the serial
data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge
where the data SDOUT is updated depends on the logic state of the INVSCLK pin.
23 D12 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
or SYNC When MODE[1:0] = 3, (serial mode), frame synchronization. In serial master mode (EXT/INT= low),
this output is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high
while SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low
while SDOUT output is valid.
24 D13 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
or RDERROR When MODE[1:0] = 3, (serial mode), read error. In serial slave mode (EXT/INT = high), this output
is used as an incomplete read error flag. If a data read is started and not completed when the
current conversion is complete, the current data is lost and RDERROR is pulsed high.
AD7641
Rev. 0 | Page 10 of 28
Pin
No. Mnemonic Type1Description
25 to
28
D[14:17] DO
Bit 14 to Bit 17 of the parallel port data output bus. These pins are always outputs, regardless of
the interface mode.
29 BUSY DO
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
30 DGND P Digital Power Ground.
31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.
CS is also used to gate the external clock in slave serial mode.
33 RESET DI Reset Input. When high, resets the AD7641. Current conversion, if any, is aborted. Falling edge of
RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface
section. If not used, this pin can be tied to DGND.
34 PD DI Power-Down Input. When high, power downs the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion.
37 REF AI/O Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the Voltage Reference Input section.
38 REFGND AI Reference Input Analog Ground.
39 IN− AI Differential Negative Analog Input.
40 NC No Connect.
43 IN+ AI Differential Positive Analog Input.
45 TEMP AO Temperature Sensor Analog Output.
46 REFBUFIN AI/O Internal Reference Output/Reference Buffer Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical)
band gap output on this pin, which needs external decoupling. The internal fixed gain reference
buffer uses this to produce 2.048 V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
47 PDREF DI Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.
48 PDBUF DI Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
Table 7. Data Bus Interface Definition
MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description
0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel
1 0 1 OB/2C A0 = 0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word
1 0 1 OB/2C A0 = 1 R[0] R[1] All Zeros 16-Bit Low Word
2 1 0 OB/2C A0 = 0 A1 = 0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit High Byte
2 1 0 OB/2C A0 = 0 A1 = 1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit Mid Byte
2 1 0 OB/2C A0 = 1 A1 = 0 All Hi-Z R[0:1] All Zeros 8-Bit Low Byte
2 1 0 OB/2C A0 = 1 A1 = 1 All Hi-Z All Zeros R[0:1] 8-Bit Low Byte
3 1 1 OB/2C All Hi-Z Serial Interface Serial Interface
AD7641
Rev. 0 | Page 11 of 28
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Gain Error
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal negative full scale
(−2.0479922 V for the ±2.048 V range). The last transition
(from 111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (+2.0479766 V for the
±2.048 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
Zero Error
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
Dynamic Range
It is the ratio of the rms value of the full scale to the rms noise
measured with the inputs shorted together. The value for
dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal to (Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transi ent Response
The time required for the AD7641 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
It is derived from the typical shift of output voltage at 25°C on a
sample of parts maximum and minimum reference output
voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is
expressed in ppm/°C using
()
()
(
)
()
()
6
10
C25
Cppm/ ×
×°
=°
M
IN
M
A
X
REF
REFREF
REF TTV
MinVMaxV
TCV
where:
VREF (Max) = Maximum VREF at TMIN, T(25°C), or TMAX
VREF (Min) = Minimum VREF at TMIN, T(25°C), or TMAX
VREF (25°C) = VREF at 25°C
TMAX = +85°C
TMIN = –40°C
AD7641
Rev. 0 | Page 12 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
2.0
–3.0
–2.5
0 262144
CODE
INL (LSB)
04761-005
1.5
1.0
0.5
0
–0.5
–1.0
–2.0
–1.5
65536 131072 196608
Figure 5. Integral Nonlinearity vs. Code
40000
0
00 0392322
11 683
272
1FFEF
1FFF0
1FFF1
1FFF2
1FFF3
1FFF4
1FFF5
1FFF6
1FFF7
1FFF8
1FFF9
1FFFA
1FFFB
1FFFC
1FFFD
1FFFE
1FFFF
20000
04761-006
CODE IN HEX
COUNTS
35000
30000
25000
20000
15000
10000
5000
0
34844
31003
24739
16207
5248
2124
10938
4730
σ = 1.55
Figure 6. Histogram of 261,120 Conversions of a DC Input at
the Code Center (External Reference)
2.0530
2.0480
–55 125
04761-007
TEMPERATURE (°C)
V
REF
(V)
2.0525
2.0520
2.0515
2.0510
2.0505
2.0500
2.0495
2.0490
2.0485
–35 –15 5 25 45 65 85 105
Figure 7. Typical Reference Voltage Output vs. Temperature (3 Units)
2.0
–2.0
0 262144
CODE
DNL (LSB)
04761-008
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
65536 131072 196608
Figure 8. Differential Nonlinearity vs. Code
30000
0
1FED9
1FEDB
1FEDD
1FEDF
1FEE1
1FEE3
1FEE5
1FEE7
1FEE9
1FEEB
1FEDA
1FEDC
1FEDE
1FEE0
1FEE2
1FEE4
1FEE6
1FEE8
1FEEA
04761-009
CODE IN HEX
COUNTS
25000
20000
15000
10000
5000
11
52 117
912
2105
10846
12922
22225
24731
23436
18995
8219
4688
1171
58951 10 1
σ = 2.02
Figure 9. Histogram of 261,120 Conversions of a DC Input at
the Code Center (Internal Reference)
20
–20
–55 125
04761-010
TEMPERATURE (°C)
ZERO-ERROR, FULL-SCALE ERROR (LSB)
18
16
14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–35 –15 5 25 45 65 85 105
ZERO-ERROR
–FS
+FS
Figure 10. Zero Error, Positive and Negative Full Scale vs. Temperature
AD7641
Rev. 0 | Page 13 of 28
FREQUENCY (kHz)
AMPLITUDE (dB of Full Scale)
0
–180
01
000
04761-011
–20
–40
–60
–80
–100
–120
–140
–160
100 200 300 400 500 600 700 800 900
f
S
= 2MSPS
f
IN
= 20.1kHz
SNR = 93.6dB
THD = –116dB
SFDR = 112dB
SINAD = 93.5dB
0
–180
01000
FREQUENCY (kHz)
AMPLITUDE (dB of Full Scale)
Figure 11. FFT 20 kHz
95
75
1 1000
FREQUENCY (kHz)
SNR, SINAD (dB)
ENOB (Bits)
04761-012
93
91
89
87
85
83
81
79
77
16.0
12.0
15.6
15.2
14.8
14.4
14.0
13.6
13.2
12.8
12.4
10
ENOB SINAD SNR
100
Figure 12. SNR, SINAD, and ENOB vs. Frequency
70
–140
1 1000
FREQUENCY (kHz)
THD, HARMONICS (dB)
SFDR (dB)
04761-013
–80
–90
–100
–110
–120
–130
120
20
110
100
90
80
70
60
50
40
30
10 100
SFDR
THD
THIRD
HARMONIC
SECOND
HARMONIC
Figure 13. THD, Harmonics, and SFDR vs. Frequency
04761-014
f
S
= 2MSPS
f
IN
= 100.8kHz
SNR = 93dB
THD = –101dB
SFDR = 101dB
SINAD = 92.5dB
–20
–40
–60
–80
–100
–120
–140
–160
100 200 300 400 500 600 700 800 900
Figure 14. FFT 100 kHz
95
90
–55 125
TEMPERATURE (°C)
SNR, SINAD (dB)
04761-015
94
93
92
91
19
14
ENOB (Bits)
18
17
16
15
–35 –15 5 25 45 65 85 105
SNR
ENOB
SINAD
Figure 15. SNR, SINAD, and ENOB vs. Temperature
90
–140
–55 125
TEMPERATURE (°C)
THD, HARMONICS (dB)
04761-016
–95
–100
–105
–110
–115
–120
–125
–130
–135
120
70
SFDR (dB)
115
110
105
100
95
90
85
80
75
–35 –15 5 25 45 65 85 105
SFDR
THD
THIRD
HARMONIC
SECOND
HARMONIC
Figure 16. THD, Harmonics, and SFDR vs. Temperature
AD7641
Rev. 0 | Page 14 of 28
96.0
93.0
–60 0
INPUT LEVEL (dB)
SNR, SINAD REFERRED TO FULL SCALE (dB)
04761-017
95.5
95.0
94.5
94.0
93.5
–50 –40 –30 –20 –10
SNR
SINAD
Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale)
16
0
–55 125
TEMPERATURE (°C)
DVDD, OVDD (µA)
04761-018
14
12
10
8
6
4
2
–35 –15 5 25 45 65 85 105
DVDD
OVDD, 3.3V
OVDD, 2.5V
AVDD
Figure 18. Power-Down Operating Currents vs. Temperature
100000
0.01
10 10M
SAMPLING RATE (SPS)
OPERATING CURRENTS (µA)
04761-019
100 1k 10k 100k 1M
0.1
1
10
100
1000
10000
AVDD
DVDD
OVDD = 2.5V, ALL MODES
OVDD = 3.3V, ALL MODES
PDREF = PDBUF = HIGH
Figure 19. Operating Current vs. Sample Rate
20
4
4
04761-020
CL (pF)
t
12 DELAY (ns)
18
16
14
12
10
8
6
50 100 150 200
OVDD = 2.5V @ 85°C
OVDD = 3.3V @ 85°C
OVDD = 3.3V @ 25°C
OVDD = 2.5V @ 25°C
Figure 20. Typical Delay vs. Load Capacitance CL
AD7641
Rev. 0 | Page 15 of 28
APPPLICATIONS INFORMATION
SW+
COMP
SW–
IN+
REF
REFGND
LSB
MSB
131,072C 65,536C 4C 2C C C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
IN–
4C 2C C C
LSB
MSB
AGND
AGND
131,072C 65,536C
04761-021
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7641 is a very fast, low power, single-supply, precise
18-bit ADC using successive approximation architecture. The
AD7641 features different modes to optimize performances
according to the applications. In warp mode, the AD7641 is
capable of converting 2,000,000 samples per second (2 MSPS).
The AD7641 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7641 can operate from a single 2.5 V supply and
interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed
in a 48-lead LQFP package or a tiny 48-lead LFCSP package,
which combines space savings with flexibility and allows the
AD7641 to be configured as either a serial or a parallel
interface. The AD7641 is pin-to-pin-compatible and is a
speed upgrade of the AD7674, AD7678, and AD7679.
CONVERTER OPERATION
The AD7641 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors that are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. A
conversion phase is initiated once the acquisition phase is complete
and the CNVST input goes low. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
the inputs (IN+ and IN−) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the comparator
input varies by binary weighted voltage steps (VREF/2, VREF/4
throughVREF/131072). The control logic toggles these switches,
starting with the MSB first, to bring the comparator back into a
balanced condition. After the completion of this process, the
control logic generates the ADC output code and brings BUSY
output low.
MODES OF OPERATION
The AD7641 features three modes of operations: wideband
warp, warp, and normal. Each of these modes is more suitable
for specific applications.
The wideband warp (WARP = high, NORMAL = high) and
warp (WARP = high, NORMAL = low) modes allow the fastest
conversion rate of up to 2 MSPS. However, in these modes, the
full specified accuracy is guaranteed only when the time between
conversions does not exceed 1 ms. If the time between two
consecutive conversions is longer than 1 ms (for instance after
power-up), the first conversion result should be ignored. These
modes make the AD7641 ideal for applications where both high
accuracy and fast sample rates are required. Wideband warp
mode offers slightly improved linearity and THD over warp mode.
Normal mode (NORMAL = low, WARP = low) is the fastest
mode (1.5 MSPS) without any limitation on time between
conversions. This mode makes the AD7641 ideal for
asynchronous applications, such as data acquisition systems,
where both high accuracy and fast sample rates are required.
AD7641
Rev. 0 | Page 16 of 28
TRANSFER FUNCTIONS
Using the OB/2C digital input, except in 18-bit interface mode,
the AD7641 offers two output codings: straight binary and twos
complement. The LSB size with VREF = 2.048 V is 2 × VREF/
262,144, which is 15.623 μV. Refer to Figure 22 and Table 8 for
the ideal transfer characteristic.
04761-022
000...000
000...001
000...010
111. ..101
111...110
111. ..111
ADC CODE (Straight Binary)
ANALOG INPUT
+FSR – 1.5 LSB
+FSR – 1 LSB–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
Figure 22. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Digital Output Code (Hex)
Description
Analog Input
VREF = 2.048 V
Straight
Binary
Twos
Complement
FSR −1 LSB +2.0479844 V 0x3FFFF10x1FFFF1
FSR − 2 LSB +2.0479688 V 0x3FFFE 0x1FFFE
Midscale + 1 LSB +15.625 μV 0x20001 0x00001
Midscale 0 V 0x20000 0x00000
Midscale − 1 LSB −15.625 μV 0x1FFFF 0x3FFFF
−FSR + 1 LSB −2.0479844 V 0x30001 0x20001
−FSR −2.048 V 0x30000 0x20000
2 2
1 This is also the code for overrange analog input (VIN+ − VIN− above
+VREF − VREFGND).
2 This is also the code for underrange analog input (VIN+ − VIN− below
−VREF + VREFGND).
04761-023
RD
CS
100nF 100nF
AVDD
10µF 100nF
AGND DGND DVDD OVDD OGND
CNVST
BUSY
SDOUT
SCLK
RESET
PD
REFBUFIN
10
D
CLOCK
AD7641
MICROCONVERTER/
MICROPROCESSOR/
DSP
SERIAL
PORT
DIGITAL
INTERFACE
SUPPLY
(2.5V OR 3.3V)
ANALOG
SUPPLY (2.5V)
OVDD
WARP
DIGIT
A
L
SUPPLY (2.5V)
IN+
IN–
U2
15
NOTE 5
50
50pF
NOTE 1
ANALOG
INPUT +
C
C
C
C
2.7nF
2.7nF
U1
15
NOTE 1
MODE0
MODE1
D0/OB/2C
REFGND
REF
PDBUF
PDREF
100nF
ANALOG
INPUT
NOTE 2
NOTE 2
NOTE 3
NOTE 4
NOTE 3
NOTE 7
NOTE 6
NORMAL
10µF
10µF
C
REF
10µF
10k
50pF
1. SEE ANALOG INPUTS SECTION.
2
. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3
. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION.
4
. A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ3YB0J106M).
SEE VOLTAGE REFERENCE INPUT SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
6. OPTION, SEE POWER-UP SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
Figure 23. Typical Connection Diagram
AD7641
Rev. 0 | Page 17 of 28
TYPICAL CONNECTION DIAGRAM
Figure 23 shows a typical connection diagram for the AD7641.
Different circuitry shown in this diagram is optional and is
discussed in the following sections.
ANALOG INPUTS
Figure 24 shows an equivalent circuit of the input structure of
the AD7641.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes the diodes to become forward-
biased and start conducting current. These diodes can handle a
forward-biased current of 100 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
U1 or U2 supplies are different from AVDD. In such a case, an
input buffer with a short-circuit current limitation can be used
to protect the part.
0
4761-024
D
1
R
IN
C
IN
D
2
IN+ OR IN–
AGND
V
DD
C
PIN
Figure 24. AD7641 Simplified Analog Input
The analog input of the AD7641 is a true differential structure.
By using this differential input, small signals common to both
inputs are rejected, as shown in Figure 25, representing the
typical CMRR over frequency with internal and external references.
65
45
1 10000
FREQUENCY (kHz)
CMRR (dB)
04761-025
10 100 1000
60
55
50
INT REF
EXT REF
Figure 25. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the impedance of
the analog inputs, IN+ and IN−, can be modeled as a parallel
combination of capacitor CPIN and the network formed by the
series connection of RIN and CIN. CPIN is primarily the pin
capacitance. RIN is typically 175 Ω and is a lumped component
comprised of some serial resistors and the on resistance of the
switches. CIN is typically 12 pF and is mainly the ADC sampling
capacitor. During the conversion phase, when the switches are
opened, the input impedance is limited to CPIN. RIN and CIN
make a 1-pole, low-pass filter that has a typical −3 dB cutoff
frequency of 50 MHz, thereby reducing an undesirable aliasing
effect and limiting the noise coming from the inputs.
Because the input impedance of the AD7641 is very high, the
AD7641 can be directly driven by a low impedance source
without gain error. To further improve the noise filtering achieved
by the AD7641 analog input circuit, an external 1-pole RC filter
between the amplifier’s outputs and the ADC analog inputs can
be used, as shown in Figure 23. However, large source impedances
significantly affect the ac performance, especially the total
harmonic distortion (THD). The maximum source impedance
depends on the amount of THD that can be tolerated. The THD
degrades as a function of the source impedance and the maximum
input frequency.
MULTIPLEXED INPUTS
When using the full 2 MSPS throughput in multiplexed
applications for a full-scale step, the RC filter, as shown in
Figure 23, does not settle in the required acquisition time, t8.
These values are chosen to optimize the best SNR perform-ance
of the AD7641. To use the full 2 MSPS throughput in
multiplexed applicaitons, the RC should be adjusted to satisfy t8
(which is ~ 8.5 × RC time constant). However, lowering R and C
increases the RC filter bandwidth and allows more noise into the
AD7641, which degrades SNR. To preserve the SNR performance
in these applications using the RC filter shown in Figure 23,
the AD7641 should be run with t8 > 350 ns; or approximately
1/(t7 + t8) ~ 1.35 MSPS in wideband and warp modes.
DRIVER AMPLIFIER CHOICE
Although the AD7641 is easy to drive, the driver amplifier
needs to meet the following requirements:
For multichannel, multiplexed applications, the driver
amplifier and the AD7641 analog input circuit must be
able to settle for a full-scale step of the capacitor array at an
18-bit level (0.0004%). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 18-bit level
and should be verified prior to driver selection. The
AD8021 op amp, which combines ultralow noise and high
gain bandwidth, meets this settling time requirement even
when used with gains up to 13.
AD7641
Rev. 0 | Page 18 of 28
Single-to-Differential Driver
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7641. The noise coming from
the driver is filtered by the AD7641 analog input circuit
1-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. The SNR degradation due
to the amplifier is
For applications using unipolar analog signals, a single-ended-
to-differential driver, as shown in Figure 26, allows for a
differential input into the part. This configuration, when
provided an input signal of 0 to VREF, produces a differential
±VREF with midscale at VREF/2. The 1-pole filter using R = 10 Ω
and C = 1 nF provides a corner frequency of 16 MHz.
() ()
++
=
+
22
2
π
2
π
900
30
20log
N
3dB
N
3dB
LOSS
Ne
f
Ne
f
SNR
If the application can tolerate more noise, the AD8139
differential driver can be used.
0
4761-027
AD8021
ANALOG INPUT
(
UNIPOLAR 0
V
TO 2.048V)
AD8021
IN+
IN–
AD7641
REF
10µF
15
15
100nF
2.7nF
2.7nF
U2
U1
10pF
10pF
5k
5k
590
590
where:
f–3dB is the input bandwidth of the AD7641 (50 MHz) or
the cutoff frequency of the input RC filter shown in Figure 23
(3.9 MHz), if one is used.
N is the noise factor of the amplifier (1 in buffer
configuration).
eN+ and eN− are the equivalent input voltage noise densities
of the op amps connected to IN+ and IN−, in nV/√Hz.
This approximation can be used when the resistances used
around the amplifier are small. If larger resistances are
used, their noise contributions should also be root-sum
squared.
Figure 26. Single-Ended-to-Differential Driver Circuit
(Internal Reference Buffer Used)
VOLTAGE REFERENCE INPUT
The AD7641 allows the choice of either a very low temperature
drift internal voltage reference or an external reference.
For instance, when using op amps with an equivalent input
noise density of 2.1 nV/√Hz, such as the AD8021, with a
noise gain of 1 when configured as a buffer, degrades the
SNR by only 0.25 dB when using the RC filter in
Unlike many ADCs with internal references, the internal
reference of the AD7641 provides excellent performance and
can be used in almost all applications.
Figure 23,
and by 2.5 dB without it.
Internal Reference (PDBUF = Low, PDREF = Low)
The driver needs to have a THD performance suitable to
that of the AD7641. Figure 13 gives the THD vs. frequency
that the driver should exceed.
To use the internal reference, the PDREF and PDBUF inputs
must both be low. This produces a 1.2 V band gap output on
REFBUFIN, which is amplified by the internal buffer and
results in a 2.048 V reference on the REF pin.
The AD8021 meets these requirements and is appropriate for
almost all applications. The AD8021 needs a 10 pF external
compensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.
The internal reference is temperature compensated to 2.048 V ±
10 mV. The reference is trimmed to provide a typical drift of
10 ppm/°C. This typical drift characteristic is shown in Figure 7.
The output resistance of REFBUFIN is 6.33 kΩ (minimum)
when the internal reference is enabled. It is necessary to
decouple this with a ceramic capacitor greater than 100 nF.
Therefore, the capacitor provides an RC filter for noise reduction.
The AD8022 can also be used when a dual version is needed
and a gain of 1 is present. The AD829 is an alternative in
applications where high frequency (above 100 kHz) performance is
not required. In applications with a gain of 1, an 82 pF
compensation capacitor is required. The Because the output impedance of REFBUFIN is typically
6.33 kΩ, relative humidity (among other industrial contaminates)
can directly affect the drift characteristics of the reference.
Typically, a guard ring is used to reduce the effects of drift
under such circumstances.
AD8610 is an option
when low bias current is needed in low frequency applications.
AD7641
Rev. 0 | Page 19 of 28
However, because the AD7641 has a fine lead pitch, guarding
this node is not practical. Therefore, in these industrial and
other types of applications, it is recommended to use a conformal
coating, such as Dow Corning® 1-2577 or HumiSeal® 1B73.
For applications that use multiple AD7641 devices, it is more
effective to use an external reference with the internal reference
buffer to buffer the reference voltage. However, because the
reference buffers are not unity gain, ratiometric, simultaneously
sampled designs should use an external reference and external
buffer, such as the
External 1.2 V Reference and Internal Buffer (PDBUF =
Low, PDREF = High) AD8031/AD8032; therefore, preserving the
same reference level for all converters.
To use an external reference along with the internal buffer,
PDREF should be high and PDBUF should be low. This powers
down the internal reference and allows the 1.2 V reference to
be applied to REFBUFIN, producing 2.048 V (typically) on
the REF pin.
The voltage reference temperature coefficient (TC) directly
impacts full scale; therefore, in applications where full-scale
accuracy matters, care must be taken with the TC. For instance,
a ±4 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.
External 2.5 V Reference (PDBUF = High, PDREF = High) Note that VREF can be increased to AVDD + 0.1 V. Because the
input range is defined in terms of VREF, this would essentially
increase the range to 0 V to 2.8 V with an AVDD = 2.7 V.
To use an external 2.5 V reference directly on the REF pin,
PDREF and PDBUF should both be high.
For improved drift performance, an external reference, such as
the Temperature Sensor
AD780 or ADR431, can be used. The advantages of directly
using the external voltage reference are: The TEMP pin measures the temperature of the AD7641. To
improve the calibration accuracy over the temperature range,
the output of the TEMP pin is applied to one of the inputs of
the analog switch (such as,
The SNR and dynamic range improvement (about 1.7 dB)
resulting from the use of a reference voltage very close to
the supply (2.5 V) instead of a typical 2.048 V reference
when the internal reference is used. This is calculated by
ADG779), and the ADC itself is
used to measure its own temperature. This configuration is
shown in Figure 27.
=50.2
048.2
log20SNR
04761-028
ADG779
AD8021 C
C
ANALOG INPUT
(UNIPOLAR)
AD7641
IN+ TEMPERATURE
SENSOR
TEMP
The power savings when the internal reference is powered
down (PDREF high).
PDREF and PDBUF power down the internal reference and
the internal reference buffer, respectively. The input current
of PDREF and PDBUF should never exceed 20 mA. This can
occur when the driving voltage is above AVDD (for instance, at
power-up). In this case, a 125 Ω series resistor is recommended.
Figure 27. Use of the Temperature Sensor
Reference Decoupling
Whether using an internal or external reference, the AD7641
voltage reference input (REF) has a dynamic input impedance;
therefore, it should be driven by a low impedance source with
efficient decoupling between the REF and REFGND inputs.
This decoupling depends on the choice of the voltage reference
but usually consists of a low ESR capacitor connected to REF
and REFGND with minimum parasitic inductance. A 10 μF
(X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum
capacitor) is appropriate when using either the internal
reference or one of the recommended reference voltages.
The placement of the reference decoupling is also important to
the performance of the AD7641. The decoupling capacitor
should be mounted on the same side as the ADC right at the
REF pin with a thick PCB trace. The REFGND should also connect
to the reference decoupling capacitor with the shortest distance.
AD7641
Rev. 0 | Page 20 of 28
POWER SUPPLY It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, drive the digital inputs close to
the power rails (that is, OVDD and OGND).
The AD7641 uses three sets of power supply pins: an analog
2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.3 V
and 5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply, as shown in
CONVERSION CONTROL
The AD7641 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion.
Detailed timing diagrams of the conversion process are shown
in
Figure 23.
Power Sequencing Figure 29. Once initiated, it cannot be restarted or aborted,
even by the power-down input, PD, until the conversion is
complete. The
The AD7641 is independent of power supply sequencing and
thus free from supply induced voltage latch-up. In addition, it is
very insensitive to power supply variations over a wide
frequency range, as shown in Figure 28.
65.0
45.0
1 10000
FREQUENCY (MHz)
PSRR (dB)
04761-029
10 100 1000
62.5
60.0
57.5
55.0
52.5
50.0
47.5
INT REF
EXT REF
Figure 28. PSRR vs. Frequency
Power-Up
At power-up, or returning to operational mode from the power-
down mode (PD = high), the AD7641 engages an initialization
process. During this time, the first 128 conversions should be
ignored or the RESET input could be pulsed to engage a faster
initialization process. Refer to the Digital Interface section for
RESET and timing details.
A simple power-on reset circuit, as shown in Figure 23, can be
used to minimize the digital interface. As OVDD powers up, the
capacitor is shorted and brings RESET high; it is then charged
returning RESET to low. However, this circuit only works when
powering up the AD7641 because the power-down mode
(PD = high) does not power down any of the supplies and as a
result, RESET is low.
CNVST signal operates independently of CS and
RD signals.
04761-030
BUSY
MODE CONVERT ACQUIREACQUIRE CONVERT
CNVST
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
Figure 29. Basic Conversion Timing
CNVST
For optimal performance, the rising edge of should not
occur after the maximum CNVST low time, t1, or until the end
of conversion.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
The CNVST trace should be shielded with ground and a low
value serial resistor (for example, 50 Ω) termination should be
added close to the output of the component that drives this line.
In addition, a 50 pF capacitor is recommended to further reduce
the effects of overshoot and undershoot as shown in Figure 23.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 23.
AD7641
Rev. 0 | Page 21 of 28
INTERFACES
DIGITAL INTERFACE PARALLEL INTERFACE
The AD7641 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7641
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic
with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic
high output voltage. In most applications, the OVDD supply pin
of the AD7641 is connected to the host system interface 2.5 V
or 3.3 V digital supply. By using the D0/OB/
The AD7641 is configured to use the parallel interface for an
18-bit, 16-bit, or 8-bit bus width according to Table 7.
Master Parallel Interface
2C input pin, either
twos complement or straight binary coding can be used.
The two signals CS and RD control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7641 in
multicircuit applications and is held low in a single AD7641
design. RD is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7641 and generate a
fast initialization. A rising edge on RESET aborts the current
conversion (if any) and tristates the data bus. The falling edge of
RESET clears the data bus and engages the initialization process
indicated by pulsing BUSY high. Conversions can take place
after the falling edge of BUSY. Refer to Figure 30 for the RESET
timing details.
0
4761-031
RESET
DATA
BUSY
CNVST
t
38
t
39
t
8
t
9
Figure 30. RESET Timing
Data can be continuously read by tying CS RD
and low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications, unless the device is held in RESET.
Figure 31 details the timing for this mode.
04761-032
t
1
BUSY
DATA
BUS PREVIOUS CONVERSION DATA NEW DATA
CNVST
CS = RD = 0
t
10
t
4
t
11
t
3
Figure 31. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 32 and
Figure 33, respectively. When the data is read during the
conversion, it is recommended that it is read-only during the
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.
04761-033
CURRENT
CONVERSION
t
13
t
12
BUSY
DATA
BUS
RD
CS
Figure 32. Slave Parallel Data Timing for Reading (Read After Convert)
AD7641
Rev. 0 | Page 22 of 28
0
45761-034
PREVIOUS
CONVERSION
t13
t12
t3
BUSY
DATA
BUS
CNVST,
RD
CS = 0
t4
t1
SERIAL INTERFACE
The AD7641 is configured to use the serial interface when
MODE[1:0] = 3. The AD7641 outputs 18 bits of data, MSB first,
on the SDOUT pin. This data is synchronized with the 18 clock
pulses provided on the SCLK pin. The output data is valid on
both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7641 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7641 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted. Depending on the read during
convert input, RDC/SDIN, the data can be read after each
conversion or during the following conversion.
Figure 33. Slave Parallel Data Timing for Reading (Read During Convert)
16-Bit and 8-Bit Interface (Master or Slave)
In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2)
interfaces, the A0/A1 pins allow a glueless interface to a 16- or
8-bit bus, as shown in Figure 35 and
Figure 34. By connecting A0/A1 to an
address line(s), the data can be read in two words for a 16-bit
interface, or three bytes for an 8-bit interface. This interface can
be used in both master and slave parallel reading modes. Refer
to
Figure 36 show detailed timing diagrams of these two modes.
Usually, because the AD7641 is used with a fast throughput, the
master read during conversion mode is the most recommended
serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions. In this mode,
the SCLK period changes because the LSBs require more time
to settle and the SCLK is derived from the SAR conversion cycle.
Table 7 for the full details of the interface.
CS, RD
A1
D[17:2] HI-Z HIGH
WORD
LOW
WORD
HI-Z
t
12
t
13
04761-035
HIGH
BYTE
A0
MID
BYTE
LOW
BYTE
D[17:10]
t
12
HI-Z HI-Z
t
12
In read after conversion mode, it should be noted that unlike
other modes, the BUSY signal returns low after the 18 data bits
are pulsed out and not at the end of the conversion phase,
resulting in a longer BUSY width. As a result, the maximum
throughput cannot be achieved in this mode.
In addition, in read after convert mode, the SCLK frequency
can be slowed down to accommodate different hosts using the
DIVSCLK[1:0] inputs. Refer to
Figure 34. 8-Bit and 16-Bit Parallel Interface Table 4 for the SCLK timing
details when using these inputs.
AD7641
Rev. 0 | Page 23 of 28
04761-036
BUSY
SYNC
SCLK
S
DOUT
123 161718
D17 D16 D2 D1 D0
X
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
CNVST
CS, RD
EXT/INT = 0
t
23
t
22
t
16
t
15
t
14
t
29
t
19
t
21
t
20
t
18
t
28
t
30
t
24
t
25
t
26
t
27
t
3
DIVSCLK[1:0] = 0
Figure 35. Master Serial Data Timing for Reading (Read After Convert)
04761-037
EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0
D17 D16 D2 D1 D0X
123 161718
BUSY
SYNC
SCLK
SDOUT
CNVST
CS, RD
t
23
t
18
t
15
t
14
t
17
t
3
t
22
t
16
t
1
t
25
t
26
t
24
t
27
t
19
t
20
t
21
Figure 36. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
AD7641
Rev. 0 | Page 24 of 28
SLAVE SERIAL INTERFACE
External Clock An example of the concatenation of two devices is shown in
Figure 37. Simultaneous sampling is possible by using a
common
The AD7641 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/ CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Therefore, the MSB of the
upstream converter just follows the LSB of the downstream
converter on the next SCLK cycle.
INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive.
0
4761-038
SCLK
SDOUTRDC/SDIN
AD7641
#1
(DOWNSTREAM)
AD7641
#2
(UPSTREAM)
BUSY
OUT
BUSYBUSY
DATA
OUT
SCLK
RDC/SDIN SDOUT
SCLK IN
CNVST IN
CNVST
CS
CNVST
CS
CS IN
Figure 38 and Figure 39 show the detailed timing
diagrams of these methods.
While the AD7641 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7641 provides error correction circuitry
that can correct for an improper bit decision made during
the first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided,
a discontinuous clock is toggled only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
Figure 37.Two AD7641 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
Figure 39 shows the detailed timing diagrams of this method.
During a conversion, while
External Discontinuous Clock Data Read After Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 38 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning low, the conversion result can be read while both CS
and RD are low. Data is shifted out MSB first with 18 clock
pulses and is valid on the rising and falling edges of the clock.
Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 80 MHz, which accommodates both the slow digital host
interface and the fast serial reading.
Finally, in this mode only, the AD7641 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple converters
together. This feature is useful for reducing component count
and wiring connections when desired, as, for instance, in
isolated multiconverter applications.
CS RD
and are both low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and the RDC/SDIN input should always
be tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock (at least 60 MHz when normal mode is
used, or 80 MHz when warp mode is used) is recommended to
ensure that all the bits are read during the first half of the SAR
conversion phase.
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
However, this is not recommended when using the fastest
throughput of any mode because the acquisition time, t8, is
only 115 ns.
If the maximum throughput is not used, thus allowing more
acquisition time, then the use of a slower clock speed can be
used to read the data.
AD7641
Rev. 0 | Page 25 of 28
04761-039
SCLK
S
DOUT D17 D16 D1 D0
D15
X17 X16 X15 X1 X0 Y17 Y16
BUSY
SDIN
INVSCLK = 0
X17 X16
X
123 1617181920
EXT/INT = 1
CS RD = 0
t
33
t
16
t
34
t
31
t
32
t
35
t
36
t
37
Figure 38. Slave Serial Data Timing for Reading (Read After Convert)
04761-040
S
DOUT
SCLK
D1 D0
XD17 D16 D15
12317 18
BUSY
EXT/INT = 1 INVSCLK = 0
CNVST
CS
RD = 0
t
16
t
31
t
32
t
35
t
3
t
36
t
37
4
D2
16
Figure 39. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
AD7641
Rev. 0 | Page 26 of 28
SPI Interface (ADSP-219x)
MICROPROCESSOR INTERFACING
Figure 40 shows an interface diagram between the AD7641 and
an SPI-equipped DSP, the ADSP-219x. To accommodate the
slower speed of the DSP, the AD7641 acts as a slave device and
data must be read after conversion. This mode also allows the
daisy-chain feature. The convert command can be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with three SPI byte access. The reading process can be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
peripheral interface (SPI) on the ADSP-219x is configured for
master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock
phase bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) =
00 by writing to the SPI control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mb/s, allowing it to read an ADC result in less
than 1 μs. When a higher sampling rate is desired, it is
recommended to use one of the parallel interface modes.
The AD7641 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The
AD7641 is designed to interface with a parallel 8-bit or 16-bit
wide interface or with a general-purpose serial port or I/O ports
on a microcontroller. A variety of external buffers can be used
with the AD7641 to prevent digital noise from coupling into the
ADC. The SPI Interface (ADSP-219x) section illustrates the use
of the AD7641 with the ADSP-219x SPI-equipped DSP.
04761-041
BUSY
CS
SDOUT
SCLK
CNVST
AD7641
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx OR TFSx
ADSP-219x
1
DVDD
MODE0
MODE1
EXT/INT
RD
INVSCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Interfacing the AD7641 to ADSP-219x
AD7641
Rev. 0 | Page 27 of 28
APPLICATION HINTS
LAYOUT
While the AD7641 has very good immunity to noise on the
power supplies, exercise care with the grounding layout. To
facilitate the use of ground planes that can be easily separated,
design the printed circuit board that houses the AD7641 so that
the analog and digital sections are separated and confined to
certain areas of the board. Digital and analog ground planes
should be joined in only one place, preferably underneath the
AD7641, or as close as possible to the AD7641. If the AD7641 is
in a system where multiple devices require analog-to-digital
ground connections, the connections should still be made at
one point only, a star ground point, established as close as
possible to the AD7641.
To prevent coupling noise onto the die, to avoid radiating noise,
and to reduce feedthrough:
Do not run digital lines under the device.
Run the analog ground plane under the AD7641.
Shield fast switching signals, like CNVST or clocks, with
digital ground to avoid radiating noise to other sections of
the board, and never run them near analog signal paths.
Avoid crossover of digital and analog signals.
Run traces on different but close layers of the board, at right
angles to each other, to reduce the effect of feedthrough
through the board.
The power supply lines to the AD7641 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the impedance of the supplies presented
to the AD7641, and to reduce the magnitude of the supply
spikes. Decoupling ceramic capacitors, typically 100 nF, should
be placed on each of the power supplies pins, AVDD, DVDD,
and OVDD. The capacitors should be placed close to, and
ideally right up against, these pins and their corresponding
ground pins. Additionally, low ESR 10 μF capacitors should be
located in the vicinity of the ADC to further reduce low
frequency ripple.
The DVDD supply of the AD7641 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, and no
separate supply is available, it is recommended to connect the
DVDD digital supply to the analog supply AVDD through an
RC filter, and to connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. Refer
to Figure 23 for an example of this configuration. When DVDD
is powered from the system supply, it is useful to insert a bead
to further reduce high frequency spikes.
The AD7641 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and,
because it carries pulsed currents, should have a low impedance
return to the reference. AGND is the ground to which most
internal ADC analog signals are referenced; it must be connected
with the least resistance to the analog ground plane. DGND
must be tied to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system ground.
The layout of the decoupling of the reference voltage is
important. To minimize parasitic inductances, place the
decoupling capacitor close to the ADC and connect it with
short, thick traces.
EVALUATING THE AD7641 PERFORMANCE
A recommended layout for the AD7641 is outlined in the
documentation of the EVAL-AD7641-CB evaluation board for
the AD7641. The evaluation board package includes a fully
assembled and tested evaluation board, documentation, and
software for controlling the board from a PC via the EVAL-
CONTROL BRD3.
AD7641
Rev. 0 | Page 28 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
7.00
BSC SQ
1.60
MAX
0.75
0.60
0.45
VIEW A
9.00
BSC SQ
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
3.5°
0.15
0.05
Figure 41. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
PIN 1
INDICATOR
TOP
VIEW 6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12° MAX
0.20 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX PIN 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
EXPOSED
P
AD
(BOTTOM VIEW)
PADDLE CONNECTED TO AGND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES.
Figure 42. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad (CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7641BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
1
AD7641BCPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
1
AD7641BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
1
AD7641BSTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
1
EVAL-AD7641CB Evaluation Board
2
EVAL-CONTROLBRD3 Controller Board
3
1 Z = Pb-free part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators.
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D04761-0-1/06(0)