LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 High Performance Power Management Unit for Handset Applications Check for Samples: LP3925 FEATURES 1 * 2 * * * * * * * * * * * * * * Linear Charger With Single Input - USB or AC Adapter Input - Power Routing Switch - 28-V OVP on the Charger Input Three High-Efficiency Synchronous Magnetic Buck Regulators, IOUT 800 mA Each: - Two Regulators Have DVS Support - High-Efficiency ECO Mode at Low IOUT - Auto Mode ECO/PWM Switch - 28-V OVP on the Charger Input 15 LDOs - 10 General-Type Low-Noise LDOs: 8 x 300 mA, 2 x 80 mA - Three Wide-Input Low-Output (WILO) LDOs, All Capable of Supplying up to 300 mA - One Micro-Power LDO With IOUT 30 mA - One High-Voltage USB LDO - S/W Controllable Outputs - Outputs Configurable for Pulldown Two Comparators and Two TCXO Buffers USB 2.0-Compatible Transceiver (12 Mbps) 12-Bit A/D Converter for Battery Management and External Monitoring Two Over-Voltage Protected Outputs for USB Transceivers Real-Time Clock With Two Alarms SIM Card Level Translator Three Controllable Current Sinks for Keypad LEDs Backup Battery Charger Thermal Shutdown With Early Warning Alarm Momentary Power Loss detection Interrupt Request to Reduce S/W Polling 81-Bump DSBGA Package KEY SPECIFICATIONS * * * * * * * Low PMU IQ in Sleep Mode 50-mA to 1200-mA Charging Current From AC Adapter 3.0-V to 4.5-V Battery Voltage 150-mV (Typ) Dropout Voltage on LDOs at 300 mA 2% (Typ) Output Voltage Accuracy on LDOs Ultra Low Noise (10 V Typ), Ultra Low IQ, Remote Capacitor General-Type "Perfect" LDOs 3% Accurate Buck Regulators up to 90% Efficient APPLICATIONS * GSM, GPRS, EDGE, CDMA, and 3G Handsets DESCRIPTION The LP3925 is designed to meet the power management requirements of the latest 3G/GSM/GPRS/EDGE cellular phones. The LP3925 PMU contains a single-input Li-Ion battery charger, 14 low-dropout voltage regulators including 3 wideinput, low-output, regulators, 3 buck regulators, a USB Transceiver, two comparators, two TCXO buffers, SIM level shifter, 12-bit ADC, real time clock, and backup battery charger. Programming is handled via an I2C-compatible high-speed Serial Interface allowing control of program on/off conditions and the output voltages of individual regulators, and to read status information of the PMU. It can charge and maintain a single cell Li-Ion battery operating from an AC adapter or USB power source. The Li-Ion charger requires few external components and integrates the power FET. Charging is thermally regulated to obtain the most efficient charging rate for a given ambient temperature. A built-in Over-Voltage Protection (OVP) circuit at the charger input protects the PMU from input voltages up to +28V eliminating the need for any external protection circuitry. Buck regulators have an automatic switch to ECO mode at low load conditions providing very good efficiency at low output currents. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2013, Texas Instruments Incorporated LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com DESCRIPTION (CONTINUED) Buck regulators have an automatic switch to ECO mode at low load conditions providing very good efficiency at low output currents. General-type "PERFECT" LDO regulators provide excellent PSRR and ULTRA LOW NOISE, 10 V typ., ideally suited for supplying voltage to RF section. The real-time clock/calendar provides time interval information as well as two programmable alarms. To accommodate different baseband requirements, the LP3925 PMU has different default voltage settings and startup sequences. Two general-purpose comparators can be used for detecting external accessories like earphones etc. Power conversion and signal level shifting circuits are provided to allow SIM interfacing. 2 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Typical Application Diagram VBUCK3 VDD VIN2 VIN3 VIN4 10 PF LDO1 CHARGER VIN_CHG 10 PF 10 PF VIN1 10 PF VDD - BATT + RSENSE* VDD LDO1 1 PF 1 PF ADC SW LDO2 LDO2 1 PF LDO3 LDO LDO3 10 General LDOs Charger 28V OVP VTRM 1 PF USB LDO 28 OVP 1.5 k: 10: D+ LP3925 LDO1 D10: SE0/VM* 1 PF LDO4 LDO4 1 PF LDO5 LDO5 1 PF LDO6 LDO6 1 PF LDO7 LDO7 1 PF LDO8 LDO8 DATA/VP* USB transceiver OE_N* 1 PF LDO9 LDO9 PWR LDO RCV* 1 PF LDO10 SPND* LDO10 1 PF GND_USB 3 WILO LDOs XOUT 32 kHz OSC XIN VCOIN + - Backup Battery Charger SEL RTC LDO1 1.5 k: LDO11 WILO1 1 PF LDO12 WILO2 1 PF LDO13 WILO3 1 PF LDO_UPWR 500 k: 1.5 k: 1 PF VDD MPL LDO1 SDA RSTOUT_N 500 k: Serial Interface and Control PS_HOLD TCXO1_O* 2TCXO Buffers TCXO2_I* TCXO2_O* PWR_ON HF_PWR 500 k: 500 k: 500 k: REF_OUT VIN_B1 SIM_DATA* SIM_RST_IN* 4.7 PF FB_B1 SW_B1 4.7 PF VIN_B2 VDD 1 PH 12 Input MUX Thermal Shutdown 4.7 PF VIN_B3 1 PH SIM card SIM_CLK* 3 Bucks SW_B2 4.7PF FB_B3 VBUCK3 SIM_IO* SIM_RST* 4.7 PF FB_B2 VBUCK2 SIM_CLK_IN* USIM Level Shifter INP2* 2 Comparators Reference Voltage SINK3* 3 Current Sinks SW_B3 Oscillator GND_B3 GND_B2 GND_B1 4.7 PF INP1* SINK2* SINK1* GND_SINK VDD 12bit ADC GND VBUCK1 1 PH 10 k: TCXO1_I* SLEEP_N (TCXO_EN) VDD 10 k: IRQ_N SCL RSTIN_N BATT OSC_32KHZ Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 3 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com Pin Configuration 9 LDO5 VIN2 LDO6 LDO7 8 LDO 3 LDO4 LDO8 SIM_IO* 7 RSTIN _N SLEEP_N (TCXO_EN) SIM_ CLK* SIM_ LDO 2 GND_ CLK_IN* SINK 6 VIN1 TCXO1 _I* RSTOUT _N SIM_ RST* RST_IN* LDO1 LDO_ 5 TCXO2 _I* SEL 4 XOUT VCOIN TCXO2 _O* 3 XIN PWR_ ON 2 VIN_ CHG 1 LDO9 LDO10 LDO11 LDO12 SINK2* SINK1* REF_ OUT VIN4 SINK3* PS_ HOLD LDO13 INP2* GND_B3 GND_B3 SW_ B3 GND INP1* IRQ_N FB_B3 VIN_B3 HF_ PWR SPND* RSE NSE* GND_ B2 GND_B2 SW_B2 TCXO1 _O* OSC_ 32KHZ* RCV* SCL SDA FB_B2 VIN_B2 VIN_ CHG VIN_ CHG VTRM OE_N* SE0 / DATA/ VM* VP* GND_B1 SW_B1 VDD VDD BATT BATT D- D+ USB_ GND FB_ B1 VIN_B1 A B C D E F G H UPWR VIN3 SIM_ DATA* SIM_ J Figure 1. LP3925 (Top View) * Pins that can be programmed as analog pins (default as stated in pin configuration) or digital input/output pins. Pins that are used for USB transceiver interfacing are chosen in accordance of the interface used, either 3-wire or 5-wire. All these pins except SINK1, 2, 3 and INP1, 2 can be used as ADC inputs. 4 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Pin Functions Table 1. Pin Descriptions Name Pin No. BATT C1, D1 P Main battery connection. (3) Description D- E1 A USB Differential Data Line (-) Input/Output. D+ F1 A USB Differential Data Line (+) Input/Output. DATA/VP (2) G2 DI/O FB_B1 H1 A Buck1 Feedback. FB_B2 H3 A Buck2 Feedback. FB_B3 H5 A Buck3 Feedback. GND E5 G Ground GND_B1 H2 G Power Ground for Buck1. GND_B2 G4, H4 G Power Ground for Buck2. GND_B3 G6, H6 G Power Ground for Buck3. GND_SINK F7 G Ground of GPIO current sink. HF_PWR D4 DI Input for triggering startup. Power up sequence starts when this pin is set HIGH. Internal 500 k pulldown resistor. INP1 (3) F5 A Comparator 1 input (3) F6 A Comparator 2 input IRQ_N G5 DO LDO_UPWR B5 A Internal supply output, fixed to 1.8V. Can be loaded externally, max 30 mA. INP2 (1) (2) Type (1) Data input/output for 3 wire USB transceiver/ USB Interface Plus Input/Output for 5 wire USB. If OE_N = HIGH, VP is a receiver output (+), If OE_N = LOW, VP is a driver input (+). Interrupt output, active LOW. Open Drain output, external pull up resistor is needed, typ. 10 k. LDO1 A5 A LDO1 Output LDO10 G9 A LDO10 Output LDO11 H9 A LDO11 Output LDO12 J9 A LDO12 Output LDO13 J7 A LDO13 Output LDO2 A7 A LDO2 Output LDO3 A8 A LDO3 Output LDO4 B8 A LDO4 Output A = Analog Pin, D = Digital Pin, I = Input Pin, DI/O = Digital Input/Output Pin, G = Ground, O = Output Pin, P = Power Connection Pins that can be programmed as analog pins (default as stated in pin configuration) or digital input/output pins. Pins that are used for USB transceiver interfacing are chosen in accordance of the interface used, either 3-wire or 5-wire. All these pins except SINK1, 2, 3 and INP1, 2 can be used as ADC inputs. Pins that can be programmed as analog pins (default as stated in pin configuration) or digital input/output pins. Pins that are used for USB transceiver interfacing are chosen in accordance of the interface used, either 3-wire or 5-wire. All these pins except SINK1, 2, 3 and INP1, 2 can be used as ADC inputs. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 5 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com Table 1. Pin Descriptions (continued) Name Pin No. LDO5 A9 A LDO5 Output LDO6 C9 A LDO6 Output LDO7 D9 A LDO7 Output LDO8 C8 A LDO8 Output LDO9 F9 A LDO9 Output E2 DI USB Output Enable input. Active LOW enables the transceiver to transmit data onto the bus. A HIGH input enables receive mode. OSC_32KHZ (3) D3 DO Buffered 32 kHz clock signal output. PS_HOLD H7 DI Control input for Power Up/Power Down sequences of PMU. Internal 500 k pulldown resistor by EEPROM default. Can be configured as pullup as well. PWR_ON B3 DI Power button input. Power up sequence starts when this pin is set HIGH. Internal 500 k pulldown resistor. RCV (3) E3 DO Receive Data: Single ended output from USB differential data lines for 5 wire USB. REF_OUT H8 A 2.5V Reference output OE_N (3) RSENSE (3) Description F4 A Sense resistor input pin for charge/discharge current measurement RSTIN_N B7 DI Reset button input, active low. Internal 500 k pullup resistor. RSTOUT_N C6 DO Reset output, active low. Pin stays LOW during power up sequence. SCL F3 DI Serial interface clock input; requires external pullup, 1.5 k typ. G3 DI/O Serial interface bi-directional data; requires external pullup, 1.5 k typ. F2 DI/O Data input/output for 3 wire USB transceiver/ USB Interface Minus Input/Output for 5 wire USB. If OE_N = HIGH, VM is a receiver output (-), If OE_N = LOW, VM is a driver input (-). SDA SEO/M (4) SEL D5 DI Select input for default option at power up SIM_CLK (4) D7 DO SIM card connection. Level shifted clock signal to SIM SIM_CLK_IN (4) E7 DI SIM clock input from Baseband Processor SIM_DATA (4) E8 D SIM data input/output from Baseband Processor SIM card connection. SIM Card Data input/output SIM_IO (4) D8 D SIM_RST (4) D6 DO SIM card connection. Level shifted reset signal to SIM SIM_RST_IN (4) E6 DI SIM reset input from Baseband Processor (4) G8 A Current sink input 3. SINK2 (4) F8 A Current sink input 2. SINK3 (4) G7 A Current sink input 3. SLEEP_N (TCXO_EN) C7 DI Sleep mode input, active low. Internal 500 k pullup resistor by EEPROM default. Can be configured as pulldown as well. SPND (4) E4 DI USB Suspend mode control input for 5 wire USB. A logical high at SUSPEND will power down the differential receiver and VP and VM will remain active with reduced current consumption. SW_B1 J2 A Buck1 Output. SW_B2 J4 A Buck2 Output. SINK1 SW_B3 J6 A Buck3 Output. TCXO1_I (4) B6 A TCXO1 buffer input. TCXO1_O (4) C3 DO TCXO2_I (4) C5 A TCXO2_O (4) 6 Type (1) (4) Buffered and validated TCXO1 output clock signal. TCXO2 buffer input. C4 DO USB_GND G1 G Buffered and validated TCXO2 output clock signal. USB Ground VCOIN B4 A Back up battery Charger Output. Connection of external coin cell (2.5 or 3.0V). VDD A1, B1 P Output for system power. VIN_B1 J1 P Input for Buck1 Pins that can be programmed as analog pins (default as stated in pin configuration) or digital input/output pins. Pins that are used for USB transceiver interfacing are chosen in accordance of the interface used, either 3-wire or 5-wire. All these pins except SINK1, 2, 3 and INP1, 2 can be used as ADC inputs. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Table 1. Pin Descriptions (continued) Type (1) Name Pin No. VIN_B2 J3 P Input for Buck2 Description VIN_B3 J5 P Input for Buck3 VIN_CHG A2, B2, C2 P DC power input to charger block from wall, car power adapter or USB. Requires 1F capacitor to ground. VIN1 A6 P Input for LDOs VIN2 B9 P Input for LDOs VIN3 E9 P Input for LDOs VIN4 J8 P Input for LDOs VTRM D2 A USB Reference supply output (3.3 V). Requires 1F capacitor to GND for stability. LDO14 XIN A3 A External Crystal Oscillator In XOUT A4 A External Crystal Oscillator Out These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) -0.3V to +28V VINCHG to GND BATT, VIN_B1, VIN_B2, VIN_B3, VCOIN, VIN1, VIN2, VIN3, VIN4 -0.3V to +6V SEL -0.3V to +2V Other input-only pins Junction Temperature 0.3V to +6V (4) 150C -65C to +150C Storage Temperature Maximum continuous power dissipation See VIN_CHG, BATT, HF_PWR, PWR_ON, RSTIN_N, D+, D-, RSENSE, SIM_IO, SIM_CLK, SIM_RST, GND_USB (5) All other (1) (2) (3) (4) (5) (5) (4) 8kV HBM 2kV HBM Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Internal thermal shutdown protects the device from permanent damage. Thermal shutdown engages at TJ = 150C (typ.) and disengages at TJ=130C (typ). The Human body model is a 100 pF capacitor discharged through a 1.5 k resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 7 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Operating Ratings (1) www.ti.com (2) VIN_CHG 4.5V to 6.5V BATT, PRSW, VIN_B1, VIN_B2, BIN_B3 3.0V to 4.5V VCOIN 1.9V to 4.5V VIN1, VIN2, VIN3 2.5V to 4.5V VIN4 1.0V to 4.5V -40C to +125C Junction Temperature Range Maximum Ambient Temperature Maximum power dissipation (3) -40C to +85C (3) 1.72W Package Thermal Resistance JA (1) (2) (3) 32C/W Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. The Maximum power dissipation depends on the ambient temperature and can be calculated using the formula P = (TJ - TA)/JA where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance. The 1.72W rating appearing under Maximum Ratings results from substituting the Maximum junction temperature, 125C, for TJ, 70C for TA, and 32C/W for JA. More power can be dissipated safely at ambient temperatures below 70C. Less power can be dissipated safely at ambient temperatures above 70C. The Maximum power dissipation can be increased by 31 mW for each degree below 70C, and it must be derated by 31 mW for each degree above 70C. General Electrical Characteristics Typical values and limits appearing in normal typeface are for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation TJ = -40C to +125C). Unless otherwise specified, the following applies for VBATT = 3.6V. (1) Symbol Parameter Test Conditions Typ Limits Min Max 3.0 3.25 Unit UNDER VOLTAGE LOCK-OUT UVLO Range-to-range accuracy VIN Rising; UVLO LEVEL programmed to 3.10V V LOGIC AND CONTROL INPUTS VIL Input low level VIH Input high level VIL Multifunctional pins low level VIH Multifunctional pins high level SDA (2), SCL SPND (2) , OE_N, DATA/VP, SEO/VM, 0.25 x VLDO1 PWR_ON, RS_HOLD, SLEEP_N, HF_PWR, RSTIN_N SDA (2), SCL SPND V 1.08 (2) , OE_N, DATA/VP, SEO/VM, 0.75 x VLDO1 PWR_ON, RS_HOLD, SLEEP_N, HF_PWR, RSTIN_N V 1.32 0.6 When configured as logic inputs. 1.6 3.0 -5 +5 V SEL input between 0V and 1.8V. ILEAK Input current RIN Input resistance (1) (2) 8 Other logic inputs without internal pullup or pulldown resistors between 0V and VDD at 3.6V. PWR_ON, HF_PWR, PS_HOLD, RSTIN_N, SLEEP_N (TXCO_EN) pullup or pulldown resistors (if configured) 500 A k All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 General Electrical Characteristics (continued) Typical values and limits appearing in normal typeface are for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation TJ = -40C to +125C). Unless otherwise specified, the following applies for VBATT = 3.6V. (1) Symbol Parameter Test Conditions Typ Limits Min Max Unit LOGIC AND CONTROL OUTPUTS VOL RSTOUT_N, RCV, DATA/VP, SEO/VM, IRQ_N IOUT = 2mA Output low level SDA (3) V 0.25 x VLDO1 VOH Output high level RCV, DATA/VP, SEO/VM IOUT = 2mA IOH Output high leakage SDA (3), RSTOUT_N, IRQ_N VOH = VLDO1 (3) 0.25 x VLDO1 0.75 x VLDO1 V 10 A Specified by design. Current Consumption Current consumption of the LP3925 PMU has been one of the main features this device is famous for. It is mainly because of ultra low IQs in sleep and standby modes the LP3925 can ensure dramatic power savings and prolong battery life for enormous amount of time. Due to such a significant advantage in these critical factors, an LP3925 is very convenient to use in innovative and environmentally friendly designs, giving the end user the possibility of increased consumer device working time and thus a crucial advantage of the rapidly developing mobile market. The quiescent currents in standby and sleep modes are stated in the Current Consumption Electrical Characteristics. Current Consumption Electrical Characteristics Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (1) Symbol Parameter Test Conditions Typ Limits Min Max Unit CURRENT CONSUMPTION IQ(STANDBY) Battery Standby Current VIN = 3.6V ICOIN = 0A 3.5 IQ(SLEEP) Battery Current in SLEEP mode at 0 load LDO1 ON 60 (1) A All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 9 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com DEVICE OPERATING MODES POWER-ON-RESET: All internal registers are reset to default values. This is the default state after applying power to the PMU, duration 1ms. STANDBY: All functions disabled (except RTC power management); PMU is in low power mode. START UP: Startup sequence is triggered by setting PWR_ON input high for 100 ms or by setting HF_PWR input high for 100 ms or by connecting a suitable voltage to charger input. For MPL or RTC ALARM events the startup sequence begins after 2ms delay from the MPL or RTC ALARM events. During the sequence the regulators on PMU are enabled according to a pre-programmed timing pattern. If the regulators are enabled, RSTOUT_N is released, allowing the application processor to start up. PS_HOLD must be set high in 1.5 seconds from the start of STARTUP. The input signal witch activates startup must stay on until PS_HOLD asserted. If PS_HOLD is not asserted in 1.5 seconds then SHUTDOWN is initiated. For PWR_ON startup there is no 1.5 seconds limit. IDLE: PMU goes to normal working mode, if PS_HOLD is pulled HIGH after releasing RSTOUT_N. In this mode all features and control interfaces are available to the user. Chip temperature over TSDH, VDD voltage below UVLO, PS_HOLD going low for 10 ms or a flag failure in a monitored regulator for 10 ms will cause the PMU to go to SHUTDOWN state. SLEEP: PMU goes to SLEEP state from IDLE state, if SLEEP_N input is pulled low. In this mode PMU current consumption is minimized to extend device's standby time. Load on regulators and bucks should stay below 5mA each. Conditions of going to SHUTDOWN state are the same as in IDLE state.. SLEEP Mode is controlled by the Serial Interface. SHUTDOWN: In this state RSTOUT_N is pulled LOW and all regulators are disabled according to preprogrammed timing pattern. After this, all registers are reset to default values, and PMU goes to STANDBY state. SYSTEM RESET: PMU goes to SYSTEM RESET mode if RSTIN_N input has been pulled low for 33 ms. In this mode RSTOUT_N output is pulled low and user registers are reset. After a pre-programmed time delay RSTOUT_N is released, allowing the application processor to start up. During SYSTEM RESET, the LP3925's always-on power rail will not drop to zero. If for some reason PS_HOLD is pulled down during reset, it must come back up within 1.5s of the beginning of system reset. If EN RSTIN SHUTDOWN bit is high then the reset sequence is similar to shutdown and will startup again only if EN RSTIN STARTUP bit is high. 10 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 POWER-ON RESET Internal Powerup Delay 5 ms PWR_ON = 1 for 100 ms OR HF_PWR = 1 for 100 ms OR VBAT < VCHGIN < VCINH for 550 ms OR coming from RSTIN reset OR RTC alarm event OR MPL event STANDBY STARTUP PS_HOLD = 0 after 1500 ms OR VDD Voltage < VUVLO Sequence Duration 1 ms RSTOUT_N = 1 AND PS_HOLD = 1 SHUTDOWN WORKING Chip Temperature > TTSD_HI OR RSTIN_N = 0 for 33 ms AND RSTIN shutdown enabled OR PS_HOLD = 0 for 10 ms OR VDD Voltage < VUVLO OR Monitored Supply < 85% for 0.5 ms PS_HOLD = 0 after 1500 ms RSTOUT_N = 1 AND PS_HOLD = 1 CPU RESET SLEEP_N = 1 (TCXO_EN) RSTIN_N = 0 for 33 ms AND RSTIN shutdown disabled SLEEP_N = 0 (TCXO_EN) SLEEP Figure 2. Device Operating Modes Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 11 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com STARTUP AND SHUTDOWN SEQUENCES VIN_CHG 1.5s 550 ms only for HF_PWR HF_PWR or PWR_ON 100 ms 192 us Step1 supplies: Step2 supplies: 192 us 32 us 256 us 32 us 64 us 32 us Y. 32 us prog 32 us prog 33 ms RSTIN_N 50 ms RSTOUT_N 32 us Y. Y. Y. Y. Step15 supplies: 1.5s 100 ms 1500 ms 50 ms 50 ms 1500 ms 450 us 450 us 10 ms PS_HOLD SLEEP_N 192 us 192 us OSC_32kHz CLK STANDBY STARTUP IDLE SLEEP IDLE RESET IDLE SHUTDOWN STANDBY STARTUP SHUTDOWN STANDBY Figure 3. Startup and Shutdown Sequences The default, factory-programmed power-up sequence of the PMU can be seen in Figure 3. Startup sequence is triggered by setting PWR_ON or HF_PWR input high for 100 ms or after 500 ms is passed from the connection of a suitable voltage to the charger input. Once this time has expired, the start-up time slots begin. The programmable values of the startup and shutdown time slots are available in the Default Operating Settings section at the end of the datasheet. If the Idle state has been reached from the Startup state, all regulators that are enabled are on, and their outputs are defined by their programmed register values. 450 s in startup/shutdown diagram is the time needed for system to perform a shutdown event. NOTE All the timings are limited by an internal oscillator's accuracy. Please contact TI sales for default EEPROM setting details. 12 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 ENABLE CONTROL LP3925 provides much flexibility in enabling/disabling on-chip features. The blocks that have advanced enable controls include: LDOs, buck regulators, USB transceiver, TCXO buffers, SIM level shifter. Each block has a 4-bit code in registers, which selects the enable signal for that block. These codes are in register addresses 0x37...0x41, with bit names ending with CONTROL. The enable signal translation table is stated below. In order to make the control more flexible, there is a possibility for the blocks to be enabled through registers 0x00...0x02 or through multifunctional pins. One control signal can enable any number of features. This allows to group signals so, that any end-system function can be switched on with only one input or register write. There are additional enable controls for sleep mode operation with ALLOW IN SLEEP bits in register addresses 0x34...0x36. If a block is not allowed in sleep mode, then this block is always off during sleep. If a block is allowed in sleep mode, then it is controlled by its selected enable signal, and does not depend on sleep mode. Example 1: Goal: Buck2 is always disabled in sleep mode and enabled in idle mode. Best solution: write BUCK2 CONTROL to '0001' and ALLOW BUCK2 IN SLEEP to '0'; now Buck2 is enabled in working mode and disabled in sleep mode, with no separate enable bit/input. Example 2: Goal - Enable LDO9, LDO10 and TCXO buffer1 together with one register write. One possible solution: write LDO9 CONTROL, LDO10 CONTROL and TCXO1 CONTROL to 0010; now writing '11' to address 0x00 bits [1:0] enables all three blocks. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 13 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com MULTIFUNCTIONAL PINS Some pins corresponding to 32 kHz oscillator, USB transceiver, SIM interface, TCXO buffer, current sink and comparator blocks along with RSENSE pin are multifunctional pins, which means that they can be programmed as analog function pins, ADC inputs or digital input/output pins. These pins can be configured from registers 0x19..0x23. If one block uses more than one pin, then all the pins must be configured for the block to work. For example, all 6 SIM level shifter pins must have level shifter function selected, before the block is connected to the pins. To use USB with 4- or 5-wire interface, the used pins must all be configured as 5-wire USB pins. For 3-wire interface the 3 pins must all be configured as 3-wire USB pins. Some GPIO functions have separate enable controls. These enables will take the blocks to a shutdown state, but will not disconnect them from the pins. The GPIO configuration options are described in Table 2. Table 2. Pin/Code 1000 1001 1010 1011 OSC_32 KHZ RSENSE 1100 1101 12 mV 26.4 mV 39.6 mV 56.4 mV 81.6 mV SIM RST, baseband side SIM_CLK _IN SIM CLK, baseband side SIM_DATA 98.4 mV 120 mV SIM I/O, baseband side SIM_RST SIM RST, SIM side SIM_CLK SIM CLK, SIM side SIM_IO SIM I/O, SIM side TCXO1 warmup time before output enable TCXO1_I 1s 21 s x8 x4 41 s 61 s TCXO1 output driver strength TCXO1_O TCXO2_O 1111 Maximum measurable voltage drop on sense resistor N/A SIM_RST_IN TCXO2_I 1110 32 kHz OSC x2 x1 TCXO2_I warmup time before output enable TCXO2in wait=1s TCXO2in wait=21 s TCXO2in wait=41 s TCXO2in wait=61 s TCXO2 output driver strength TCXO2out strength=1 TCXO2out strength=2 TCXO2out strength=4 TCXO2out strength=8 OE_N OE_N: 3-pin USB interface DATA/VP DATA: 3-pin USB interface VP: 5-pin USB interface SEO/VM SEO: 3-pin USB interface VM: 5-pin USB interface RCV N/A RCV: 5-pin USB interface SPND N/A INP1 INP2 SINK1 SINK2 SINK3 14 OE_N: 5-pin USB interface SUSP: 5-pin USB interface Comparator1 input comparison threshold 0.4V 0.6V 0.8V 0.4V 0.6V 0.8V 1.0V 1.2V 1.5V 1.8V 2.4V 1.5V 1.8V 2.4V 188 mA 219 mA 250 mA 75 mA 88 mA 100 mA 75 mA 88 mA 100 mA Comparator2 input comparison threshold 1.0V 1.2V Current sink1 max current output 31mA 63 mA 94 mA 125 mA 156 mA Current sink2 max current output 13 mA 25 mA 38 mA 50 mA 63 mA Current sink3 max current output 13 mA 25 mA 38 mA 50 mA 63 mA Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 SINGLE-INPUT LINEAR CHARGER WITH PMOS ROUTING SWITCH LP3925 has a built-in Li-Ion/Li-Poly battery management system. Its main features are: * One input with many current limit options to accommodate different USB and adapter types * Separate supply branches for battery and system * Integrated power routing switch * Charging cycle with precharge, constant current and constant voltage modes * Selectable battery regulation voltage to accommodate different batteries * Selectable system regulation voltage * Wide array of battery charging current options * Flexible charging cycle control * Temperature monitoring to avoid overheating * Selectable safety timer GENERAL CHARGER CONTROL The charger control is divided into two separate parts: battery charging and system supply. Battery charging part of the charger measures battery voltage and current. Based on this data, it makes the decisions about starting or ending battery charging and choosing the right current. System supply part monitors the power consumption by the external system, ensures that the system supply is stable and that the charger input is not overloaded. These systems work independently from each other. If the power routing switch is OFF (non-conducting), then they can be viewed as two separate systems. The only dependence between the two is, that battery charging current can be reduced, if the system requires more current from the input. If the power routing switch is turned ON, then the two algorithms still work independently, but the system supply part is in control of the whole charger. The battery charging part is in the situation, that it still does make battery charging cycle decisions, but these do not affect the actual charging. If the switch is turned OFF again, then the two systems keep on working separately. CHARGER INPUT DETECTION AND LIMITS Input detection is implemented with 2 comparators. One compares the input voltage to the lower limit of the working range, the other to the higher limit of the working range. If the input voltage is between these two levels, then the charger is allowed to work. The lower limit of input's working range is VBATT+200 mV, with an option to add a 4.2V minimum requirement. The higher limit of input's working range can be one of the following values: 6.15V, 6.64V, 7.18V, 7.71V, 10.28V, 15.38V, 18.45V or disabled. To get the exact information about your product, please refer to the Datasheet Addendum document. The charger is capable of limiting input current, allowing to accommodate different voltage sources (wall adapters, USB, etc). IDCIN bits set the maximum input current. The sum of system supply and battery charging currents will not go over this limit during normal operation. For correct operation, IDCIN should be set to 235mA or more above IBATT (though this margin can be reduced for IDCIN below 500 mA; e.g. down to 85 mA at IDCIN = 135 mA). High current mode ignores the input current limit. Some of the GPIO pins can be configured as a dedicated charger input status signal output. This signal is low, if charger input is in working range. The 'Inverted VDCIN' configuration details are in the GPIO chapter of the datasheet. SYSTEM SUPPLY FUNCTION system supply regulator starts to regulate voltage on VDD pin. The voltage is selectable with VDD control bits. System voltage regulator will work as long as charger input is in working range. The only exception is the case, where PMU is in standby mode and system supply is configured off in standby. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 15 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com Because system and battery are supplied from separate branches, the VDD and BATT voltage levels can be different. This means, that the selected voltage can be supplied to VDD and the PMU can fully operate, while the battery is deeply discharged and the charger is in pre-charge mode. In that case the system should not use modes, which will require more current, than the input can provide. System supply is with higher priority than battery charging. This means that if the sum of system and battery currents starts to go over the input limit, then battery charging current will be reduced to stay within the input loading limit. If the system supply reaches the selected input current limit, then the power routing switch will be turned ON. This will connect the battery to the system, which will provide the extra power needed. Also, the system supply current limit will change from input current limit (IDCIN bits) to battery current limit (IBATT bits). This ensures, that if the system load drops, then the battery will not be charged with too large current. In some systems it may be practical to disable the input current limit, so the system can draw more than 1.2A without turning the switch ON. The SYSTEM SUPPLY CURLIM OFF bit can be used for this purpose. Warning: continuous high current draw from the input may cause the PMU to shut down because of high temperature. There is a configuration option for the system supply during PMU's standby mode. The selection for a specific product is shown in Datasheet Addendum document. This option has following behavior: a) supply on during PMU standby: VDD is supplied from BATT via switch (if charger is not working) or from system supply branch (if charger is working). b) supply off during PMU standby: VDD is isolated from BATT pin during PMU standby and system supply branch is disabled. BATTERY CHARGING FUNCTION LP3925 has a safe and smart Li-Ion/Li-Poly battery charge management system, keeping the number of battery charging cycles to a minimum and thus increasing battery lifetime. Following the correct detection of a voltage at the charger input, the charger enters precharge mode. In this mode the battery is charged with a small constant current. Precharge settings are available in register 0x82 and these values are remembered as long as the PMU has power. CHARGER IPRECHARGE bits select the battery current in precharge mode. It should be noted, that value '00' disables precharge current completely. CHARGER VFULLRATE bits select the level, from which the battery can be charged with full charging current. If battery voltage reaches that level, then the charger will move on to full charging mode. CHARGER TPRECHARGE sets the maximum precharge time, after which the battery will be isolated, protecting it from further charging. In full charging mode full rate constant current is applied to the battery, to raise the voltage to the termination level (selected by VTERM bits). The maximum charging current is selectable via IBATT bits, but the actual current can be lower than this limit, depending on the load of system branch. When termination voltage is reached, the charger enters constant voltage mode and a constant voltage is maintained. Now charging current is monitored to detect the end-of-charge condition. After reaching this condition, charger disables the battery charging branch and enters standby mode. FULL TIMEOUT sets the maximum full charge duration, after which the charging will be ended automatically. Then the charger enters standby mode, where the battery is isolated and the charger monitors battery voltage. If restart conditions have been met, then the charging cycle is reinitiated to re-establish the termination voltage level. In standby mode the battery is isolated and the charger monitors battery voltage. CC TO CV MODE TRANSITION CC to CV mode transition is shown on Figure 9. The voltage level of charging mode change (CC to CV) is dependent on both VTERM (0x47, bit3-0) and IBATT (real charging current) settings, equation shows below: VCCtoCV = VTERM - (IBATT*0.05) 16 (1) Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 where 0.05 stands for charger's internal resistance. This equation is valid only when the power routing switch is in non conducting state and the charging is done through charger's branch. When the switch is ON, the charging is done through the supply branch, and the internal resistance in the equation is replaced by the power routing switch's ON resistance. Note that the IBATT current in equation is the real battery charging current which may differ from the programmed one. USER can use ADC to measure charging current and BATT pin voltage. END-OF-CHARGE AND RESTART Ending and re-starting the charging cycle can be accomplished in multiple ways. Automatic control can be enabled with AUTOMATIC START/STOP bit. If this bit is '0', then the charging cycle can only be controlled manually. Writing this bit to '1' enables fully automatic cycle control. Manual control is always available via STOP CHARGING and START CHARGING bits. These control bits are write-only and not tied to any internal monitoring, allowing to start and stop charging at any time. Only one of these bits must be written to '1' at once. Automatic control utilizes internal battery monitoring, which can be configured trough control registers. Automatic end-of-charge requires that the battery has reached termination level. Then the charger starts monitoring battery charging current and comparing it to end-of-charge current (set by ABS EOC and EOC LEVEL bits). If the charging current is below this level for the duration of EOC TIME, then the automatic end-of-charge condition has been reached. Automatic restart requires that one charging cycle has already been completed and the charger is in standby mode. Then the charger monitors battery voltage and compares it to restart level (set by RESTART LEVEL). If the battery voltage is below this level for the duration of RESTART TIME, then the automatic restart condition has been reached. In manual-only mode it is possible to get automatic cycle control information via interrupts. CHARGE STOP INT is generated, if end-of-charge condition has been reached, and CHARGE START INT is generated, if restart condition has been reached). POWER ROUTING SWITCH This switch separates the battery from the system. This helps to conserve charge and reduce the count of charge-discharge cycles. If charger input is not connected, then the switch is in ON (conducting) state. In normal conditions the switch is OFF during charger operation. The switch will be turned ON, if the system load is greater than the charger can supply. This event also generates a SWITCH AUTO ON interrupt. If the switch is turned ON during charger operation, then it does not turn back OFF automatically. The only exception to that rule is, if the PMU enters standby mode. If the charger is operating and the switch is turned ON, then only system supply branch is working. Maximum output current is then set by IBATT code, to avoid too high current into the battery. If the charger is working, then power routing switch state can be controlled manually with SWITCH ON and SWITCH OFF command bits. It is advisable to use the SWITCH ON command before the system enters a mode, which draws more current than the input can provide. This will help to avoid voltage drop on VDD, before the internal overload detection reacts. If the system returns to low consumption mode, the SWITCH OFF command bit should be used to restore normal charger operation. OPERATION WITHOUT BATTERY The charger is not aware of battery presence, it always behaves by the same configuration. If the battery is not connected, then it is recommended to keep the battery charging part disabled. This can be done by disabling the restart timer and ending the charging with STOP CHARGING bit. Otherwise the charger will keep trying to regulate the voltage on BATT pin, causing frequent charging cycles. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 17 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com HIGH-CURRENT MODE If HIGH-CURRENT MODE bit is set, then the charger enters special high load mode. In this mode the power routing switch is set ON, input current limit is disabled, and the charger branches are working together. All charging cycle controls do not have any effect in high current mode. Pre-Charge to Full-Rate Transition to ConstantCharge Transition Voltage Mode Battery Voltage Maintenance charging starts VTERM VRESTART Full-Rate Current Charging Current Battery Voltage Restart VFULLRATE Charging Current End-of-Charge Current Level IPRECHG Time Figure 4. Charging Cycle Voltage and Current Plots Battery Charger to battery BATT + - Power Routing Switch VIN_CHG System Supply to the system VDD Figure 5. Charger Power Structure 18 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Input out of range (Input > VIN_OV ) OR (Input < VIN_LV ) CHARGER OFF (Ichg = 0) Input in range (VIN_OV > Input > VIN_LV ) AND wait 40ms for charger services Restart condition STANDBY (Ichg = 0) PRECHARGE (max Ichg = Iprechg) VBATT > VFULLRATE EOC condition OR full charge timeout Precharge timeout BAD BATTERY (Ichg = 0) VBATT < VFULLRATE FULL CHARGE (max Ichg = IBATT) Deglitching times: - Charger input in range, rising edge: 50 ms - Charger input in range, falling edge: 2 us - Vfullrate, Vrestart, Ieoc: 400 ms Figure 6. Charger Charging Cycle Operation Description SWITCH ON PMU enters standby mode (configuration option) PMU exits from standby mode OR charger input removed SWITCH OFF Figure 7. Charger Internal Power Switch Operation Description When Charger is Off Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 19 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com SWITCH ON Start of the first charging cycle after input connection OR PMU in standby mode OR Switch OFF command x x x x x BATT and VDD connected through switch BATT regulator: disabled VDD regulator: enabled VDD regulator current: up to IBAT No current sharing VDD voltage below 3.3V OR VDD regulator current = IDCIN OR High Current Mode enabled OR Switch ON command x x SWITCH OFF x x x x BATT and VDD separated by switch BATT regulator: enabled during precharge and full charge BATT regulator current: up to IBAT in full charge, up to IPRECHG in precharge VDD regulator: enabled (disabled only if PMU in standby and VDD configured off in standby) VDD regulator current: up to IDCIN Current sharing activated Figure 8. Charger Internal Power Switch Operation Description When Charger is On 20 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Charge Pump cp CHGIN cp LDO Curlim Selection + LDO Curlim Amplifier VDD cp vref LDO Output Voltage Selection + - LDO Error Amplifier Adaptive Current Sharing Battery Temperature Monitor PMU Internal Supply Discharge Current Measurement CHGIN vref cp Charge Current Selection + - I Error Amplifier BATT cp vref BATT Termination Voltage Selection + - V Error Amplifier cp Temperature Selection & Temperature Sensor + - End of Charge Current T Error Amplifier Restart Voltage Fullrate Threshold Voltage System Voltage Monitor Input Voltage Control CC to CV Mode Transition Figure 9. Charger Block Diagram Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 21 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com CC/CV transition point IBATT IBATT 50 m internal resistance slope Charge Current in CV mode limited by 50 m Charge Current limited by CC mode VTRM VBATT Figure 10. Charger CC to CV Mode Transition Diagram CHARGER ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ =-25C to +85C. Unless otherwise specified, the following applies for VVIN_CHG = 5.0V. (1) (2) Symbol Parameter Test Conditions Typ Charger input is turned off if voltage is above this threshold. 6.95 VOV Over-Voltage Protection threshold VVIN_CHG AC input voltage operating range VOK_CHG VIN_CHG OK trip-point VTERM VTERM voltage tolerance default VTERM = 4.2V, ICHG = 50 mA VTERM is measured at 10% of the programmed ICHG current Programmable full-rate charge current 6.5V VVIN_CHG 4.5V V BATT < VVIN_CHG - VOK_VIN_CHG V FULL_RATE < VBATT < VTERM (1) ICHG Full-rate charge current tolerance VVIN_CHG - VBATT (Rising) 300 VVIN_CHG - VBATT (Falling) 90 7.4 V 4.5 6.5 V mV -0.35 +0.35 -1 +1 50 1200 % mA 100 75 125 ICHG = 400 mA 400 350 450 600 540 660 1100 1040 1160 50 35 65 mA -9 5 % 2.3 A ICHG = 600 mA (2) 2.2V < VBATT < VFULL_RATE IDCIN Input current limit IDCIN = 435 mA; IBATT = 200 mA IVIN_CHG_MAX Maximum input current in high-current mode VVIN_CHG - VDD 0.8V VFULL_RATE Full-rate qualification threshold VBATT rising, transition from pre-charge to full-rate charging (2.8V option selected) VRESTART Restart threshold voltage From VTERM voltage (4.2V, -150 mV options selected) 22 6.55 (2) Pre-charge current (1) (2) Max (2) IPRECHG (2) Unit Min ICHG = 100 mA ICHG = 1100 mA (1) Limit (2) mA 2.8 2.7 2.9 V -150 -180 -120 mV All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Specified for output voltages no less than 1.0V Specified by design. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ =-25C to +85C. Unless otherwise specified, the following applies for VVIN_CHG = 5.0V.() () Symbol TREG Parameter Regulated junction temperature DETECTION AND TIMING Test Conditions 115C option selected (2) Typ Limit Min Max Unit 115 C ms (2) TPOK Power OK deglitch time VCHG > VBATT + VOK_CHG 30 TPQ_FULL Deglitch time Pre-charge to full-rate charge transition 210 ms Pre-charge mode (default setting) 45 mins CC mode/CV mode (default setting). 5 Hrs 210 ms TCHG Charge timer TEOC Deglitch time for end-ofcharge transition BUCK INFORMATION The LP3925 has integrated three high efficiency step-down DC-DC switching buck converters that deliver a constant voltage from a single cell battery to portable devices. Using voltage mode architecture with synchronous rectification, the buck has the ability to deliver up to 800 mA depending on the input voltage and output voltage, ambient temperature, and the inductor chosen. There are two modes of operation depending on the current required - PWM (Pulse Width Modulation), ECO (ECOnomy) mode. The device operates in PWM mode at load currents of approximately 50 mA (typ.) or higher. Lighter output current loads cause the device to automatically switch into ECO mode for reduced current consumption and a longer battery life. 2 buck regulators are capable of DVS control. Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown protection. Only three external power components are required for implementation. BUCK CIRCUIT OPERATION The switching buck converter operates as follows. During the first portion of each switching cycle, the control block in the LP3925 turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VINVOUT)/L, by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of -VOUT/L. The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. PWM OPERATION During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is introduced. While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 23 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com Figure 11. Typical PWM Operation INTERNAL SYNCHRONOUS RECTIFICATION While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. CURRENT LIMITING A current limit feature allows to protect itself and external components during overload conditions. PWM mode implements current limit using an internal comparator that trips at 1100 mA (typ.). If the output is shorted to ground and output voltage becomes lower than 0.3V (typ.), the device enters a timed current limit mode where the switching frequency will be one fourth, and NFET synchronous rectifier is disabled, thereby preventing excess current and thermal runaway. ECO MODE OPERATION The buck switches from ECO state to PWM state based on output load current. At light loads (less than 50mA), the converter enters ECO mode. In this mode the part operates with low Iq. During ECO operation, the converter positions the output voltage slightly higher (+30mV typ.) than the nominal output voltage in PWM operation. The more complete understanding of an ECO mode operation can be derived from diagram in Figure 12. PWM threshold peak current limit ECO Comparator FB Current Sensing comp + + - PWM pwm SW SW Control SW Err Amp Figure 12. Typical ECO Operation Power FETs are controlled by "SW Control" which is a combination of `comp' and `pwm' signals, dependent on `PWM threshold' level. "ECO Comparator" is a simple comparator with hysteresis. "Err Amp" and "PWM" are error amplifier with a ramp generator. `PWM threshold' is current sensing at PFET, that lets control logic know which input has to be used. In low load condition `comp' is used and in high load condition `pwm' is used. Once Vout voltage level gets too small, then in low load condition (ECO mode) the "ECO Comparator" triggers and "SW Control" opens PFET (wide pulse at SW pin; see Figure 3). The wideness of that pulse is determined by "ECO comparator" which has a built in hysteresis. Normal in ECO mode after that wide pulse has passed no action should be taken, until next "ECO Comparator" triggering. If some other condition (PWM threshold/Current limit) is fulfilled, then buck enters PWM mode. 24 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 If `peak current limit' which is a current sensing signal for PFET's switch peak currents triggers, then buck enters PWM mode from the next clock pulse. Peak current sensing is reset at the beginning of every clock pulse. Once in PWM mode, buck will stay there at least 32 clock pulses and if `PWM threshold' indicates that buck should be operating in ECO mode, it will return into ECO mode. This is what actually happens on Figure 3 during wide ECO mode pulse. (The reason behind that is in high peak current during the time PFET is opened. Rough example: I= c v t -5 = -2 10 5 10 -6 0.35 10 = 1.4A Figure 13. Buck's Switches Controlling Diagram where COUT = 10 F, ripple V = 50 mV and PFET open time = 350 ns). Figure 14. Typical ECO Operation The output voltage ripple is slightly higher in ECO mode (30 mV peak-peak ripple typ.) Figure 15. Typical Ripple in ECO Mode BUCK OUTPUT VOLTAGE SELECTION The selection of the bucks' output voltages can be done by writing a specific code into the control registers (addr. 0x10 ... 0x18). The required voltage can be calculated from the following equation: BUCK (X)_VOUT(Y*)(mV) = 600 mV + code(dec)/127 * 2200 mV (2) Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 25 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com Where Y* denotes a number, which corresponds to the DVS control code. If DVS is not in use, then VOUT0 is used. 1-bit DVS uses VOUT0 and VOUT1 and 2-bit DVS uses VOUTs 0 to 3. EXTERNAL COMPONENT SELECTION Default values for external components of LP3925 bucks are input and output capacitances CIN = COUT = 4.7 F and inductor L=1H whit the lowest possible DCR (less than 50 m). Below is the table with the selection of suitable inductors for the application. With the careful selection of the output components the performance of the buck will not degrade in stability, ripple, load regulation and transient aspects. The inductor current (IL) and output voltage (VOUT) ripples are directly dependent on the external components. Current ripple is mainly dependent on the inductance L (VIN IL RPdson VOUT IL DCR) VOUT AIL = L VIN fSW (3) where fSW is the buck's switching frequency and RPdson is the drain to source resistance of the PMOS power switch. Voltage ripple on the other hand has 2 main components. One dependent on output capacitance: AVOUT_C = 'iL COUT fSW 8 (4) The other is due to capacitor's ESR 'VOUT_ESR = ESR 'iL (5) The resulting RMS ripple is AVOUT = AV 2 2 OUT_C + AV 2 OUT_ESR (6) For example if use the combination L = 0.47 H (DCR = 50 m) and COUT = 30 F (ESR = 10 m), when VIN = 3V and VOUT = 1.8V with load current of 600 mA, the theoretical peak to peak current ripple should be: (3 - 0.6 * 0.16 - 1.8 - 0.6 * 0.05) * 1.8 = 342 mA AIL = 0.47 * 3 * 4 (7) while the RMS peak-to-peak voltage ripple should be in the region of: AVOUT = ( 8 2 342 ) + (0.01 30 4 2 342) = 4 mV (8) DVS CONTROL DVS allows a buck regulator to step between pre-programmed voltage values, using multifunctional pins as selectors. DVS is supported for Buck1 and Buck2. They can have up to 4 pre-programmed values, which are set in registers BUCKn VOUTn. Multifunctional pins can be set as single DVS selectors (1 selecting signal) or dual DVS selectors (2 selecting signals). DVS-controlling pins must be set as Buck1 DVS (code 0101) or Buck2 DVS (code 0110) pins in their control registers (named GPIOnn). Any multifunctional pin can be used as a single DVS signal. The signal selects between VOUT0 (input low) and VOUT1 (input high). Dual DVS signals can only be predetermined pairs, the function description can be seen in Table 3. 26 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Table 3. Dual DVS Control Table for Bucks 1 and 2 OSC_32KHZ RSENSE SIM_RST_IN SIM_CLK _IN SIM_DATA SIM_RST SIM_CLK SIM_IO TCXO1_I TCXO1_O TCXO2_I TCXO2_O OE_N DATA/VP SE0/VM RCV SPND INP1 BUCK1,2 VOUT INP2 SINK1 SINK2 SINK3 0 0 VOUT0 0 1 VOUT1 1 0 VOUT2 1 1 VOUT3 BUCK TYPICAL PERFORMANCE PLOTS Efficiency (VIN = 3.0V, VOUT = 1.2V) Efficiency (VIN = 3.6V, VOUT = 1.2V) Efficiency (VIN = 4.2V, VOUT = 1.2V) Efficiency (VIN = 3.0V, VOUT = 1.76V) Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 27 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 28 www.ti.com Efficiency (VIN = 3.6V, VOUT = 1.76V) Efficiency (VIN = 4.2V, VOUT = 1.76V) Buck1 Fast Rise (1s) Buck2 Fast Rise (1s) Buck3 Fast Rise (1s) Buck1 Slow Rise (5s) Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Buck2 Slow Rise (5s) Buck1 Slow Rise (5s) BUCK ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -25C to +85C. Unless otherwise specified, the following applies for VBATT = 3.6V. (1) Symbol VFB Parameter Feedback voltage Test Conditions Limits Typ Unit Min Max PWM Mode, No load VOUT = 1.1V to 1.8V -3 3 % PWM Mode, No load VOUT = 0.75V to 1.0V -10 10 mV IQ_ECO ECO mode IQ ECO Mode, FB = VIN No switching, sleep mode 25 RDSON (P) Pin-pin resistance for PFET VIN = VGS = 3.6V IOUT = 200 mA 160 250 m RDSON (N) Pin-pin resistance for NFET VIN = VGS = 3.6V IOUT = -200 mA 115 180 m ILIM Switch peak current limit Open loop; BuckX = 11 1475 mA tSTARTUP Startup time from shutdown IOUT= 0 VOUT 0 to 97% (1) 65 s FSW Switching frequency PWM Mode 4 (1) (1) A 3.6 4.4 MHz All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 29 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com LDO INFORMATION There are altogether 15 LDOs in LP3925 grouped as: * General-type "PERFECT" LDOs; * WILO-type LDOs; * MICRO-PWR LDO; and * USB LDO. All LDOs can be programmed through serial interface for different output voltage values which are summarized in the "Control Register Bit Description" tables. At the PMU power on, LDOs start up according to the selected startup sequence and the default voltages. See section Power-on and Power-On Sequences for details. For stability all LDOs need to have external capacitors COUT connected to the output with recommended value of 1F . It is important to select the type of capacitor which capacitance will in no case (voltage, temperature, etc) be outside of limits specified in the LDO Electrical Characteristics. The description of different LDO types follow, except for the RTC description in the following section. GENERAL-TYPE "PERFECT" LDOs The general "PERFECT" LDOs are optimized to supply both analog and digital loads having ULTRA LOW NOISE (10 VRMS for IOUT > 5mA) and excellent PSRR (75 dB at 10 kHz) performance. They can be programmed through the serial interface for different output voltage values. For fast discharging of the output capacitors in shutdown, an internal 300 pulldown resistor to ground can be set via program control. In sleep mode quiescent current is lowered to 5A for energy saving; in this mode these LDOs should not be loaded by more than 3-5mA of output current. The innovative design of these general type LDOs reduces the sensitivity to the placement of the output capacitor. These general purpose LDOs do not need the output capacitor to be placed as close to the PMU as is the case for normal LDOs. If a (1F or more) capacitor is attached to a circuit load there is no need to place an output capacitor at the PMU. WILO-TYPE LDOs Wide Input Low Output (WILO) LDOs. The WILO-type LDO is optimized for wide range supply and low output voltage. It has good dynamic performance to supply different fast changing (digital) loads. For proper operation, an input voltage of more than 2V is necessary. Hence, voltage drop on pass transistor (dropout voltage) will always exceed 0.45V and is independent of output current (in specified current range). For fast discharge of the output capacitors in shut down, an internal 300 pulldown resistor to ground can be set via program control MICRO-PWR LDO This LDO is primarily used for internal supply purposes and fixed to 1.8V, but may deliver up to 30 mA of current also externally. This LDO is ON even in Standby mode (with total PMU current consumption about 2A) and user may use it to supply some backup/always on system(s). USB LDO USB LDO is a high voltage LDO that uses VIN_CHG as a supply. It is used as a supply for D+ and D- buses as well as the VTRM output. It has a 28V over voltage protection capability. Regulator provides 45 dB PSRR at 10 kHz on entire voltage selection range except 4.85V option. Here it is 30 dB and is due to small distance to supply. 30 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 GENERAL LDO ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (2) Symbol Parameter Test Conditions VOUT Output voltage accuracy IMAX Output current rating ISC Output current limit ISLEEP Output current in sleep mode IQ Quiescent current in sleep mode VDO Dropout voltage VOUT = 3V; IOUT = IMAX (2) Line regulation VOUT +0.5V VIN 4.5V IOUT = IMAX Load regulation 1mA IOUT IMAX eN Output noise voltage PSRR LDO No. IOUT = 1mA, VOUT = 2.0V Typ 1-10 Limits Min Max -2 2 -3 3 4,8 80 1-3, 5-7, 9, 10 300 Unit % mA VOUT +0.5V VIN 4.5V (1) 4,8 300 80 mA VOUT +0.5V VIN 4.5V (1) 1-3, 5-7, 9, 10 650 300 mA VOUT +0.5V VIN 4.5V 1-10 3 mA 5 A 4, 8 60 150 1-3, 4-7, 9, 10 100 200 1-10 3 mV 4, 8 0.5 mV 1-3, 5-7, 9, 10 3.5 10 Hz f 100 kHz COUT = 1F (1) 1-10 15 VRMS Power supply ripple rejection ratio f = 10 kHz, COUT = 1F IOUT = 20 mA (1) 1-10 70 dB tSTART-UP Startup time from shutdown IOUT= 0 VOUT 0 - 90% VOUT 0 - 97% 1-10 45 50 s VLOADTRANS Load transient overshoot IOUT = 0 200 mA IOUT = 0 200 mA (1) 1-10 -30 35 mV VLINETRANS Line transient, peak-to-peak VIN = 3.6 4.2 3.6; tr = tf = 30 s IOUT = 50 mA (1) 1-10 90 V VTRANSIENT Start-up transient overshoot COUT = 1F, IOUT = IMAX (1) 1-10 1 COUT External output capacitance for stability 1-10 1 VOUT (2) (1) (2) (1) 0.6 mV 30 mV 20 F All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 31 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com WILO-TYPE LDO ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (3) (4) Symbol Parameter Test Conditions LDO No. Typ VOUT Output voltage accuracy IOUT = 1mA, VOUT = 2.0V 11-13 ISC Output current limit VOUT = 0V 11-13 600 IMAX Output current rating VDO Dropout voltage VOUT = 3V; IOUT = IMAX (1) 11-13 150 Line regulation VOUT +0.5V VIN 4.5V IOUT = IMAX 11-13 2.5 Load regulation 1mA IOUT IMAX 11-13 3 VOUT Limits Min Max -2 2 -3 3 300 Unit % mA 300 mA 250 mV mV Quiescent current in normal mode (2) IQsleep Quiescent current in sleep mode (2) eN Output noise voltage 10 Hz f 100 kHz COUT = 1F, IOUT = 20 mA VOUT = 1.8V (2) 11-13 85 VRMS PSRR Power supply ripple rejection ratio f = 10 kHz, COUT = 1F IOUT = 20 mA (2) 11-13 60 dB tSTARTUP Startup time from shutdown COUT = 1F, IOUT = IMAX 11-13 35 VTRANSIENT Startup transient overshoot COUT = 1F, IOUT = IMAX 11-13 COUT External output capacitance for stability IQnormal (3) (4) (1) (2) 32 17 11-13 A 4 11-13 1.0 s 0.5 30 mV 20 F All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified for output voltages no less than 1.0V Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Specified by design. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 MICRO-PWR LDO ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (3) Symbol Parameter Test Conditions Typ Limits Min Unit Max VOUT Output voltage accuracy IOUT = 1mA, VOUT = 1.80V 1.8 V IMAX Maximum output current VOUT = 1.8V 30 mA ISC Output current limit VOUT = 0V 220 mA Line regulation VOUT +0.5V VIN 4.5V IOUT = IMAX 2 Load regulation 1mA IOUT IMAX 1 Power supply ripple rejection ratio f = 10 kHz, COUT = 1F IOUT = 20 mA (1) VOUT PSRR 45 (1) tSTARTUP Startup time from shutdown COUT = 1F, IOUT = IMAX VTRANSIENT Startup transient overshoot COUT = 1F, IOUT = IMAX (1) COUT External output capacitance for stability (3) mV dB 200 1.0 s 0.6 75 mV 20 F All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. (1) USB LDO ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VVIN_CHG = 5.0V. (2) Symbol Parameter Test Conditions Typ Limits Unit Min Max 3.15 3.45 VOUT Output voltage accuracy IOUT = 1mA, VOUT = 3.30V IMAX Maximum output current VOUT = 3.30V 50 mA ISC Output current limit VOUT = 0V 300 mA Dropout voltage IOUT = IMAX USB LDO VOUT = 4.85V 330 mV Line regulation VOUT +0.5V VIN_CHG 6.5V IOUT = 10 mA, VOUT = 4.85V 5 Load regulation 1mA IOUT IMAX VOUT = 3.3V 6 Power supply ripple rejection ratio f = 10 kHz, COUT = 1F IOUT = 20 mA (2) VDO VOUT PSRR tSTARTUP Startup time from shutdown COUT = 1F, IOUT = IMAX VTRANSIENT Startup transient overshoot COUT = 1F, IOUT = IMAX COUT External output capacitance for stability (2) (1) (2) (1) mV 45 (2) V dB 15 s 250 mV 1.0 0.6 20 F All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Specified by design. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 33 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com USB TRANSCEIVER USB TRANSCEIVER USB transceiver complies with USB 2.0 specification for full-speed (12Mb/s) device and low-speed (1.5Mb/s) device operation. The transceiver also supports USB Charger Detection by "Battery Charging Specification Revision 1.0 Mar 8, 2007". The transceiver includes internal 1.5 k pullup resistor and it is supplied from USB LDO. USB transceiver can be configured to 3-pin, 4-pin or 5-pin interface. If "USB transceiver not used" is configured, then USB transceiver is disabled in all circumstances, D+ and Dpins are Hi-Z and also 1.5 k pullup resistor is disconnected. USB LDO has separate enable control and can be used also if "USB transceiver is not used". VTRM USB LDO VIN_CHG 1.5 kO 1.5 kO USB Charger Detection LP3925 logic Interface to LP3925 logic VDAT_SRC + IDAT_SINK VDAT_REF D+ D- USB Tranceiver 28: LDO 1 28: OE_N* SPND* + PP Interface DATA / VP * - SE0 / VM * RCV * GND_USB Figure 16. USB Transceiver Block Diagram USB Transceiver enable is controlled by register 0x41 (USB XCVR CONTROL bits) and 0x36 (bit ALLOW USB XCVR IN SLEEP). 34 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 If AUTOMATIC USB DETECTION bit is set 1 then in any circumstances the USB transceiver stays disabled until USB Charger Detection is completed. USB Speed is determined by bit USB SPEED in register 0x4D: USB SPEED 1 - Full Speed (12 Mb/s) 0 - Low Speed (1.5 Mb/s) USB CHARGER DETECTION USB Charger Detection works according to "Battery Charging Specification Revision 1.0 Mar 8, 2007" published by USB-IF. To enable USB Charger detection: (1) bit AUTOMATIC USB DETECTION in register 0x4D should be set 1; and (2) Charger should be enabled. After VIN_CHG voltage was detected to be high enough to start charging USB Charger Detection waits 900 ms and then checks D+ and D- for 100 ms. The detection result can be read form register 0x8D: USB DETECTION DONE 1- USB Charger Detection completed 0 - USB Charger Detection is in progress or charger is disabled or there is no enough voltage on VIN_CHG. USB DETECTION RESULT 1 - USB Charger detected 0 - USB host detected If AUTOMATIC USB DETECTION is enabled (bit is set 1) then USB Transceiver stays disabled in all circumstances until USB Charger detection is completed. USB Charger Detection block gets supply from VTRM. To have detection result correct then USB_LDO should be enabled VTRM USB LDO VIN_CHG 1.5 k: 1.5 k: USB Tranceiver 28: LDO1 D+ OE_N* OE_N 28: D- DATA /VP* SE0 / VM * DATA / VP + PP Interface - SE0 GND_USB Figure 17. USB Transceiver Configured to 3-Pin Interface Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 35 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com Table 4. INTERFACE PINS DATA USB Interface data input/output SE0 USB interface single ended 0 input/output OE_N USB Output Enable, active low Table 5. TRUTH TABLE FOR 3-PIN INTERFACE Transmitting OE_N=0 Inputs Receiving OE_N=1 Outputs Inputs Outputs DATA/VP* SE0/VM* D+ D- D+ D- DATA/VP* SE0/VM* 0 0 0 1 0 0 previous state 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 undefined 0 VTRM USB LDO VIN_CHG 1.5 kO USB Transceiver LDO1 DATA/VP* OE_N* SE0/VM* 1.5 kO 28: VP OE_N D+ 28: VM DRCV* RCV + - GND_USB Figure 18. USB Transceiver Configured to 4-Pin Interface Table 6. INTERFACE PINS VM USB interface minus input/output VP USB interface plus input/output RCV Receiver data - single ended output from USB differential lines. OE_N USB Output Enable, active low. 36 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Table 7. Controlling the Transceiver OE_N VP VM FUNCTION 0 Input D+ = VP Input D- = VM Transmitting 1 Output D+ = VP Output D- = VM Receiving VTRM USB LDO VIN_CHG 1.5 kO 1.5 kO USB Transceiver LDO1 28: VP DATA/VP* OE_N OE_N* D+ 28: VM SE0/VM* D- + RCV RCV* - SPND SPND* GND_USB Figure 19. USB Transceiver Configured to 5-Pin Interface Table 8. Interface Pins VM USB interface minus input/output VP USB interface plus input/output RCV Receiver data - single ended output from USB differential lines. OE_N USB Output Enable, active low. SPND USB suspend mode control input. A logical high will power down the differential receiver; VM and VP will remain active with reduced power consumption. Table 9. Controlling the Transceiver in 5-Pin Configuration SPND OE_N 0 0 Driving D+/D- Active RCV Input VP/VM Normal Transmitting Function 0 1 Receiving Active Output Normal Receiving 1 0 Driving USB_RCV_OFF in 0x6B Input Low-Power Transmitting 1 1 Receiving USB_RCV_OFF in 0x6B Output Low-Power Receiving Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 37 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com USB CHARGER DETECTION ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VVIN_CHG = 5V. (1) Symbol Parameter VDAT_SRC Data source voltage VDAT_REF Data detect voltage IDAT_SINK Data sink current (1) Test Conditions Typ. Load Current = 200 A 0.15V < VD- < 3.6V Limits Unit Min Max 0.6 0.5 0.7 0.325 0.25 0.4 100 50 150 V A All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. USB TRANSCEIVER ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V, VTRM = 3.3V. (1) Symbol Parameter Test Conditions Typ VBUS VIN_CHG supply voltage VIN_CHG pin works as USB VBUS pin IBUS VIN_CHG pin quiescent current Low-speed VIN_CHG pin works as USB VBUS pin USB Transmitter Receiving USB_LDO enabled, charger OFF Limits Unit Min Max 4.2 5.5 V 2.5 mA 10 A 1.1 Transceiver DC Characteristics ILO Hi-Z state data line leakage 0V < V < VTRM D+ if Low Speed; D- if High Speed, OE_N = 1. -10 VDI Differential input sensitivity |(D+)-(D-)|, VIN = 0.8V - 2.5V 200 VCM Differential common-mode range Includes VDI Range (1) 0.8 Single-ended receiver threshold high VSE mV 2.5 V 2.0 V Single-ended receiver threshold low 0.8 Receiver hysteresis 100 mV VOL Static output low OE_N = 0, RLOAD = 1.5 k to 3.6V 0.3 VOH Static output high OE_N = 0, RLOAD = 15 k to GND 2.8 3.6 VTRM Termination voltage IOUT = 0, USB_LDO programmed to 3.3V 3.15 3.45 RTRM Pullup resistance CIN Transceiver capacitance Pin to GND ZDRV Drive output resistance D+, D- steady-state drive, IOUT = 15 mA from regulator 1.5 k (1) (1) V 20 pF 28 44 Low-Speed Driver Characteristics tR Transition rise time CLOAD = 50-600 pF (1) 75 300 tF Transition fall time CLOAD = 50-600 pF (1) 75 300 tR/tF Rise/fall time matching R/tF 80 125 (1) ns % Full-Speed Driver Characteristics tR Transition rise time CLOAD = 50 pF (1) 4 20 tF Transition fall time CLOAD = 50 pF (1) 4 20 (1) (1) 38 ns All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V, VTRM = 3.3V. () Symbol tR/tF Parameter Test Conditions Rise/fall time matching R/tF Typ (1) Limits Unit Min Max 90 110 % TCXO BUFFERS The TCXO Buffer amplifies the 20 MHz sine wave from an external TCXO and shapes it into a buffered square wave clock signal with controlled rise and fall times. The buffer input connected to an internal decoupling capacitor. The output clock signal has a default slew rate of 325 V/s with an external load capacitance of 12.5 pF. The slew rate can be adjusted by changing the two-bit control data in the control register. This may be necessary if the actual load capacitance is considerably higher or the clock slew rate needs to be slower for EMC reasons. If TCXO buffers are enabled, then they need some time to reach a working point. During this time the output signal can have an undesirable shape. To avoid unwanted signals, "TCXO in wait" control signals allow to set the time delay before enabling TCXO buffer output. "TCXO out strength" signals modify buffer output drive strength. Possible values of "TCXO in wait" and "TCXO out strength" are stated in the GPIO section. Buffers are supplied from LDO1. TCXO BUFFER ELECTRICAL CHARACTERISTICS (2) Unless otherwise noted VBATT = VDD = 3.6V, CBYP_CHG = 1F, CFB_CHG = 10 F. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (3) Symbol Parameter Test Conditions Typ (1) VIN Input voltage level VOH High-level output voltage DC at 1A 2.5 VOL Low-level output voltage DC at 1A 0.1 TP Propagation delay CL = 13 pF TTT Output transition time CL = 13 pF (10% and 90% level) VSR Output slew rate CL = 13 pF CIN (2) (3) (1) Unit Max 750 (1) (1) (1) (1) Input capacitance Limits Min mVP-P 2.4 V 0.2 12 ns 7 325 2 200 450 V/s 10 pF For warm-up time and driving strength, refer to multifunctional pins section. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. BACKUP BATTERY CHARGER Backup battery charger (BBC) is intended for charging an external coin battery. Its output is connected to VCOIN-pin. It consists of Voltage Limited Current Source with 1k output resistor. By default it is always on. It is possible to turn backup battery charger off via registers. VCOIN - voltage limit and ICOIN - current source values are also programmable via registers (the possible values are stated in Backup battery charger selection table). BBC has a reverse current protection. VCOIN-pin voltage can be measured by an internal ADC. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 39 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com IVCOIN ICOIN 1 k: slope Charge Current limited by CC mode Charge Current limited by 1 k: VCOIN VVCOIN Figure 20. BBC IU Characteristics MOMENTARY POWER LOSS When power is removed from the LP3925 PMU and MPL function is enabled (register 0x81) then Momentary Power Loss (MPL) timer starts as unexpected power down has occurred. This timer is set to the maximum duration allowed for a momentary power loss (register 0x81). If power is restored before the timer expires, then MPL block informs LP3925 control logic about MPL-event. The MPL circuit is powered from VCOIN-pin. MPL timer uses 32.786 kHz RTC crystal oscillator for time base. Host processor needs to enable the MPL function every time the device is powered up. 32.768 kHz CRYSTAL OSCILLATOR There are two options for implementing the 32.768 kHz oscillator: 1. 1. An external crystal that is connected between XIN and XOUT. The external crystal ESR must not exceed 100 k; if this value is exceeded the circuit may never start oscillating. 2. 2. An external oscillator module could be used by connecting the module output directly into XIN. When using an external oscillator module, the XOUT pin should be unconnected. Pins XIN and XOUT are not able to drive external load. Oscillator output is buffered to pin OSC_32KHZx Note. Oscillator is powered by LDO1, thus before it is up, the oscillator will not start. 40 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 BACKUP BATTERY CHARGER ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (2) Symbol Parameter Test Conditions VCOIN Voltage Limit ILOAD = 1A; VCOIN programmed to 3.00V ICOIN Charging Current VCOIN pin shorted to GND ICOIN programmed to 200 A RVCOIN Internal Series Resistor ILEAK Reverse leakage current VRTC pin current = 0 Charger Ground Current ILOAD = 0. 2.5 Load Regulation ILOAD = 0. 0.5 IGND (2) Limits Typ 1.0 Unit Min Max -3 +3 % -20 +20 % 0.5 1.6 k 10 A All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. REAL TIME CLOCK The Real Time Clock (RTC) block is used for time tracking in any chip condition. It uses 32 kHz crystal oscillator for accurate timekeeping and is supplied either from system supply in normal condition or from coin battery when the PMU has no main power. The RTC gets power from VCOIN, with minimum operation above 1.9V. This RTC has following features: * Accurate time counting with fine-grained correction for long-term accuracies; * Calendar for years 2000 - 2099 with leap year compensation and automatic weekday calculation; * Two highly customizable alarms; and * Data in software-friendly binary format. VCOIN VCOIN<1.2V disable VCOIN>1.2V enable Level shifters for BBC Backup Battery Charger RTC MPL Dedect if OK signal from XOSC, if not OK signal, then give 32 kHz to output XOSC 32 kHz XIN XOUT Note 1: If main supply drops, then interface gets locked automatically. LP3925 liogic control unlocks the interface on startup. to OSC_32 KHZ pad buffer Control from registers Level shiters with lock/unlock Interface Note 1 RC oscillator Data from registers Level shifters with enable Clock from internal Data from registers Figure 21. RTC Functional Block Diagram Calendar and alarm data is presented in following format: Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 41 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com Table 10. Calendar and Alarm Data Time Unit Register Data Represented Values Seconds 000000 - 111011 0 - 59 Minutes 000000 - 111011 0 - 59 Hours 00000 - 10111 0 - 23 Day of Month 00001 - 11111 1 - 31 Month 0001 - 1100 January - December Year 0000000 - 1100011 2000 - 2099 Weekday 0000001 - 1000000 (1-hot code) Monday - Sunday RTC calendar and alarm registers are user-writable, except for calendar weekday registers, which are calculated automatically and are read-only. All RTC registers are in RTC power domain. The registers are zeroed, if RTC is powered up. As long as RTC is supplied, the alarm registers will hold the written data and the calendar will keep track of time. Writing data to a calendar register will initiate a calendar write sequence, which will last 3ms. During this time the register's data should not be read, because it may not be accurate. Alarms allow creating periodical or one-time events. The result of an alarm event depends on the PMU state. If PMU is in standby, then alarm can cause PMU to start up. If PMU is in working mode, then alarm can create an interrupt. Alarm event happens if the alarm is activated (ALARM ACTIVATED bit is 1) and current RTC time matches the time in all alarm configuration registers. To exclude a time unit value from matching check, write the unit's IGNORE bit to 1. If alarm's weekday is not important or not known, then all weekday bits should be set to 1. Interrupt or PMU startup is triggered at the start of an alarm event. The RTC also has a time counting correction register. This can slightly change time counting speed to compensate for oscillator inaccuracies. Correction events happen 7 times in an hour. The maximum correction range is 241 ppm (corresponds to code 127) and one step size is approximately 1.9 ppm. USIM INTERFACE LP3925 includes a SIM/RUIM card interface level-shifter function. This can be used, if the processor I/O voltage and SIM card I/O voltage have different values. The interface includes pins for 3 signals: reset, clock and data. Reset and clock are unidirectional control signals, going from the processor to the SIM card. Data signal is bidirectional. The SIM card side of the level shifter is always supplied by LDO8. The processor side supply is user-selectable between Buck2, LDO1 and LDO11. If the level shifter is enabled, then the supplies on both sides must be 1.5V or higher to ensure proper operation. 42 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 USIM LEVEL TRANSLATOR ELECTRICAL CHARACTERISTICS Unless otherwise noted, CLDOx = CVIN_CHG+CVBUS+CVTRM = 1F. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (1) Symbol Parameter VILS Input low threshold VIHS Input high threshold VOLS Output low level VOHS Output high level RINPU SIM_IO pullup resistor VIL_SIM_IO Input low VIH_SIM_IO Input high VOL_SIM_IO Output low level when SIM_DATA=GND VOH_SIM_IO Output high level RSPU SIM_DATA pullup resistor VIL_SIM_DATA Input low VIH_SIM_DATA Input high Test Conditions Typ VOH_SIM_DATA Output high level Max Unit V 0.75* VLDO1 0.25* VLDO8 V 0.75* VLDO8 10 K 0.3 VDD-0.6V SIM_IO 0.25* VLDO8 V 0.75* VLDO8 20 13 K 0.3 0.75* VLDO1 SIM_DATA, LDO1 supply selected Output low level when SIM_IO=GND Min 0.25* VLDO1 RST_IN, CLK_IN logic inputs, LDO1 supply selected SIM_RST, SIM_CLK logic outputs VOL_SIM_DATA Limits V 0.25* VLDO1 0.75* VLDO1 Timing Clock frequency (1) (1) (1) 20 5 MHz All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 43 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com LDO1 LDO8 LDO11 BUCK2 SIM LS SUPPLY SELECT 1.8V 20k 10k SIM_DATA SIM_IO SIM_CLK_IN SIM_CLK SIM_RST_IN SIM_RST Figure 22. SIM Interface Level Shifters COMPARATORS Two general purpose comparators are available, which can be used for detecting the plugging of external accessories or other events. Voltage comparators are available on multifunctional pins INP1 and INP2. 8 comparison thresholds are available between 400 mV and 2400 mV, the values can be found in the multifunction pins section. Comparator state is available from registers as a read-only bit, or from multifunctional pins as a direct data output. It is also possible to generate an interrupt every time the comparator state changes. COMPARATOR ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (2) Symbol Parameter Test Conditions Typ VTH Input threshold voltage Default setting 0.6 VTH2 Input threshold voltage 2 Default setting 1 IIL Input leakage current INP1, INP2 0 VINPUT VVIN1. (2) Limits Min Unit Max V -1 1 A All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. ADC LP3925 is equipped with a 12-bit ADC that has 8 inputs for measuring charging current, discharge current, battery voltage (measuring at BATT pin), backup battery voltage, charger input voltage, VDD, temperature and external signal through GPIO. The inputs are scaled linearly to adapt the voltage/current range of the source to the input voltage range of the A/D core. 44 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 The ADC is clocked by the internal 4MHz system clock. The conversion result is available in the registers 0x88 and 0x89 in 3ms after the setting of the ADC CONV START bit in the 0x87 Register. The ADC will automatically enter power save mode if conversions are not performed. A/D CONVERTER DATA AND CONTROL REGISTERS Two read only registers 0x88 and 0x89 provide access to the a/d conversion result. 8 most significant bits of the data can be accessed in one read cycle. The Read/Write 0x87 register allows starting the conversion, source selection and output format selection. Setting the ADC CONV START bit in the control register starts a new A/D conversion. Setting ADC_FORMAT bit to 1 allows throwing out the MSB and shifting the result 1 bit left. This can be used if result's MSB is known, to get more data with one register read. BATTERY DISCHARGE CURRENT MEASUREMENT The discharge current is measured indirectly by measuring the voltage drop produced by discharge current on the Rsense. The calculation of the current value is done by equation below: VSNS IBATT (A) = code(dec) * 4095 * RSENSE (9) The value of the appropriate VSNS (so that the maximum code would correspond to 1.2A) can be chosen in reg.0x19. That is if RSENSE = 100 m, the VSNS should equal 120 mV. JUNCTION TEMPERATURE MEASUREMENT Temperature measurement is performed in the rage of +390C...-275C which means that the following equation is valid for calculating the chip's junction temperature: TEMP(C) = 390C (code(dec) * 0.16C) (10) OTHER ITEM CURRENT VOLTAGE MEASUREMENT Full_Scale_Value V(or I)= code(dec) * 4095 (11) For example: If ADC input SEL is set as 0011, it will measure the BATT voltage. Full_Scale_Value = 4.80V; so VBATT = code(dec) * 4.8/4095. Figure 23. LP3925 ADC Temperature Range Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 45 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com ADC ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (1) Symbol Parameter Test Conditions Typ Resolution INL Integral Nonlinearity DNL Differential Nonlinearity (1) Min Max -4 +4 -2 +2 12 (1) No missing code (1) Unit bits (1) Conversion Time (1) Limits 3 LSB ms All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. REFERENCE OUTPUT Reference Output Reference output voltage is used by the external blocks (plug-in microphone, ADCs, etc). This voltage is achieved by the reference buffer and is supplied to the REF_OUT bump. Reference buffer has a load capability of 1mA and when not used can be disabled while the output is pulled by an internal resistor to the ground. A presented diagram shows a typical application of REF_OUT signal for battery temperature measurement purpose, using an internal battery thermistor. REF_OUT 10 kO ADC3 (SE0/VM) 10 kO @ 25YC NTC in Battery Figure 24. Typical REF_OUT Battery Temperature Measurement Application Diagram REFERENCE BUFFER ELECTRICAL CHARACTERISTICS Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40C to +125C. Unless otherwise specified, the following applies for VBATT = 3.6V. (2) Symbol Parameter VREF Reference voltage accuracy ILOAD Load Current RPULL_DOWN Integral Nonlinearity (2) 46 Test Conditions Typ ILOAD = 0mA 0.3 ILOAD = 1mA 1 Limits Min % -1 400 Unit Max +1 mA k All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 UVLO OPERATION UVLO measures system voltage on pin VDD and compares it to selected voltages. The function uses 2 comparators, which are configured in register address 0x85 (possible values are stated in the table below). These comparators are combined into UVLO_N state, which can affect startup, cause shutdown or generate interrupt. The state is readable in register address 0x8E bit 2. UVLO_N state can change on following conditions: * If system voltage is lower than UVLO LEVEL1 and UVLO LEVEL2, then UVLO_N state is set to '0'. * If system voltage is higher than UVLO LEVEL1 and UVLO LEVEL2, then UVLO_N state is set to '1'. Using different values for levels 1 and 2 provides a window for voltage drops under high load working conditions. UVLO_N state '0' indicates that the voltage is below normal working range, so the system is not allowed to start up. This state can also cause the system to shut down. UVLO_N state '1' indicates that the voltage is in normal working range, so the system is allowed to start up and operate. State transition '1'->'0' causes an UVLO interrupt, which can be sent to IRQ_N output. CURRENT SINKS LP3925 provides 3 current sinks, which can sink current for LEDs, vibration motors or other external functions. Current sinks have selectable DC current value and also PWM control options. SINK1, SINK2 and SINK3 are multifunction pins, so current sink function and DC current value are selectable with respective GPIO control bits (described in the table in Multifunctional pins section). SINK1 has a 250 mA maximum current value, SINK2 and SINK3 provide up to 100 mA. If the pin is configured as a current sink with a certain current, then PWM CODE bits will switch that current on and off, according to the PWM algorithm. The smallest unit in PWM control is a time slot. The length of a time slot is set with ISINK PWM TIME SLOT SIZE bits. Smaller time slot causes faster switching, but increases non-linearity. 7 time slots form a PWM cycle. Cycle is the current sink on-off switching period, so the main PWM frequency can be calculated as: Fpwm = 1/(7*Ttimeslot). 9 cycles, which is 9*7=63 time slots, form a PWM pattern. ISINK PWM CODE bits select, during how many of these 63 time slots the current sink is active. Code 000000 means that the sink is always off. Code 111111 (63 in decimal) means that the sink is always on. Cycle = 7 time slots Time slot (1...8 es) Pattern reading in time Time slots filled by PWM code Example: PWM CODE=40 Pattern (9 cycles, 63 time slots) Figure 25. Current Sinks PWM Control Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 47 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com SUPPORT FUNCTIONS REFERENCE LP3925 has internal reference block creating all necessary references and biasing for all blocks. OSCILLATOR There is internal oscillator giving clock to the bucks and to logic control. Table 11. VVBATT = 3.6V Parameter Oscillator Frequency Typ Min Max Unit 4.0 3.9 4.1 MHz THERMAL SHUTDOWN The Thermal Shutdown (TSD) function monitors the chip temperature to protect the chip from temperature damage caused by excessive power dissipation. The temperature monitoring function has two threshold values TSD_H and TSD_L that result in protective actions. When TSD_L +125C is exceeded, then IRQ_N is set to low and "1" is written to TSD_L bit in both STATUS register and in INTERRUPT register. If the temperature exceeds TSD_H +160C, then PMU initiates Shutdown. The POWER UP operation after Thermal Shutdown can be initiated only after the chip has cooled down to the +115C threshold Parameter TSDH (1) TSDL (1) TSDL Hysteresis (1) Typ Unit 160 125 (1) C 10 Specified by design. I2C-COMPATIBLE SERIAL BUS INTERFACE INTERFACE BUS OVERVIEW The I2C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bi-directional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be connected to a positive supply, via a pullup resistor of 1.5 k, and remain HIGH even when the bus is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock (SCL). DATA TRANSACTIONS One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock's high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. 48 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 SDA SCL Data Line Stable: Data Valid Change of Data Allowed Figure 26. Bit Transfer Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process. START AND STOP The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition. SDA SCL S P START CONDITION STOP CONDITION Figure 27. Start and Stop Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle. ACKNOWLEDGE CYCLE The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pulldown the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 49 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com Data Output by Transmitter Transmitter Stays Off the Bus During the Acknowledgement Clock Data Output by Receiver Acknowledgement Signal From Receiver SCL 1 2 3-6 7 8 9 S Start Condition Figure 28. Bus Acknowledge Cycle "ACKNOWLEDGE AFTER EVERY BYTE" RULE The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the "acknowledge after every byte" rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging ("negative acknowledge") the last byte clocked out of the slave. This "negative acknowledge" still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. ADDRESSING TRANSFER FORMATS Each device on the bus has a unique slave address. The LP3925 operates as a slave device with the address 7h'xx (binary nnnnnnnn). Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address -- the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. CONTROL REGISTER WRITE CYCLE * Master device generates start condition. * Master device sends slave address (7 bits) and the data direction bit (r/w = '0'). * Slave device sends acknowledge signal if the slave address is correct. * Master sends control register address (8 bits). * Slave sends acknowledge signal. * Master sends data byte to be written to the addressed register. * Slave sends acknowledge signal. * If master will send further data bytes the control register address will be incremented by one after acknowledge signal. * Write cycle ends when the master creates stop condition. CONTROL REGISTER READ CYCLE * Master device generates a start condition. * Master device sends slave address (7 bits) and the data direction bit (r/w = '0'). * Slave device sends acknowledge signal if the slave address is correct. * Master sends control register address (8 bits). * Slave sends acknowledge signal. 50 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com * * * * * * SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 Master device generates repeated start condition. Master sends the slave address (7 bits) and the data direction bit (r/w = "1"). Slave sends acknowledge signal if the slave address is correct. Slave sends data byte from addressed register. If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register. Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. Address Mode Data Read <Start Condition> <Slave Address><r/w = `0'>[Ack] <Register Addr.>[Ack] <Repeated Start Condition> <Slave Address><r/w = `1'>[Ack] [Register Data]<Ack or NAck> ... additional reads from subsequent register address possible <Stop Condition> Data Write <Start Condition> <Slave Address><r/w = `0'>[Ack] <Register Addr.>[Ack] <Register Data>[Ack] ... additional writes to subsequent register address possible <Stop Condition> REGISTER READ AND WRITE DETAIL S Slave Address (7 bits) '0' A Control Register Add. (8 bits) Register Data (8 bits) A A P Data transferred, byte + Ack R/W From Slave to Master A - ACKNOWLEDGE (SDA Low) S - START CONDITION From Master to Slave P - STOP CONDITION Figure 29. Register Write Format S Slave Address (7 bits) '0' A Control Register Add. (8 bits) A Sr Slave Address (7 bits) R/W '1' A R/W Register Data (8 bits) A/ P NA Data transferred, byte + Ack/NAck Direction of the transfer will change at this point A - ACKNOWLEDGE (SDA Low) From Slave to Master NA - ACKNOWLEDGE (SDA High) From Master to Slave S - START CONDITION Sr - REPEATED START CONDITION P - STOP CONDITION Figure 30. Register Read Format Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 51 LP3925 SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 www.ti.com For more detailed control register information, or to order samples, please contact your local Texas Instruments sales office or visit http://www.ti.com. 52 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 LP3925 www.ti.com SNVS672C - FEBRUARY 2011 - REVISED MAY 2013 REVISION HISTORY Changes from Revision B (May 2013) to Revision C * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 52 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LP3925 53 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2018 PACKAGING INFORMATION Orderable Device Status (1) LP3925RME-A/NOPB NRND Package Type Package Pins Package Drawing Qty DSBGA YQB 81 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAG Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) -40 to 125 V030 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP3925RME-A/NOPB Package Package Pins Type Drawing SPQ DSBGA 250 YQB 81 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 12.4 Pack Materials-Page 1 3.81 B0 (mm) K0 (mm) P1 (mm) 3.81 0.76 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3925RME-A/NOPB DSBGA YQB 81 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YQB0081xxx D 0.6500.075 E RMD81XXX (Rev A) D: Max = 3.64 mm, Min = 3.58 mm E: Max = 3.64 mm, Min = 3.58 mm 4214915/A NOTES: A. All linear dimensions are in millimeters. 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NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2018, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: LP3925RME-A/NOPB LP3925RMX-A/NOPB LP3925RME-E/NOPB LP3925RMX-E/NOPB