LP3925RME-E/NOPB - Texas Instruments

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

High Performance Power Management Unit for Handset Applications

Check for Samples: LP3925

1FEATURES

2• Linear Charger With Single Input KEY SPECIFICATIONS

– USB or AC Adapter Input • Low PMU IQin Sleep Mode

– Power Routing Switch • 50-mA to 1200-mA Charging Current From AC

Adapter

– 28-V OVP on the Charger Input • 3.0-V to 4.5-V Battery Voltage

• Three High-Efficiency Synchronous Magnetic

Buck Regulators, IOUT 800 mA Each: • 150-mV (Typ) Dropout Voltage on LDOs at 300

– Two Regulators Have DVS Support • 2% (Typ) Output Voltage Accuracy on LDOs

– High-Efficiency ECO Mode at Low IOUT • Ultra Low Noise (10 µV Typ), Ultra Low IQ,

– Auto Mode ECO/PWM Switch Remote Capacitor General-Type "Perfect"

– 28-V OVP on the Charger Input LDOs

• 15 LDOs • 3% Accurate Buck Regulators up to 90%

– 10 General-Type Low-Noise LDOs: 8 x 300 Efficient

mA, 2 x 80 mA

– Three Wide-Input Low-Output (WILO) LDOs, APPLICATIONS

All Capable of Supplying up to 300 mA • GSM, GPRS, EDGE, CDMA, and 3G Handsets

– One Micro-Power LDO With IOUT 30 mA

– One High-Voltage USB LDO DESCRIPTION

– S/W Controllable Outputs The LP3925 is designed to meet the power

management requirements of the latest

– Outputs Configurable for Pulldown 3G/GSM/GPRS/EDGE cellular phones. The LP3925

• Two Comparators and Two TCXO Buffers PMU contains a single-input Li-Ion battery charger,

• USB 2.0-Compatible Transceiver (12 Mbps) 14 low-dropout voltage regulators including 3 wide-

• 12-Bit A/D Converter for Battery Management input, low-output, regulators, 3 buck regulators, a

USB Transceiver, two comparators, two TCXO

and External Monitoring buffers, SIM level shifter, 12-bit ADC, real time clock,

• Two Over-Voltage Protected Outputs for USB and backup battery charger. Programming is handled

Transceivers via an I2C-compatible high-speed Serial Interface

• Real-Time Clock With Two Alarms allowing control of program on/off conditions and the

output voltages of individual regulators, and to read

• SIM Card Level Translator status information of the PMU.

• Three Controllable Current Sinks for Keypad

LEDs It can charge and maintain a single cell Li-Ion battery

operating from an AC adapter or USB power source.

• Backup Battery Charger The Li-Ion charger requires few external components

• Thermal Shutdown With Early Warning Alarm and integrates the power FET. Charging is thermally

• Momentary Power Loss detection regulated to obtain the most efficient charging rate for

• Interrupt Request to Reduce S/W Polling a given ambient temperature.

• 81-Bump DSBGA Package A built-in Over-Voltage Protection (OVP) circuit at the

charger input protects the PMU from input voltages

up to +28V eliminating the need for any external

protection circuitry.

Buck regulators have an automatic switch to ECO

mode at low load conditions providing very good

efficiency at low output currents.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

DESCRIPTION (CONTINUED)

Buck regulators have an automatic switch to ECO mode at low load conditions providing very good efficiency at

low output currents.

General-type “PERFECT” LDO regulators provide excellent PSRR and ULTRA LOW NOISE, 10 µV typ., ideally

suited for supplying voltage to RF section.

The real-time clock/calendar provides time interval information as well as two programmable alarms.

To accommodate different baseband requirements, the LP3925 PMU has different default voltage settings and

startup sequences. Two general-purpose comparators can be used for detecting external accessories like ear-

phones etc. Power conversion and signal level shifting circuits are provided to allow SIM interfacing.

Product Folder Links: LP3925

LP3925

VIN1

VIN2

VIN3

TCXO2_I*

TCXO2_O*

GND

TCXO1_I*

TCXO1_O*

VIN4

VCOIN

VTRM

1 PF

SW_B1

FB_B1

VIN_B1

GND_B1

GND_B2

GND_B3

SINK1*

SINK2*

SINK3*

INP1*

SDA

SCL

PWR_ON

PS_HOLD

SLEEP_N (TCXO_EN)

1 PF

LDO1

LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

LDO8

LDO9

LDO10

LDO11

LDO12

LDO13

10 PF

4.7 PF

1 PH

4.7 PF

SW_B2

FB_B2

VIN_B2

4.7 PF

1 PH

4.7 PF

SW_B3

FB_B3

VIN_B3

4.7PF

1PH

4.7 PF

HF_PWR

VDD

- +

10 PF

BATT

Thermal

Shutdown

USB LDO

28 OVP

Backup

Battery

Charger RTC

MPL

Serial Interface

and

Control

3 Bucks

LDO1

LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

LDO8

LDO9

LDO10

10 General LDOs

2TCXO

Buffers

INP2*

µPWR LDO

1 PF

LDO_UPWR

WILO1

3 WILO LDOs

VDD VDD

VBUCK3

VBUCK1

VBUCK2

VBUCK3

VDD

GND_SINK

Reference

Voltage

Oscillator

2 Comparators

3 Current

Sinks

1.5 k:1.5 k:

500 k:

LDO1

BATT

1 PF

Charger

28V OVP

CHARGER

LDO

USB

transceiver

10:

D+

10:

D-

SE0/VM*

DATA/VP*

OE_N*

LDO1

XIN

XOUT 32 kHz OSC

OSC_32KHZ

1.5 k:

VIN_CHG

SEL

WILO2

WILO3

SIM_CLK*

SIM_RST*

SIM_CLK_IN*

SIM_RST_IN*

SIM_IO*

SIM_DATA*

GND_USB

REF_OUT

12bit

ADC

12 Input MUX

RCV*

SPND*

USIM Level

Shifter

IRQ_N 10 k:

LDO1

RSTOUT_N

RSTIN_N

RSENSE*

ADC

10 k:

1 PF

VDD

500 k:

SIM card

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Typical Application Diagram

Product Folder Links: LP3925

VDD VDD BATT D- D+ USB_

GND FB_ B1 VIN_B1

VIN_

CHG VIN_

CHG VTRM

RCV*

SE0/

VM* DATA/

VP* GND_B1 SW_B1

XIN PWR_

ON TCXO1

_O* OSC_

32KHZ*

OE_N*

SCL SDA FB_B2 VIN_B2

XOUT VCOIN TCXO2

_O*

RSTOUT

RSE

NSE* GND_B2 GND_B2 SW_B2

LDO1 LDO_

UPWR TCXO2

_I*

SPND*

GND INP1* IRQ_N FB_B3 VIN_B3

VIN1 TCXO1

_I*

SEL

SIM_

RST*

SIM_

RST_IN* INP2* GND_B3 GND_B3 SW_B3

LDO2 RSTIN

_N SLEEP_N

(TCXO_EN) SIM_

CLK* SIM_

CLK_IN* GND_

SINK SINK3* PS_

HOLD LDO13

LDO3 LDO4 LDO8 SIM_IO* SIM_

DATA* SINK2* SINK1* REF_

OUT VIN4

LDO5 VIN2 LDO6 LDO7 VIN3 LDO9 LDO10 LDO11 LDO12

A B C D EFGHJ

BATT

HF_

PWR

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Pin Configuration

Figure 1. LP3925 (Top View)

* Pins that can be programmed as analog pins (default as stated in pin configuration) or digital input/output pins.

Pins that are used for USB transceiver interfacing are chosen in accordance of the interface used, either 3-wire

or 5-wire. All these pins except SINK1, 2, 3 and INP1, 2 can be used as ADC inputs.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Pin Functions

Table 1. Pin Descriptions

Name Pin No. Type(1) Description

BATT C1, D1 P Main battery connection.

D- E1 A USB Differential Data Line (-) Input/Output.

D+ F1 A USB Differential Data Line (+) Input/Output.

Data input/output for 3 wire USB transceiver/ USB Interface Plus Input/Output for 5 wire

DATA/VP(2) G2 DI/O USB. If OE_N = HIGH, VP is a receiver output (+), If OE_N = LOW, VP is a driver input (+).

FB_B1 H1 A Buck1 Feedback.

FB_B2 H3 A Buck2 Feedback.

FB_B3 H5 A Buck3 Feedback.

GND E5 G Ground

GND_B1 H2 G Power Ground for Buck1.

GND_B2 G4, H4 G Power Ground for Buck2.

GND_B3 G6, H6 G Power Ground for Buck3.

GND_SINK F7 G Ground of GPIO current sink.

Input for triggering startup. Power up sequence starts when this pin is set HIGH. Internal 500

HF_PWR D4 DI kΩpulldown resistor.

INP1(3) F5 A Comparator 1 input

INP2(3) F6 A Comparator 2 input

Interrupt output, active LOW.

IRQ_N G5 DO Open Drain output, external pull up resistor is needed, typ. 10 kΩ.

LDO_UPWR B5 A Internal supply output, fixed to 1.8V. Can be loaded externally, max 30 mA.

LDO1 A5 A LDO1 Output

LDO10 G9 A LDO10 Output

LDO11 H9 A LDO11 Output

LDO12 J9 A LDO12 Output

LDO13 J7 A LDO13 Output

LDO2 A7 A LDO2 Output

LDO3 A8 A LDO3 Output

LDO4 B8 A LDO4 Output

(1) A = Analog Pin, D = Digital Pin, I = Input Pin, DI/O = Digital Input/Output Pin, G = Ground, O = Output Pin, P = Power Connection

(2) Pins that can be programmed as analog pins (default as stated in pin configuration) or digital input/output pins. Pins that are used for

USB transceiver interfacing are chosen in accordance of the interface used, either 3-wire or 5-wire. All these pins except SINK1, 2, 3

and INP1, 2 can be used as ADC inputs.

(3) Pins that can be programmed as analog pins (default as stated in pin configuration) or digital input/output pins. Pins that are used for

USB transceiver interfacing are chosen in accordance of the interface used, either 3-wire or 5-wire. All these pins except SINK1, 2, 3

and INP1, 2 can be used as ADC inputs.

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Table 1. Pin Descriptions (continued)

Name Pin No. Type(1) Description

LDO5 A9 A LDO5 Output

LDO6 C9 A LDO6 Output

LDO7 D9 A LDO7 Output

LDO8 C8 A LDO8 Output

LDO9 F9 A LDO9 Output

USB Output Enable input. Active LOW enables the transceiver to transmit data onto the bus.

OE_N(3) E2 DI A HIGH input enables receive mode.

OSC_32KHZ(3) D3 DO Buffered 32 kHz clock signal output.

Control input for Power Up/Power Down sequences of PMU. Internal 500 kΩpulldown

PS_HOLD H7 DI resistor by EEPROM default. Can be configured as pullup as well.

Power button input. Power up sequence starts when this pin is set HIGH. Internal 500 kΩ

PWR_ON B3 DI pulldown resistor.

RCV(3) E3 DO Receive Data: Single ended output from USB differential data lines for 5 wire USB.

REF_OUT H8 A 2.5V Reference output

RSENSE(3) F4 A Sense resistor input pin for charge/discharge current measurement

RSTIN_N B7 DI Reset button input, active low. Internal 500 kΩpullup resistor.

RSTOUT_N C6 DO Reset output, active low. Pin stays LOW during power up sequence.

SCL F3 DI Serial interface clock input; requires external pullup, 1.5 kΩtyp.

SDA G3 DI/O Serial interface bi-directional data; requires external pullup, 1.5 kΩtyp.

Data input/output for 3 wire USB transceiver/ USB Interface Minus Input/Output for 5 wire

SEO/M(4) F2 DI/O USB. If OE_N = HIGH, VM is a receiver output (-), If OE_N = LOW, VM is a driver input (-).

SEL D5 DI Select input for default option at power up

SIM_CLK(4) D7 DO SIM card connection. Level shifted clock signal to SIM

SIM_CLK_IN(4) E7 DI SIM clock input from Baseband Processor

SIM_DATA(4) E8 D SIM data input/output from Baseband Processor

SIM_IO(4) D8 D SIM card connection. SIM Card Data input/output

SIM_RST(4) D6 DO SIM card connection. Level shifted reset signal to SIM

SIM_RST_IN(4) E6 DI SIM reset input from Baseband Processor

SINK1(4) G8 A Current sink input 3.

SINK2(4) F8 A Current sink input 2.

SINK3(4) G7 A Current sink input 3.

SLEEP_N Sleep mode input, active low. Internal 500 kΩpullup resistor by EEPROM default. Can be

C7 DI

(TCXO_EN) configured as pulldown as well.

USB Suspend mode control input for 5 wire USB. A logical high at SUSPEND will power

SPND(4) E4 DI down the differential receiver and VP and VM will remain active with reduced current

consumption.

SW_B1 J2 A Buck1 Output.

SW_B2 J4 A Buck2 Output.

SW_B3 J6 A Buck3 Output.

TCXO1_I(4) B6 A TCXO1 buffer input.

TCXO1_O(4) C3 DO Buffered and validated TCXO1 output clock signal.

TCXO2_I(4) C5 A TCXO2 buffer input.

TCXO2_O(4) C4 DO Buffered and validated TCXO2 output clock signal.

USB_GND G1 G USB Ground

VCOIN B4 A Back up battery Charger Output. Connection of external coin cell (2.5 or 3.0V).

VDD A1, B1 P Output for system power.

VIN_B1 J1 P Input for Buck1

(4) Pins that can be programmed as analog pins (default as stated in pin configuration) or digital input/output pins. Pins that are used for

USB transceiver interfacing are chosen in accordance of the interface used, either 3-wire or 5-wire. All these pins except SINK1, 2, 3

and INP1, 2 can be used as ADC inputs.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Table 1. Pin Descriptions (continued)

Name Pin No. Type(1) Description

VIN_B2 J3 P Input for Buck2

VIN_B3 J5 P Input for Buck3

DC power input to charger block from wall, car power adapter or USB. Requires 1µF

VIN_CHG A2, B2, C2 P capacitor to ground.

VIN1 A6 P Input for LDOs

VIN2 B9 P Input for LDOs

VIN3 E9 P Input for LDOs

VIN4 J8 P Input for LDOs

VTRM D2 A USB Reference supply output (3.3 V). Requires 1µF capacitor to GND for stability. LDO14

XIN A3 A External Crystal Oscillator In

XOUT A4 A External Crystal Oscillator Out

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1) (2)(3)

VINCHG to GND −0.3V to +28V

BATT, VIN_B1, VIN_B2, VIN_B3, VCOIN, VIN1, VIN2, VIN3, VIN4 −0.3V to +6V

SEL −0.3V to +2V

Other input-only pins 0.3V to +6V

Junction Temperature (4) 150°C

Storage Temperature −65°C to +150°C

Maximum continuous power dissipation See (4)

VIN_CHG, BATT, HF_PWR, PWR_ON, RSTIN_N, D+, D-, RSENSE, SIM_IO, SIM_CLK, SIM_RST, 8kV HBM

GND_USB (5)

All other (5) 2kV HBM

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test

conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(4) Internal thermal shutdown protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typ.) and

disengages at TJ=130°C (typ).

(5) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. The machine model is a 200 pF

capacitor discharged directly into each pin. MIL-STD-883 3015.7

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Operating Ratings(1) (2)

VIN_CHG 4.5V to 6.5V

BATT, PRSW, VIN_B1, VIN_B2, BIN_B3 3.0V to 4.5V

VCOIN 1.9V to 4.5V

VIN1, VIN2, VIN3 2.5V to 4.5V

VIN4 1.0V to 4.5V

Junction Temperature Range −40°C to +125°C

Maximum Ambient Temperature (3) −40°C to +85°C

Maximum power dissipation (3) 1.72W

Package Thermal Resistance θJA 32°C/W

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test

conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pin.

(3) The Maximum power dissipation depends on the ambient temperature and can be calculated using the formula P = (TJ- TA)/θJA where

TJis the junction temperature, TAis the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The 1.72W rating

appearing under Maximum Ratings results from substituting the Maximum junction temperature, 125°C, for TJ, 70°C for TA, and 32°C/W

for θJA. More power can be dissipated safely at ambient temperatures below 70°C. Less power can be dissipated safely at ambient

temperatures above 70°C. The Maximum power dissipation can be increased by 31 mW for each degree below 70°C, and it must be de-

rated by 31 mW for each degree above 70°C.

General Electrical Characteristics

Typical values and limits appearing in normal typeface are for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation TJ=−40°C to +125°C). Unless otherwise specified, the following applies for

VBATT = 3.6V. (1)

Limits

Symbol Parameter Test Conditions Typ Unit

Min Max

UNDER VOLTAGE LOCK-OUT

VIN Rising; UVLO LEVEL programmed to

UVLO Range-to-range accuracy 3.0 3.25 V

3.10V

LOGIC AND CONTROL INPUTS

SDA (2), SCL (2), OE_N, DATA/VP, SEO/VM, 0.25 ×

SPND VLDO1

VIL Input low level V

PWR_ON, RS_HOLD, SLEEP_N, HF_PWR, 1.08

RSTIN_N

SDA (2), SCL (2), OE_N, DATA/VP, SEO/VM, 0.75 ×

SPND VLDO1

VIH Input high level V

PWR_ON, RS_HOLD, SLEEP_N, HF_PWR, 1.32

RSTIN_N

VIL Multifunctional pins low level 0.6

When configured as logic inputs. V

VIH Multifunctional pins high level 1.6 3.0

SEL input between 0V and 1.8V.

Other logic inputs without internal pullup or

ILEAK Input current −5 +5 µA

pulldown resistors between 0V and VDD at

3.6V.

PWR_ON, HF_PWR, PS_HOLD, RSTIN_N,

RIN Input resistance SLEEP_N (TXCO_EN) pullup or pulldown 500 kΩ

resistors (if configured)

(1) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(2) Specified by design.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

General Electrical Characteristics (continued)

Typical values and limits appearing in normal typeface are for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation TJ=−40°C to +125°C). Unless otherwise specified, the following applies for

VBATT = 3.6V. (1)

Limits

Symbol Parameter Test Conditions Typ Unit

Min Max

LOGIC AND CONTROL OUTPUTS

RSTOUT_N, RCV, DATA/VP, SEO/VM, 0.25 ×

IRQ_N VLDO1

IOUT = 2mA

VOL Output low level V

SDA (3) 0.25 ×

VLDO1

RCV, DATA/VP, SEO/VM 0.75 ×

VOH Output high level V

IOUT = 2mA VLDO1

SDA (3), RSTOUT_N, IRQ_N

IOH Output high leakage 10 µA

VOH = VLDO1

(3) Specified by design.

Current Consumption

Current consumption of the LP3925 PMU has been one of the main features this device is famous for. It is

mainly because of ultra low IQs in sleep and standby modes the LP3925 can ensure dramatic power savings and

prolong battery life for enormous amount of time. Due to such a significant advantage in these critical factors, an

LP3925 is very convenient to use in innovative and environmentally friendly designs, giving the end user the

possibility of increased consumer device working time and thus a crucial advantage of the rapidly developing

mobile market.

The quiescent currents in standby and sleep modes are stated in the Current Consumption Electrical

Characteristics.

Current Consumption Electrical Characteristics

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V. (1)

Limits

Symbol Parameter Test Conditions Typ Unit

Min Max

CURRENT CONSUMPTION

VIN = 3.6V

IQ(STANDBY) Battery Standby Current 3.5

ICOIN = 0µA µA

IQ(SLEEP) Battery Current in SLEEP mode at 0 load LDO1 ON 60

(1) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

DEVICE OPERATING MODES

POWER-ON-RESET: All internal registers are reset to default values. This is the default state after applying

power to the PMU, duration 1ms.

STANDBY: All functions disabled (except RTC power management); PMU is in low power mode.

START UP:Startup sequence is triggered by setting PWR_ON input high for 100 ms or by setting HF_PWR

input high for 100 ms or by connecting a suitable voltage to charger input. For MPL or RTC ALARM

events the startup sequence begins after 2ms delay from the MPL or RTC ALARM events. During the

sequence the regulators on PMU are enabled according to a pre-programmed timing pattern. If the

regulators are enabled, RSTOUT_N is released, allowing the application processor to start up. PS_HOLD

must be set high in 1.5 seconds from the start of STARTUP. The input signal witch activates startup must

stay on until PS_HOLD asserted. If PS_HOLD is not asserted in 1.5 seconds then SHUTDOWN is

initiated. For PWR_ON startup there is no 1.5 seconds limit.

IDLE: PMU goes to normal working mode, if PS_HOLD is pulled HIGH after releasing RSTOUT_N. In this mode

all features and control interfaces are available to the user. Chip temperature over TSDH, VDD voltage

below UVLO, PS_HOLD going low for 10 ms or a flag failure in a monitored regulator for 10 ms will cause

the PMU to go to SHUTDOWN state.

SLEEP: PMU goes to SLEEP state from IDLE state, if SLEEP_N input is pulled low. In this mode PMU current

consumption is minimized to extend device's standby time. Load on regulators and bucks should stay

below 5mA each. Conditions of going to SHUTDOWN state are the same as in IDLE state.. SLEEP Mode

is controlled by the Serial Interface.

SHUTDOWN: In this state RSTOUT_N is pulled LOW and all regulators are disabled according to pre-

programmed timing pattern. After this, all registers are reset to default values, and PMU goes to

STANDBY state.

SYSTEM RESET:PMU goes to SYSTEM RESET mode if RSTIN_N input has been pulled low for 33 ms. In this

mode RSTOUT_N output is pulled low and user registers are reset. After a pre-programmed time delay

RSTOUT_N is released, allowing the application processor to start up. During SYSTEM RESET, the

LP3925’s always-on power rail will not drop to zero. If for some reason PS_HOLD is pulled down during

reset, it must come back up within 1.5s of the beginning of system reset. If EN RSTIN SHUTDOWN bit is

high then the reset sequence is similar to shutdown and will startup again only if EN RSTIN STARTUP bit

is high.

Product Folder Links: LP3925

POWER-ON

RESET

STANDBY STARTUP

WORKINGSHUTDOWN

SLEEP

SLEEP_N = 0

(TCXO_EN)

Chip Temperature > TTSD_HI OR

RSTIN_N = 0 for 33 ms AND

RSTIN shutdown enabled OR

PS_HOLD = 0 for 10 ms OR

VDD Voltage < VUVLO OR

Monitored Supply < 85%

for 0.5 ms

PWR_ON = 1 for 100 ms OR

HF_PWR = 1 for 100 ms OR

VBAT < VCHGIN < VCINH for 550 ms OR

coming from RSTIN reset OR

RTC alarm event OR MPL event

PS_HOLD = 0 after 1500 ms OR

VDD Voltage < VUVLO

Sequence

Duration 1 ms

Internal Powerup

Delay 5 ms

CPU RESET

RSTIN_N = 0 for 33 ms AND

RSTIN shutdown disabled

RSTOUT_N = 1 AND

PS_HOLD = 1

RSTOUT_N = 1 AND

PS_HOLD = 1

SLEEP_N = 1

(TCXO_EN)

PS_HOLD = 0

after 1500 ms

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Figure 2. Device Operating Modes

Product Folder Links: LP3925

SLEEPSTANDBY STARTUP SHUTDOWN STANDBY STARTUP SHUTDOWN STANDBYIDLEIDLE

VIN_CHG

PWR_ON

Step1 supplies:

RSTOUT_N

PS_HOLD

SLEEP_N

Step2 supplies:

Step15 supplies:

550 ms

100 ms

prog

256

50 ms

450 us

100 ms

prog

50 ms 1500 ms

450 us

HF_PWR or

only for HF_PWR

1.5s

OSC_32kHz CLK

RSTIN_N 1500 ms

50 ms

RESET IDLE

192

us 32

192

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

STARTUP AND SHUTDOWN SEQUENCES

Figure 3. Startup and Shutdown Sequences

The default, factory-programmed power-up sequence of the PMU can be seen in Figure 3. Startup sequence is

triggered by setting PWR_ON or HF_PWR input high for 100 ms or after 500 ms is passed from the connection

of a suitable voltage to the charger input. Once this time has expired, the start-up time slots begin. The

programmable values of the startup and shutdown time slots are available in the Default Operating Settings

section at the end of the datasheet. If the Idle state has been reached from the Startup state, all regulators that

are enabled are on, and their outputs are defined by their programmed register values. 450 µs in

startup/shutdown diagram is the time needed for system to perform a shutdown event.

NOTE

All the timings are limited by an internal oscillator’s accuracy. Please contact TI sales for

default EEPROM setting details.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

ENABLE CONTROL

LP3925 provides much flexibility in enabling/disabling on-chip features. The blocks that have advanced enable

controls include: LDOs, buck regulators, USB transceiver, TCXO buffers, SIM level shifter. Each block has a 4-bit

code in registers, which selects the enable signal for that block. These codes are in register addresses

0x37...0x41, with bit names ending with CONTROL. The enable signal translation table is stated below.

In order to make the control more flexible, there is a possibility for the blocks to be enabled through registers

0x00…0x02 or through multifunctional pins. One control signal can enable any number of features. This allows to

group signals so, that any end-system function can be switched on with only one input or register write.

There are additional enable controls for sleep mode operation with ALLOW IN SLEEP bits in register addresses

0x34...0x36. If a block is not allowed in sleep mode, then this block is always off during sleep. If a block is

allowed in sleep mode, then it is controlled by its selected enable signal, and does not depend on sleep mode.

Example 1:

Goal: Buck2 is always disabled in sleep mode and enabled in idle mode.

Best solution: write BUCK2 CONTROL to '0001' and ALLOW BUCK2 IN SLEEP to '0'; now Buck2 is enabled in

working mode and disabled in sleep mode, with no separate enable bit/input.

Example 2:

Goal - Enable LDO9, LDO10 and TCXO buffer1 together with one register write.

One possible solution: write LDO9 CONTROL, LDO10 CONTROL and TCXO1 CONTROL to 0010; now writing

'11' to address 0x00 bits [1:0] enables all three blocks.

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

MULTIFUNCTIONAL PINS

Some pins corresponding to 32 kHz oscillator, USB transceiver, SIM interface, TCXO buffer, current sink and

comparator blocks along with RSENSE pin are multifunctional pins, which means that they can be programmed

as analog function pins, ADC inputs or digital input/output pins. These pins can be configured from registers

0x19..0x23.

If one block uses more than one pin, then all the pins must be configured for the block to work. For example, all

6 SIM level shifter pins must have level shifter function selected, before the block is connected to the pins. To

use USB with 4- or 5-wire interface, the used pins must all be configured as 5-wire USB pins. For 3-wire

interface the 3 pins must all be configured as 3-wire USB pins.

Some GPIO functions have separate enable controls. These enables will take the blocks to a shutdown state, but

will not disconnect them from the pins. The GPIO configuration options are described in Table 2.

Table 2.

Pin/Code 1000 1001 1010 1011 1100 1101 1110 1111

OSC_32 KHZ 32 kHz OSC

Maximum measurable voltage drop on sense resistor

RSENSE N/A 12 mV 26.4 mV 39.6 mV 56.4 mV 81.6 mV 98.4 mV 120 mV

SIM_RST_IN SIM RST, baseband side

SIM_CLK _IN SIM CLK, baseband side

SIM_DATA SIM I/O, baseband side

SIM_RST SIM RST, SIM side

SIM_CLK SIM CLK, SIM side

SIM_IO SIM I/O, SIM side

TCXO1 warmup time before output enable

TCXO1_I 1µs 21 µs 41 µs 61 µs

TCXO1 output driver strength

TCXO1_O x8 x4 x2 x1

TCXO2_I warmup time before output enable

TCXO2_I TCXO2in wait=1µs TCXO2in wait=21 µs TCXO2in wait=41 µs TCXO2in wait=61 µs

TCXO2 output driver strength

TCXO2_O TCXO2out strength=1 TCXO2out strength=2 TCXO2out strength=4 TCXO2out strength=8

OE_N OE_N: 3-pin USB interface OE_N: 5-pin USB interface

DATA/VP DATA: 3-pin USB interface VP: 5-pin USB interface

SEO/VM SEO: 3-pin USB interface VM: 5-pin USB interface

RCV N/A RCV: 5-pin USB interface

SPND N/A SUSP: 5-pin USB interface

Comparator1 input comparison threshold

INP1 0.4V 0.6V 0.8V 1.0V 1.2V 1.5V 1.8V 2.4V

Comparator2 input comparison threshold

INP2 0.4V 0.6V 0.8V 1.0V 1.2V 1.5V 1.8V 2.4V

Current sink1 max current output

SINK1 31mA 63 mA 94 mA 125 mA 156 mA 188 mA 219 mA 250 mA

Current sink2 max current output

SINK2 13 mA 25 mA 38 mA 50 mA 63 mA 75 mA 88 mA 100 mA

Current sink3 max current output

SINK3 13 mA 25 mA 38 mA 50 mA 63 mA 75 mA 88 mA 100 mA

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

SINGLE-INPUT LINEAR CHARGER WITH PMOS ROUTING SWITCH

LP3925 has a built-in Li-Ion/Li-Poly battery management system. Its main features are:

• One input with many current limit options to accommodate different USB and adapter types

• Separate supply branches for battery and system

• Integrated power routing switch

• Charging cycle with precharge, constant current and constant voltage modes

• Selectable battery regulation voltage to accommodate different batteries

• Selectable system regulation voltage

• Wide array of battery charging current options

• Flexible charging cycle control

• Temperature monitoring to avoid overheating

• Selectable safety timer

GENERAL CHARGER CONTROL

The charger control is divided into two separate parts: battery charging and system supply.

Battery charging part of the charger measures battery voltage and current. Based on this data, it makes the

decisions about starting or ending battery charging and choosing the right current.

System supply part monitors the power consumption by the external system, ensures that the system supply is

stable and that the charger input is not overloaded. These systems work independently from each other.

If the power routing switch is OFF (non-conducting), then they can be viewed as two separate systems. The only

dependence between the two is, that battery charging current can be reduced, if the system requires more

current from the input. If the power routing switch is turned ON, then the two algorithms still work independently,

but the system supply part is in control of the whole charger. The battery charging part is in the situation, that it

still does make battery charging cycle decisions, but these do not affect the actual charging.

If the switch is turned OFF again, then the two systems keep on working separately.

CHARGER INPUT DETECTION AND LIMITS

Input detection is implemented with 2 comparators. One compares the input voltage to the lower limit of the

working range, the other to the higher limit of the working range. If the input voltage is between these two levels,

then the charger is allowed to work.

The lower limit of input's working range is VBATT+200 mV, with an option to add a 4.2V minimum requirement.

The higher limit of input's working range can be one of the following values: 6.15V, 6.64V, 7.18V, 7.71V, 10.28V,

15.38V, 18.45V or disabled. To get the exact information about your product, please refer to the Datasheet

Addendum document.

The charger is capable of limiting input current, allowing to accommodate different voltage sources (wall

adapters, USB, etc). IDCIN bits set the maximum input current. The sum of system supply and battery charging

currents will not go over this limit during normal operation. For correct operation, IDCIN should be set to 235mA

or more above IBATT (though this margin can be reduced for IDCIN below 500 mA; e.g. down to 85 mA at IDCIN

= 135 mA). High current mode ignores the input current limit.

Some of the GPIO pins can be configured as a dedicated charger input status signal output. This signal is low, if

charger input is in working range. The 'Inverted VDCIN' configuration details are in the GPIO chapter of the

datasheet.

SYSTEM SUPPLY FUNCTION

system supply regulator starts to regulate voltage on VDD pin. The voltage is selectable with VDD control bits.

System voltage regulator will work as long as charger input is in working range. The only exception is the case,

where PMU is in standby mode and system supply is configured off in standby.

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Because system and battery are supplied from separate branches, the VDD and BATT voltage levels can be

different. This means, that the selected voltage can be supplied to VDD and the PMU can fully operate, while the

battery is deeply discharged and the charger is in pre-charge mode. In that case the system should not use

modes, which will require more current, than the input can provide.

System supply is with higher priority than battery charging. This means that if the sum of system and battery

currents starts to go over the input limit, then battery charging current will be reduced to stay within the input

loading limit.

If the system supply reaches the selected input current limit, then the power routing switch will be turned ON.

This will connect the battery to the system, which will provide the extra power needed. Also, the system supply

current limit will change from input current limit (IDCIN bits) to battery current limit (IBATT bits). This ensures, that

if the system load drops, then the battery will not be charged with too large current.

In some systems it may be practical to disable the input current limit, so the system can draw more than 1.2A

without turning the switch ON. The SYSTEM SUPPLY CURLIM OFF bit can be used for this purpose. Warning:

continuous high current draw from the input may cause the PMU to shut down because of high temperature.

There is a configuration option for the system supply during PMU's standby mode. The selection for a specific

product is shown in Datasheet Addendum document.

This option has following behavior:

a) supply on during PMU standby: VDD is supplied from BATT via switch (if charger is not working) or from

system supply branch (if charger is working).

b) supply off during PMU standby: VDD is isolated from BATT pin during PMU standby and system supply

branch is disabled.

BATTERY CHARGING FUNCTION

LP3925 has a safe and smart Li-Ion/Li-Poly battery charge management system, keeping the number of battery

charging cycles to a minimum and thus increasing battery lifetime.

Following the correct detection of a voltage at the charger input, the charger enters precharge mode. In this

mode the battery is charged with a small constant current. Precharge settings are available in register 0x82 and

these values are remembered as long as the PMU has power. CHARGER IPRECHARGE bits select the battery

current in precharge mode. It should be noted, that value '00' disables precharge current completely.

CHARGER VFULLRATE bits select the level, from which the battery can be charged with full charging current. If

battery voltage reaches that level, then the charger will move on to full charging mode. CHARGER

TPRECHARGE sets the maximum precharge time, after which the battery will be isolated, protecting it from

further charging.

In full charging mode full rate constant current is applied to the battery, to raise the voltage to the termination

level (selected by VTERM bits). The maximum charging current is selectable via IBATT bits, but the actual

current can be lower than this limit, depending on the load of system branch. When termination voltage is

reached, the charger enters constant voltage mode and a constant voltage is maintained. Now charging current

is monitored to detect the end-of-charge condition. After reaching this condition, charger disables the battery

charging branch and enters standby mode. FULL TIMEOUT sets the maximum full charge duration, after which

the charging will be ended automatically. Then the charger enters standby mode, where the battery is isolated

and the charger monitors battery voltage. If restart conditions have been met, then the charging cycle is re-

initiated to re-establish the termination voltage level.

In standby mode the battery is isolated and the charger monitors battery voltage.

CC TO CV MODE TRANSITION

CC to CV mode transition is shown on Figure 9. The voltage level of charging mode change (CC to CV) is

dependent on both VTERM (0x47, bit3-0) and IBATT (real charging current) settings, equation shows below:

VCCtoCV = VTERM - (IBATT*0.05) (1)

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

where 0.05 stands for charger’s internal resistance. This equation is valid only when the power routing switch is

in non conducting state and the charging is done through charger’s branch. When the switch is ON, the charging

is done through the supply branch, and the internal resistance in the equation is replaced by the power routing

switch’s ON resistance. Note that the IBATT current in equation is the real battery charging current which may

differ from the programmed one.

USER can use ADC to measure charging current and BATT pin voltage.

END-OF-CHARGE AND RESTART

Ending and re-starting the charging cycle can be accomplished in multiple ways.

Automatic control can be enabled with AUTOMATIC START/STOP bit. If this bit is '0', then the charging cycle

can only be controlled manually. Writing this bit to '1' enables fully automatic cycle control.

Manual control is always available via STOP CHARGING and START CHARGING bits. These control bits are

write-only and not tied to any internal monitoring, allowing to start and stop charging at any time. Only one of

these bits must be written to '1' at once.

Automatic control utilizes internal battery monitoring, which can be configured trough control registers.

Automatic end-of-charge requires that the battery has reached termination level. Then the charger starts

monitoring battery charging current and comparing it to end-of-charge current (set by ABS EOC and EOC LEVEL

bits). If the charging current is below this level for the duration of EOC TIME, then the automatic end-of-charge

condition has been reached.

Automatic restart requires that one charging cycle has already been completed and the charger is in standby

mode. Then the charger monitors battery voltage and compares it to restart level (set by RESTART LEVEL). If

the battery voltage is below this level for the duration of RESTART TIME, then the automatic restart condition

has been reached.

In manual-only mode it is possible to get automatic cycle control information via interrupts. CHARGE STOP INT

is generated, if end-of-charge condition has been reached, and CHARGE START INT is generated, if restart

condition has been reached).

POWER ROUTING SWITCH

This switch separates the battery from the system. This helps to conserve charge and reduce the count of

charge-discharge cycles.

If charger input is not connected, then the switch is in ON (conducting) state.

In normal conditions the switch is OFF during charger operation. The switch will be turned ON, if the system load

is greater than the charger can supply. This event also generates a SWITCH AUTO ON interrupt. If the switch is

turned ON during charger operation, then it does not turn back OFF automatically. The only exception to that rule

is, if the PMU enters standby mode. If the charger is operating and the switch is turned ON, then only system

supply branch is working. Maximum output current is then set by IBATT code, to avoid too high current into the

battery.

If the charger is working, then power routing switch state can be controlled manually with SWITCH ON and

SWITCH OFF command bits. It is advisable to use the SWITCH ON command before the system enters a mode,

which draws more current than the input can provide. This will help to avoid voltage drop on VDD, before the

internal overload detection reacts. If the system returns to low consumption mode, the SWITCH OFF command

bit should be used to restore normal charger operation.

OPERATION WITHOUT BATTERY

The charger is not aware of battery presence, it always behaves by the same configuration. If the battery is not

connected, then it is recommended to keep the battery charging part disabled. This can be done by disabling the

restart timer and ending the charging with STOP CHARGING bit. Otherwise the charger will keep trying to

regulate the voltage on BATT pin, causing frequent charging cycles.

Product Folder Links: LP3925

Battery

Charger

System

Supply

Power

Routing

Switch

VIN_CHG

BATT

VDD

to battery

to the system

VTERM

IPRECHG

VFULLRATE

Battery Voltage

Pre-Charge to Full-Rate

Charge Transition Transition to Constant-

Voltage Mode

Charging Current

End-of-Charge Current Level

Full-Rate Current

Battery Voltage

Charging Current

Time

Maintenance charging starts

VRESTART Restart

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

HIGH-CURRENT MODE

If HIGH-CURRENT MODE bit is set, then the charger enters special high load mode. In this mode the power

routing switch is set ON, input current limit is disabled, and the charger branches are working together. All

charging cycle controls do not have any effect in high current mode.

Figure 4. Charging Cycle Voltage and Current Plots

Figure 5. Charger Power Structure

Product Folder Links: LP3925

SWITCH ON

SWITCH OFF

PMU exits from standby mode

OR charger input removed

PMU enters standby mode

(configuration option)

PRECHARGE

(max Ichg = Iprechg)

Input in range (VIN_OV > Input > VIN_LV )

AND wait 40ms for charger services

STANDBY

(Ichg = 0)

Input out of range

(Input > VIN_OV ) OR (Input < VIN_LV ) CHARGER OFF

(Ichg = 0)

Restart condition

FULL CHARGE

(max Ichg = IBATT)

VBATT > VFULLRATE

Precharge timeout

VBATT < VFULLRATE

EOC condition OR

full charge timeout

BAD BATTERY

(Ichg = 0)

Deglitching times:

- Charger input in range, rising edge: 50 ms

- Charger input in range, falling edge: 2 us

- Vfullrate, Vrestart, Ieoc: 400 ms

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Figure 6. Charger Charging Cycle Operation Description

Figure 7. Charger Internal Power Switch Operation Description When Charger is Off

Product Folder Links: LP3925

SWITCH ON

SWITCH OFF

x BATT and VDD connected through switch

x BATT regulator: disabled

x VDD regulator: enabled

x VDD regulator current: up to IBAT

x No current sharing

x BATT and VDD separated by switch

x BATT regulator: enabled during precharge and

full charge

x BATT regulator current: up to IBAT in full

charge, up to IPRECHG in precharge

x VDD regulator: enabled (disabled only if PMU in

standby and VDD configured off in standby)

x VDD regulator current: up to IDCIN

x Current sharing activated

VDD voltage below 3.3V OR

VDD regulator current = IDCIN OR

High Current Mode enabled OR

Switch ON command

Start of the first charging cycle

after input connection OR

PMU in standby mode OR

Switch OFF command

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Figure 8. Charger Internal Power Switch Operation Description When Charger is On

Product Folder Links: LP3925

I Error

Amplifier

V Error

Amplifier

T Error

Amplifier

Charge

Current

Selection

Termination

Voltage

Selection

vref

BATT

Temperature

Selection &

Temperature

Sensor

vref

Charge

Pump cp

CHGIN

BATT

Discharge

Current

Measurement

End of

Charge

Current

LDO Error

Amplifier

LDO Curlim

Amplifier

CHGIN

VDD

LDO

Curlim

Selection

vref

LDO

Output

Voltage

Selection

Adaptive

Current

Sharing

Restart

Voltage

Fullrate

Threshold

Voltage

Input

Voltage

Control

CC to CV

Mode

Transition

System

Voltage

Monitor

Battery

Temperature

Monitor

PMU Internal

Supply

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Figure 9. Charger Block Diagram

Product Folder Links: LP3925

IBATT

VTRM

Charge Current

limited by CC mode

Charge

Current in

CV mode

limited by

50 m

50 m internal

resistance slope

CC/CV transition

point

VBATT

IBATT

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Figure 10. Charger CC to CV Mode Transition Diagram

CHARGER ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−25°C to +85°C. Unless otherwise specified, the following applies for

VVIN_CHG = 5.0V.(1) (2)

Limit

Symbol Parameter Test Conditions Typ Unit

Min Max

Over-Voltage Protection Charger input is turned off if voltage is

VOV 6.95 6.55 7.4 V

threshold above this threshold.

VVIN_CHG AC input voltage operating 4.5 6.5 V

range VVIN_CHG - VBATT (Rising) 300

VOK_CHG VIN_CHG OK trip-point mV

VVIN_CHG - VBATT (Falling) 90

VTERM = 4.2V, ICHG = 50 mA −0.35 +0.35

VTERM voltage tolerance

VTERM VTERM is measured at 10% of the %

default −1 +1

programmed ICHG current

6.5V ≥VVIN_CHG ≥4.5V

Programmable full-rate VBATT < VVIN_CHG −VOK_VIN_CHG 50 1200 mA

charge current VFULL_RATE < VBATT < VTERM(1)

ICHG = 100 mA (2) 100 75 125

ICHG ICHG = 400 mA (2) 400 350 450

Full-rate charge current mA

tolerance ICHG = 600 mA 600 540 660

ICHG = 1100 mA (2) 1100 1040 1160

IPRECHG Pre-charge current 2.2V < VBATT < VFULL_RATE 50 35 65 mA

IDCIN Input current limit IDCIN = 435 mA; IBATT = 200 mA −9 5 %

Maximum input current in

IVIN_CHG_MAX VVIN_CHG - VDD ≤0.8V (2) 2.3 A

high-current mode VBATT rising, transition from pre-charge

Full-rate qualification

VFULL_RATE to full-rate charging 2.8 2.7 2.9 V

threshold (2.8V option selected)

From VTERM voltage (4.2V, −150 mV

VRESTART Restart threshold voltage −150 −180 −120 mV

options selected)

(1) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(1) Specified for output voltages no less than 1.0V

(2) Specified by design.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−25°C to +85°C. Unless otherwise specified, the following applies for

VVIN_CHG = 5.0V.() ()

Limit

Symbol Parameter Test Conditions Typ Unit

Min Max

TREG Regulated junction 115°C option selected (2) 115 °C

temperature

DETECTION AND TIMING (2)

TPOK Power OK deglitch time VCHG > VBATT + VOK_CHG 30 ms

TPQ_FULL Deglitch time Pre-charge to full-rate charge transition 210 ms

Pre-charge mode (default setting) 45 mins

TCHG Charge timer CC mode/CV mode (default setting). 5 Hrs

TEOC Deglitch time for end-of- 210 ms

charge transition

BUCK INFORMATION

The LP3925 has integrated three high efficiency step-down DC-DC switching buck converters that deliver a

constant voltage from a single cell battery to portable devices. Using voltage mode architecture with synchronous

rectification, the buck has the ability to deliver up to 800 mA depending on the input voltage and output voltage,

ambient temperature, and the inductor chosen.

There are two modes of operation depending on the current required - PWM (Pulse Width Modulation), ECO

(ECOnomy) mode. The device operates in PWM mode at load currents of approximately 50 mA (typ.) or higher.

Lighter output current loads cause the device to automatically switch into ECO mode for reduced current

consumption and a longer battery life. 2 buck regulators are capable of DVS control. Additional features include

soft-start, under voltage protection, current overload protection, and thermal shutdown protection. Only three

external power components are required for implementation.

BUCK CIRCUIT OPERATION

The switching buck converter operates as follows. During the first portion of each switching cycle, the control

block in the LP3925 turns on the internal PFET switch. This allows current to flow from the input through the

inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN-

VOUT)/L, by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the

PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The

inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the

inductor current down with a slope of -VOUT/L.

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage

across the load. The output voltage is regulated by modulating the PFET switch on time to control the average

current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the

switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter

capacitor. The output voltage is equal to the average voltage at the SW pin.

PWM OPERATION

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This

allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional

to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is

introduced. While in PWM mode, the output voltage is regulated by switching at a constant frequency and then

modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET

switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the

switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is

exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by

the clock turning off the NFET and turning on the PFET.

Product Folder Links: LP3925

Control

PWM

ECO

Comparator

Err Amp

FB SW

pwm

comp

Current

Sensing

peak current

limit

PWM threshold

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Figure 11. Typical PWM Operation

INTERNAL SYNCHRONOUS RECTIFICATION

While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

CURRENT LIMITING

A current limit feature allows to protect itself and external components during overload conditions. PWM mode

implements current limit using an internal comparator that trips at 1100 mA (typ.). If the output is shorted to

ground and output voltage becomes lower than 0.3V (typ.), the device enters a timed current limit mode where

the switching frequency will be one fourth, and NFET synchronous rectifier is disabled, thereby preventing

excess current and thermal runaway.

ECO MODE OPERATION

The buck switches from ECO state to PWM state based on output load current. At light loads (less than 50mA),

the converter enters ECO mode. In this mode the part operates with low Iq. During ECO operation, the converter

positions the output voltage slightly higher (+30mV typ.) than the nominal output voltage in PWM operation. The

more complete understanding of an ECO mode operation can be derived from diagram in Figure 12.

Figure 12. Typical ECO Operation

Power FETs are controlled by “SW Control” which is a combination of ‘comp’ and ‘pwm’ signals, dependent on

‘PWM threshold’ level. “ECO Comparator” is a simple comparator with hysteresis. “Err Amp” and “PWM” are

error amplifier with a ramp generator. ‘PWM threshold’ is current sensing at PFET, that lets control logic know

which input has to be used. In low load condition ‘comp’ is used and in high load condition ‘pwm’ is used. Once

Vout voltage level gets too small, then in low load condition (ECO mode) the “ECO Comparator” triggers and

“SW Control” opens PFET (wide pulse at SW pin; see Figure 3). The wideness of that pulse is determined by

“ECO comparator” which has a built in hysteresis. Normal in ECO mode after that wide pulse has passed no

action should be taken, until next “ECO Comparator” triggering. If some other condition (PWM threshold/Current

limit) is fulfilled, then buck enters PWM mode.

Product Folder Links: LP3925

BUCK (X)_VOUT(Y*)(mV) =

600 mV + code(dec)/127 * 2200 mV

I =

c v

t=10-5 5 10-2

0.35  10-6 = 1.4A

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

If ‘peak current limit’ which is a current sensing signal for PFET’s switch peak currents triggers, then buck enters

PWM mode from the next clock pulse. Peak current sensing is reset at the beginning of every clock pulse. Once

in PWM mode, buck will stay there at least 32 clock pulses and if ‘PWM threshold’ indicates that buck should be

operating in ECO mode, it will return into ECO mode. This is what actually happens on Figure 3 during wide

ECO mode pulse. (The reason behind that is in high peak current during the time PFET is opened. Rough

example:

Figure 13. Buck's Switches Controlling Diagram

where COUT = 10 µF, ripple V = 50 mV and PFET open time = 350 ns).

Figure 14. Typical ECO Operation

The output voltage ripple is slightly higher in ECO mode (30 mV peak-peak ripple typ.)

Figure 15. Typical Ripple in ECO Mode

BUCK OUTPUT VOLTAGE SELECTION

The selection of the bucks’ output voltages can be done by writing a specific code into the control registers (addr.

0x10 … 0x18). The required voltage can be calculated from the following equation:

(2)

Product Folder Links: LP3925

ÂVOUT = 342

8 304

()2+ (0.01 342)2 = 4 mV

ÂIL =0.47 * 3 * 4

(3 - 0.6 * 0.16 - 1.8 - 0.6 * 0.05) * 1.8 = 342 mA

ÂVOUT = ÂV2OUT_C2 + ÂV2OUT_ESR

'VOUT_ESR = ESR'iL

ÂVOUT_C ='iL

8  COUT fSW

ÂIL =L  VIN  fSW

(VIN ± IL  RPdson ± VOUT ± IL  DCR)VOUT

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Where Y* denotes a number, which corresponds to the DVS control code. If DVS is not in use, then VOUT0 is

used. 1-bit DVS uses VOUT0 and VOUT1 and 2-bit DVS uses VOUTs 0 to 3.

EXTERNAL COMPONENT SELECTION

Default values for external components of LP3925 bucks are input and output capacitances CIN = COUT = 4.7 µF

and inductor L=1µH whit the lowest possible DCR (less than 50 mΩ). Below is the table with the selection of

suitable inductors for the application. With the careful selection of the output components the performance of the

buck will not degrade in stability, ripple, load regulation and transient aspects. The inductor current (IL) and

output voltage (VOUT) ripples are directly dependent on the external components. Current ripple is mainly

dependent on the inductance L

(3)

where fSW is the buck’s switching frequency and RPdson is the drain to source resistance of the PMOS power

switch. Voltage ripple on the other hand has 2 main components.

One dependent on output capacitance:

(4)

The other is due to capacitor's ESR

(5)

The resulting RMS ripple is

(6)

For example if use the combination L = 0.47 µH (DCR = 50 mΩ) and COUT = 30 µF (ESR = 10 mΩ), when VIN =

3V and VOUT = 1.8V with load current of 600 mA, the theoretical peak to peak current ripple should be:

(7)

while the RMS peak-to-peak voltage ripple should be in the region of:

(8)

DVS CONTROL

DVS allows a buck regulator to step between pre-programmed voltage values, using multifunctional pins as

selectors. DVS is supported for Buck1 and Buck2. They can have up to 4 pre-programmed values, which are set

in registers BUCKn VOUTn.

Multifunctional pins can be set as single DVS selectors (1 selecting signal) or dual DVS selectors (2 selecting

signals). DVS-controlling pins must be set as Buck1 DVS (code 0101) or Buck2 DVS (code 0110) pins in their

control registers (named GPIOnn).

Any multifunctional pin can be used as a single DVS signal. The signal selects between VOUT0 (input low) and

VOUT1 (input high).

Dual DVS signals can only be predetermined pairs, the function description can be seen in Table 3.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Table 3. Dual DVS Control Table for Bucks 1 and 2

OSC_32KHZ RSENSE

SIM_RST_IN SIM_CLK _IN

SIM_DATA SIM_RST

SIM_CLK SIM_IO

TCXO1_I TCXO1_O

TCXO2_I TCXO2_O BUCK1,2 VOUT

OE_N DATA/VP

SE0/VM RCV

SPND INP1

INP2 SINK1

SINK2 SINK3

0 0 VOUT0

0 1 VOUT1

1 0 VOUT2

1 1 VOUT3

BUCK TYPICAL PERFORMANCE PLOTS

Efficiency Efficiency

(VIN = 3.0V, VOUT = 1.2V) (VIN = 3.6V, VOUT = 1.2V)

Efficiency Efficiency

(VIN = 4.2V, VOUT = 1.2V) (VIN = 3.0V, VOUT = 1.76V)

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Efficiency Efficiency

(VIN = 3.6V, VOUT = 1.76V) (VIN = 4.2V, VOUT = 1.76V)

Buck1 Fast Rise (1µs) Buck2 Fast Rise (1µs)

Buck3 Fast Rise (1µs) Buck1 Slow Rise (5µs)

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Buck2 Slow Rise (5µs) Buck1 Slow Rise (5µs)

BUCK ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−25°C to +85°C. Unless otherwise specified, the following applies for

VBATT = 3.6V. (1)

Limits

Symbol Parameter Test Conditions Typ Unit

Min Max

PWM Mode, No load -3 3 %

VOUT = 1.1V to 1.8V

VFB Feedback voltage PWM Mode, No load -10 10 mV

VOUT = 0.75V to 1.0V

ECO Mode, FB = VIN

IQ_ECO ECO mode IQ25 µA

No switching, sleep mode

VIN = VGS = 3.6V

RDSON (P) Pin-pin resistance for PFET 160 250 mΩ

IOUT = 200 mA

VIN = VGS = 3.6V

RDSON (N) Pin-pin resistance for NFET 115 180 mΩ

IOUT = -200 mA

ILIM Switch peak current limit Open loop; BuckX = 11 1475 mA

IOUT= 0

tSTARTUP Startup time from shutdown 65 µs

VOUT ≥0 to 97%(1)

FSW Switching frequency PWM Mode 4 3.6 4.4 MHz

(1) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(1) Specified by design.

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

LDO INFORMATION

There are altogether 15 LDOs in LP3925 grouped as:

• General-type “PERFECT” LDOs;

• WILO-type LDOs;

• MICRO-PWR LDO; and

• USB LDO.

All LDOs can be programmed through serial interface for different output voltage values which are summarized in

the “Control Register Bit Description” tables.

At the PMU power on, LDOs start up according to the selected startup sequence and the default voltages. See

section Power-on and Power-On Sequences for details.

For stability all LDOs need to have external capacitors COUT connected to the output with recommended value

of 1µF . It is important to select the type of capacitor which capacitance will in no case (voltage, temperature, etc)

be outside of limits specified in the LDO Electrical Characteristics.

The description of different LDO types follow, except for the RTC description in the following section.

GENERAL-TYPE “PERFECT” LDOs

The general “PERFECT” LDOs are optimized to supply both analog and digital loads having ULTRA LOW

NOISE (10 µVRMS for IOUT > 5mA) and excellent PSRR (75 dB at 10 kHz) performance. They can be

programmed through the serial interface for different output voltage values.

For fast discharging of the output capacitors in shutdown, an internal 300Ωpulldown resistor to ground can be

set via program control.

In sleep mode quiescent current is lowered to 5µA for energy saving; in this mode these LDOs should not be

loaded by more than 3-5mA of output current.

The innovative design of these general type LDOs reduces the sensitivity to the placement of the output

capacitor. These general purpose LDOs do not need the output capacitor to be placed as close to the PMU as is

the case for normal LDOs. If a (1µF or more) capacitor is attached to a circuit load there is no need to place an

output capacitor at the PMU.

WILO-TYPE LDOs

Wide Input Low Output (WILO) LDOs. The WILO-type LDO is optimized for wide range supply and low output

voltage. It has good dynamic performance to supply different fast changing (digital) loads.

For proper operation, an input voltage of more than 2V is necessary. Hence, voltage drop on pass transistor

(dropout voltage) will always exceed 0.45V and is independent of output current (in specified current range).

For fast discharge of the output capacitors in shut down, an internal 300Ωpulldown resistor to ground can be set

via program control

MICRO-PWR LDO

This LDO is primarily used for internal supply purposes and fixed to 1.8V, but may deliver up to 30 mA of current

also externally. This LDO is ON even in Standby mode (with total PMU current consumption about 2µA) and user

may use it to supply some backup/always on system(s).

USB LDO

USB LDO is a high voltage LDO that uses VIN_CHG as a supply. It is used as a supply for D+ and D- buses as

well as the VTRM output. It has a 28V over voltage protection capability. Regulator provides 45 dB PSRR at 10

kHz on entire voltage selection range except 4.85V option. Here it is 30 dB and is due to small distance to

supply.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

GENERAL LDO ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V. (2)

Limits

Symbol Parameter Test Conditions LDO No. Typ Unit

Min Max

-2 2

VOUT Output voltage accuracy IOUT = 1mA, VOUT = 2.0V 1-10 %

-3 3

4,8 80

IMAX Output current rating mA

1-3, 5-7, 300

9, 10

VOUT +0.5V ≤VIN ≤4.5V (1) 4,8 300 80 mA

ISC Output current limit 1-3, 5-7,

VOUT +0.5V ≤VIN ≤4.5V (1) 650 300 mA

9, 10

ISLEEP Output current in sleep mode VOUT +0.5V ≤VIN ≤4.5V 1-10 3mA

Quiescent current in sleep

IQ5 µA

mode 4, 8 60 150 mV

VOUT = 3V;

VDO Dropout voltage 1-3, 4-7,

IOUT = IMAX(2) 100 200

9, 10

VOUT +0.5V ≤VIN ≤4.5V

Line regulation 1-10 3 mV

IOUT = IMAX

ΔVOUT 4, 8 0.5 mV

Load regulation 1mA ≤IOUT ≤IMAX 1-3, 5-7, 3.5

9, 10

10 Hz ≤f≤100 kHz

eNOutput noise voltage 1-10 15 µVRMS

COUT = 1µF (1)

Power supply ripple rejection f = 10 kHz, COUT = 1µF

PSRR 1-10 70 dB

ratio IOUT = 20 mA (1)

IOUT= 0 45

tSTART-UP Startup time from shutdown VOUT ≥0 - 90% 1-10 µs

VOUT ≥0 - 97% (1)

IOUT = 0 ≥200 mA -30

VLOADTRANS Load transient overshoot 1-10 mV

IOUT = 0 ≥200 mA (1) 35

VIN = 3.6 ≥4.2 ≥3.6;

VLINETRANS Line transient, peak-to-peak tr = tf = 30 µs 1-10 90 µV

IOUT = 50 mA (1)

VTRANSIENT Start-up transient overshoot COUT = 1µF, IOUT = IMAX(1) 1-10 1 30 mV

External output capacitance for

COUT 1-10 1 0.6 20 µF

stability

(2) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(1) Specified by design.

(2) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This

specification does not apply in cases it implies operation with an input voltage below the minimum appearing under Operating Ratings.

For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an

input voltage at or about 1.5V.

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

WILO-TYPE LDO ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V. (3) (4)

Limits

Symbol Parameter Test Conditions LDO No. Typ Unit

Min Max

-2 2

VOUT Output voltage accuracy IOUT = 1mA, VOUT = 2.0V 11-13 %

-3 3

ISC Output current limit VOUT = 0V 11-13 600 300 mA

IMAX Output current rating 300 mA

VDO Dropout voltage VOUT = 3V; IOUT = IMAX(1) 11-13 150 250 mV

VOUT +0.5V ≤VIN ≤4.5V

Line regulation 11-13 2.5

IOUT = IMAX

ΔVOUT mV

Load regulation 1mA ≤IOUT ≤IMAX 11-13 3

Quiescent current in normal

IQnormal (2) 17

mode 11-13 µA

Quiescent current in sleep

IQsleep (2) 4

mode 10 Hz ≤f≤100 kHz

eNOutput noise voltage COUT = 1µF, IOUT = 20 mA 11-13 85 µVRMS

VOUT = 1.8V (2)

Power supply ripple rejection f = 10 kHz, COUT = 1µF

PSRR 11-13 60 dB

ratio IOUT = 20 mA (2)

tSTARTUP Startup time from shutdown COUT = 1µF, IOUT = IMAX 11-13 35 µs

VTRANSIENT Startup transient overshoot COUT = 1µF, IOUT = IMAX 11-13 30 mV

External output capacitance for

COUT 11-13 1.0 0.5 20 µF

stability

(3) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(4) Specified for output voltages no less than 1.0V

(1) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This

specification does not apply in cases it implies operation with an input voltage below the minimum appearing under Operating Ratings.

For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an

input voltage at or about 1.5V.

(2) Specified by design.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

MICRO-PWR LDO ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V. (3)

Limits Unit

Symbol Parameter Test Conditions Typ Min Max

VOUT Output voltage accuracy IOUT = 1mA, VOUT = 1.80V 1.8 V

IMAX Maximum output current VOUT = 1.8V 30 mA

ISC Output current limit VOUT = 0V 220 mA

VOUT +0.5V ≤VIN ≤4.5V

Line regulation 2

IOUT = IMAX

ΔVOUT mV

Load regulation 1mA ≤IOUT ≤IMAX 1

f = 10 kHz, COUT = 1µF

PSRR Power supply ripple rejection ratio 45 dB

IOUT = 20 mA (1)

tSTARTUP Startup time from shutdown COUT = 1µF, IOUT = IMAX(1) 200 µs

VTRANSIENT Startup transient overshoot COUT = 1µF, IOUT = IMAX(1) 75 mV

External output capacitance for

COUT 1.0 0.6 20 µF

stability

(3) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(1) Specified by design.

USB LDO ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VVIN_CHG = 5.0V. (2)

Limits Unit

Symbol Parameter Test Conditions Typ Min Max

VOUT Output voltage accuracy IOUT = 1mA, VOUT = 3.30V 3.15 3.45 V

IMAX Maximum output current VOUT = 3.30V 50 mA

ISC Output current limit VOUT = 0V 300 mA

IOUT = IMAX

VDO Dropout voltage 330 mV

USB LDO VOUT = 4.85V (1)

VOUT +0.5V ≤VIN_CHG ≤6.5V

Line regulation 5

IOUT = 10 mA, VOUT = 4.85V

ΔVOUT mV

1mA ≤IOUT ≤IMAX

Load regulation 6

VOUT = 3.3V

f = 10 kHz, COUT = 1µF

PSRR Power supply ripple rejection ratio 45 dB

IOUT = 20 mA (2)

tSTARTUP Startup time from shutdown COUT = 1µF, IOUT = IMAX(2) 15 µs

VTRANSIENT Startup transient overshoot COUT = 1µF, IOUT = IMAX 250 mV

External output capacitance for

COUT 1.0 0.6 20 µF

stability

(2) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(1) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This

specification does not apply in cases it implies operation with an input voltage below the minimum appearing under Operating Ratings.

For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an

input voltage at or about 1.5V.

(2) Specified by design.

Product Folder Links: LP3925

28:

Interface

VTRM

LDO 1

VDAT_SRC

IDAT_SINK

VDAT_REF

D+

D-

USB Charger

Detection

OE_N*

GND_USB

1.5 kÖ

VIN_CHG

USB LDO

USB Tranceiver

Interface

LP3925

logic

1.5 kÖ

LP3925 logic

RCV*

SE0 VM*

DATA /VP

SPND*

28:

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

USB TRANSCEIVER

USB transceiver complies with USB 2.0 specification for full-speed (12Mb/s) device and low-speed (1.5Mb/s)

device operation. The transceiver also supports USB Charger Detection by “Battery Charging Specification

Revision 1.0 Mar 8, 2007”. The transceiver includes internal 1.5 kΩpullup resistor and it is supplied from USB

LDO.

USB transceiver can be configured to 3-pin, 4-pin or 5-pin interface.

If “USB transceiver not used” is configured, then USB transceiver is disabled in all circumstances, D+ and D-

pins are Hi-Z and also 1.5 kΩpullup resistor is disconnected. USB LDO has separate enable control and can be

used also if “USB transceiver is not used”.

Figure 16. USB Transceiver Block Diagram

USB Transceiver enable is controlled by register 0x41 (USB XCVR CONTROL bits) and 0x36 (bit ALLOW USB

XCVR IN SLEEP).

Product Folder Links: LP3925

28:

Interface +

LDO1

OE_N*

USB Tranceiver

SE0 VM*

DATA /VP*

28:

D+

D-

VTRM

1.5 k:

VIN_CHG

USB LDO

1.5 k:

OE_N

DATA /VP

SE0

GND_USB

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

If AUTOMATIC USB DETECTION bit is set 1 then in any circumstances the USB transceiver stays disabled until

USB Charger Detection is completed. USB Speed is determined by bit USB SPEED in register 0x4D:

USB SPEED 1 - Full Speed (12 Mb/s)

0 - Low Speed (1.5 Mb/s)

USB CHARGER DETECTION

USB Charger Detection works according to “Battery Charging Specification Revision 1.0 Mar 8, 2007” published

by USB-IF.

To enable USB Charger detection:

(1) bit AUTOMATIC USB DETECTION in register 0x4D should be set 1; and

(2) Charger should be enabled.

After VIN_CHG voltage was detected to be high enough to start charging USB Charger Detection waits 900 ms

and then checks D+ and D- for 100 ms. The detection result can be read form register 0x8D:

USB DETECTION DONE 1- USB Charger Detection completed

0 - USB Charger Detection is in progress or charger is disabled or there is no enough voltage

on VIN_CHG.

USB DETECTION RESULT 1 - USB Charger detected

0 - USB host detected

If AUTOMATIC USB DETECTION is enabled (bit is set 1) then USB Transceiver stays disabled in all

circumstances until USB Charger detection is completed. USB Charger Detection block gets supply from VTRM.

To have detection result correct then USB_LDO should be enabled

Figure 17. USB Transceiver Configured to 3-Pin Interface

Product Folder Links: LP3925

28:

LDO1

OE_N*

USB Transceiver

SE0/VM*

DATA/VP*

28:

D-

VTRM

1.5 kÖ

VIN_CHG

USB LDO

1.5 kÖ

OE_N

GND_USB

RCV* RCV

D+

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Table 4. INTERFACE PINS

DATA USB Interface data input/output

SE0 USB interface single ended 0 input/output

OE_N USB Output Enable, active low

Table 5. TRUTH TABLE FOR 3-PIN INTERFACE

Transmitting OE_N=0 Receiving OE_N=1

Inputs Outputs Inputs Outputs

DATA/VP* SE0/VM* D+ D- D+ D- DATA/VP* SE0/VM*

0 0 0 1 0 0 previous state 1

0 1 0 0 0 1 0 0

1 0 1 0 1 0 1 0

1 1 0 0 1 1 undefined 0

Figure 18. USB Transceiver Configured to 4-Pin Interface

Table 6. INTERFACE PINS

VM USB interface minus input/output

VP USB interface plus input/output

RCV Receiver data - single ended output from USB differential lines.

OE_N USB Output Enable, active low.

Product Folder Links: LP3925

28:

LDO1

OE_N*

USB Transceiver

DATA/VP*

28:

D-

VTRM

1.5 kÖ

VIN_CHG

USB LDO

1.5 kÖ

OE_N

RCV* RCV

GND_USB

SPND* SPND

SE0/VM*

D+

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Table 7. Controlling the Transceiver

OE_N VP VM FUNCTION

0 Input D+ = VP Input D−= VM Transmitting

1 Output D+ = VP Output D−= VM Receiving

Figure 19. USB Transceiver Configured to 5-Pin Interface

Table 8. Interface Pins

VM USB interface minus input/output

VP USB interface plus input/output

RCV Receiver data - single ended output from USB differential lines.

OE_N USB Output Enable, active low.

SPND USB suspend mode control input. A logical high will power down the differential receiver; VM and VP will remain active

with reduced power consumption.

Table 9. Controlling the Transceiver in 5-Pin Configuration

SPND OE_N D+/D−RCV VP/VM Function

0 0 Driving Active Input Normal Transmitting

0 1 Receiving Active Output Normal Receiving

1 0 Driving USB_RCV_OFF in 0x6B Input Low-Power Transmitting

1 1 Receiving USB_RCV_OFF in 0x6B Output Low-Power Receiving

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

USB CHARGER DETECTION ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VVIN_CHG = 5V. (1)

Limits Unit

Symbol Parameter Test Conditions Typ. Min Max

VDAT_SRC Data source voltage Load Current = 200 µA 0.6 0.5 0.7 V

VDAT_REF Data detect voltage 0.325 0.25 0.4

IDAT_SINK Data sink current 0.15V < VD−< 3.6V 100 50 150 µA

(1) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

USB TRANSCEIVER ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V, VTRM = 3.3V. (1)

Limits Unit

Symbol Parameter Test Conditions Typ Min Max

VBUS VIN_CHG supply voltage VIN_CHG pin works as USB VBUS pin 4.2 5.5 V

Low-speed VIN_CHG pin works as

VIN_CHG pin quiescent USB VBUS pin

IBUS 1.1 2.5 mA

current USB Transmitter Receiving

USB_LDO enabled, charger OFF

Transceiver DC Characteristics

0V < V < VTRM

ILO Hi-Z state data line leakage D+ if Low Speed; D- if High Speed, −10 10 µA

OE_N = 1.

VDI Differential input sensitivity |(D+)−(D−)|, VIN = 0.8V - 2.5V 200 mV

Differential common-mode

VCM Includes VDI Range (1) 0.8 2.5 V

range

Single-ended receiver 2.0

threshold high V

VSE Single-ended receiver 0.8

threshold low

Receiver hysteresis 100 mV

VOL Static output low OE_N = 0, RLOAD = 1.5 kΩto 3.6V 0.3

VOH Static output high OE_N = 0, RLOAD = 15 kΩto GND 2.8 3.6 V

IOUT = 0,

VTRM Termination voltage 3.15 3.45

USB_LDO programmed to 3.3V

RTRM Pullup resistance 1.5 kΩ

CIN Transceiver capacitance Pin to GND (1) 20 pF

D+, D−steady-state drive,

ZDRV Drive output resistance 28 44 Ω

IOUT = 15 mA from regulator (1)

Low-Speed Driver Characteristics

tRTransition rise time CLOAD = 50-600 pF (1) 75 300 ns

tFTransition fall time CLOAD = 50-600 pF (1) 75 300

tR/tFRise/fall time matching R/tF(1) 80 125 %

Full-Speed Driver Characteristics

tRTransition rise time CLOAD = 50 pF (1) 4 20 ns

tFTransition fall time CLOAD = 50 pF (1) 4 20

(1) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(1) Specified by design.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V, VTRM = 3.3V. ()

Limits Unit

Symbol Parameter Test Conditions Typ Min Max

tR/tFRise/fall time matching R/tF(1) 90 110 %

TCXO BUFFERS

The TCXO Buffer amplifies the 20 MHz sine wave from an external TCXO and shapes it into a buffered square

wave clock signal with controlled rise and fall times.

The buffer input connected to an internal decoupling capacitor. The output clock signal has a default slew rate of

325 V/µs with an external load capacitance of 12.5 pF. The slew rate can be adjusted by changing the two-bit

control data in the control register. This may be necessary if the actual load capacitance is considerably higher or

the clock slew rate needs to be slower for EMC reasons.

If TCXO buffers are enabled, then they need some time to reach a working point. During this time the output

signal can have an undesirable shape. To avoid unwanted signals, “TCXO in wait” control signals allow to set the

time delay before enabling TCXO buffer output. “TCXO out strength” signals modify buffer output drive strength.

Possible values of “TCXO in wait” and “TCXO out strength” are stated in the GPIO section. Buffers are supplied

from LDO1.

TCXO BUFFER ELECTRICAL CHARACTERISTICS(2)

Unless otherwise noted VBATT = VDD = 3.6V, CBYP_CHG = 1µF, CFB_CHG = 10 µF. Typical values and limits appearing in normal

type apply for TJ= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ

=−40°C to +125°C. Unless otherwise specified, the following applies for VBATT = 3.6V. (3)

Limits Unit

Symbol Parameter Test Conditions Typ Min Max

VIN Input voltage level (1) 750 mVP-P

VOH High-level output voltage DC at 1µA 2.5 2.4 V

VOL Low-level output voltage DC at 1µA 0.1 0.2

TPPropagation delay CL= 13 pF (1) 12

CL= 13 pF ns

TTT Output transition time (10% and 90% level) 7

(1)

VSR Output slew rate CL= 13 pF (1) 325 200 450 V/µs

CIN Input capacitance (1) 2 10 pF

(2) For warm-up time and driving strength, refer to multifunctional pins section.

(3) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(1) Specified by design.

BACKUP BATTERY CHARGER

Backup battery charger (BBC) is intended for charging an external coin battery. Its output is connected to

VCOIN-pin. It consists of Voltage Limited Current Source with 1kΩoutput resistor. By default it is always on. It is

possible to turn backup battery charger off via registers. VCOIN - voltage limit and ICOIN - current source values

are also programmable via registers (the possible values are stated in Backup battery charger selection table).

BBC has a reverse current protection. VCOIN-pin voltage can be measured by an internal ADC.

Product Folder Links: LP3925

ICOIN

VCOIN

Charge Current

limited by

CC mode

IVCOIN

VVCOIN

1 k: slope

Charge

Current

limited by

1 k:

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Figure 20. BBC IU Characteristics

MOMENTARY POWER LOSS

When power is removed from the LP3925 PMU and MPL function is enabled (register 0x81) then Momentary

Power Loss (MPL) timer starts as unexpected power down has occurred. This timer is set to the maximum

duration allowed for a momentary power loss (register 0x81). If power is restored before the timer expires, then

MPL block informs LP3925 control logic about MPL-event.

The MPL circuit is powered from VCOIN-pin. MPL timer uses 32.786 kHz RTC crystal oscillator for time base.

Host processor needs to enable the MPL function every time the device is powered up.

32.768 kHz CRYSTAL OSCILLATOR

There are two options for implementing the 32.768 kHz oscillator:

1. 1. An external crystal that is connected between XIN and XOUT. The external crystal ESR must not exceed

100 kΩ; if this value is exceeded the circuit may never start oscillating.

2. 2. An external oscillator module could be used by connecting the module output directly into XIN. When

using an external oscillator module, the XOUT pin should be unconnected.

Pins XIN and XOUT are not able to drive external load. Oscillator output is buffered to pin OSC_32KHZx Note.

Oscillator is powered by LDO1, thus before it is up, the oscillator will not start.

Product Folder Links: LP3925

Backup

Battery

Charger

Level

shifters

for

BBC

Data from registers

RTC

Level

shiters

with

lock/unlock

Interface

Note 1

Level

shifters

with

enable

VCOIN<1.2V disable

VCOIN>1.2V enable

Dedect if OK signal

from XOSC, if not OK

signal, then give

32 kHz to output

Clock from internal

RC oscillator

Control from registers

to OSC_32 KHZ

pad buffer

XIN XOUT

VCOIN

Note 1: If main supply drops, then interface gets locked automatically.

LP3925 liogic control unlocks the interface on startup.

MPL

XOSC

32 kHz

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

BACKUP BATTERY CHARGER ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V. (2)

Limits Unit

Symbol Parameter Test Conditions Typ Min Max

ILOAD = 1µA; VCOIN programmed to

VCOIN Voltage Limit −3 +3 %

3.00V

VCOIN pin shorted to GND

ICOIN Charging Current −20 +20 %

ICOIN programmed to 200 µA

RVCOIN Internal Series Resistor 1.0 0.5 1.6 kΩ

ILEAK Reverse leakage current VRTC pin current = 0 10

Charger Ground Current ILOAD = 0. 2.5 µA

IGND Load Regulation ILOAD = 0. 0.5

(2) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

REAL TIME CLOCK

The Real Time Clock (RTC) block is used for time tracking in any chip condition. It uses 32 kHz crystal oscillator

for accurate timekeeping and is supplied either from system supply in normal condition or from coin battery when

the PMU has no main power. The RTC gets power from VCOIN, with minimum operation above 1.9V. This RTC

has following features:

• Accurate time counting with fine-grained correction for long-term accuracies;

• Calendar for years 2000 - 2099 with leap year compensation and automatic weekday calculation;

• Two highly customizable alarms; and

• Data in software-friendly binary format.

Figure 21. RTC Functional Block Diagram

Calendar and alarm data is presented in following format:

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Table 10. Calendar and Alarm Data

Time Unit Register Data Represented Values

Seconds 000000 - 111011 0 - 59

Minutes 000000 - 111011 0 - 59

Hours 00000 - 10111 0 - 23

Day of Month 00001 - 11111 1 - 31

Month 0001 - 1100 January - December

Year 0000000 - 1100011 2000 - 2099

Weekday 0000001 - 1000000 (1-hot code) Monday - Sunday

RTC calendar and alarm registers are user-writable, except for calendar weekday registers, which are calculated

automatically and are read-only. All RTC registers are in RTC power domain. The registers are zeroed, if RTC is

powered up. As long as RTC is supplied, the alarm registers will hold the written data and the calendar will keep

track of time.

Writing data to a calendar register will initiate a calendar write sequence, which will last 3ms. During this time the

Alarms allow creating periodical or one-time events. The result of an alarm event depends on the PMU state. If

PMU is in standby, then alarm can cause PMU to start up. If PMU is in working mode, then alarm can create an

interrupt.

Alarm event happens if the alarm is activated (ALARM ACTIVATED bit is 1) and current RTC time matches the

time in all alarm configuration registers. To exclude a time unit value from matching check, write the unit's

IGNORE bit to 1. If alarm's weekday is not important or not known, then all weekday bits should be set to 1.

Interrupt or PMU startup is triggered at the start of an alarm event.

The RTC also has a time counting correction register. This can slightly change time counting speed to

compensate for oscillator inaccuracies. Correction events happen 7 times in an hour. The maximum correction

range is 241 ppm (corresponds to code 127) and one step size is approximately 1.9 ppm.

USIM INTERFACE

LP3925 includes a SIM/RUIM card interface level-shifter function. This can be used, if the processor I/O voltage

and SIM card I/O voltage have different values. The interface includes pins for 3 signals: reset, clock and data.

Reset and clock are unidirectional control signals, going from the processor to the SIM card. Data signal is

bidirectional.

The SIM card side of the level shifter is always supplied by LDO8. The processor side supply is user-selectable

between Buck2, LDO1 and LDO11. If the level shifter is enabled, then the supplies on both sides must be 1.5V

or higher to ensure proper operation.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

USIM LEVEL TRANSLATOR ELECTRICAL CHARACTERISTICS

Unless otherwise noted, CLDOx = CVIN_CHG+CVBUS+CVTRM = 1µF. Typical values and limits appearing in normal type apply for TJ

= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ=−40°C to

+125°C. Unless otherwise specified, the following applies for VBATT = 3.6V. (1)

Limits

Symbol Parameter Test Conditions Typ Unit

Min Max

0.25*

VILS Input low threshold VLDO1

RST_IN, CLK_IN logic inputs, LDO1 V

supply selected 0.75*

VIHS Input high threshold VLDO1 0.25*

VOLS Output low level VLDO8

SIM_RST, SIM_CLK logic outputs V

0.75*

VOHS Output high level VLDO8

RINPU SIM_IO pullup resistor 10 KΩ

VIL_SIM_IO Input low 0.3

VIH_SIM_IO Input high VDD-0.6V

SIM_IO

Output low level when 0.25* V

VOL_SIM_IO SIM_DATA=GND VLDO8

0.75*

VOH_SIM_IO Output high level VLDO8

RSPU SIM_DATA pullup resistor 20 13 KΩ

VIL_SIM_DATA Input low 0.3

0.75*

VIH_SIM_DATA Input high VLDO1

SIM_DATA, LDO1 supply selected V

Output low level when 0.25*

VOL_SIM_DATA SIM_IO=GND VLDO1

0.75*

VOH_SIM_DATA Output high level VLDO1

Timing

Clock frequency(1) 20 5MHz

(1) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(1) Specified by design.

Product Folder Links: LP3925

LDO11

LDO1

BUCK2

LDO8

20k 10k

SIM LS

SUPPLY

SELECT

SIM_DATA

SIM_CLK_IN

SIM_RST_IN

SIM_CLK

SIM_IO

SIM_RST

1.8V

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Figure 22. SIM Interface Level Shifters

COMPARATORS

Two general purpose comparators are available, which can be used for detecting the plugging of external

accessories or other events. Voltage comparators are available on multifunctional pins INP1 and INP2. 8

comparison thresholds are available between 400 mV and 2400 mV, the values can be found in the multifunction

pins section. Comparator state is available from registers as a read-only bit, or from multifunctional pins as a

direct data output. It is also possible to generate an interrupt every time the comparator state changes.

COMPARATOR ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V.(2)

Limits Unit

Symbol Parameter Test Conditions Typ Min Max

VTH Input threshold voltage Default setting 0.6 V

VTH2 Input threshold voltage 2 Default setting 1

IIL INP1, INP2

Input leakage current −1 1 µA

0≤VINPUT ≤VVIN1.

(2) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

ADC

LP3925 is equipped with a 12-bit ADC that has 8 inputs for measuring charging current, discharge current,

battery voltage (measuring at BATT pin), backup battery voltage, charger input voltage, VDD, temperature and

external signal through GPIO.

The inputs are scaled linearly to adapt the voltage/current range of the source to the input voltage range of the

A/D core.

Product Folder Links: LP3925

V(or I)= code(dec) * Full_Scale_Value

4095

TEMP(°C) = 390°C ± (code(dec) * 0.16°C)

IBATT (A) = code(dec) * VSNS

4095 * RSENSE

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

The ADC is clocked by the internal 4MHz system clock. The conversion result is available in the registers 0x88

and 0x89 in 3ms after the setting of the ADC CONV START bit in the 0x87 Register. The ADC will automatically

enter power save mode if conversions are not performed.

A/D CONVERTER DATA AND CONTROL REGISTERS

Two read only registers 0x88 and 0x89 provide access to the a/d conversion result. 8 most significant bits of the

data can be accessed in one read cycle. The Read/Write 0x87 register allows starting the conversion, source

selection and output format selection. Setting the ADC CONV START bit in the control register starts a new A/D

conversion. Setting ADC_FORMAT bit to 1 allows throwing out the MSB and shifting the result 1 bit left. This can

be used if result’s MSB is known, to get more data with one register read.

BATTERY DISCHARGE CURRENT MEASUREMENT

The discharge current is measured indirectly by measuring the voltage drop produced by discharge current on

the Rsense. The calculation of the current value is done by equation below:

(9)

The value of the appropriate VSNS (so that the maximum code would correspond to 1.2A) can be chosen in

reg.0x19. That is if RSENSE = 100 mΩ, the VSNS should equal 120 mV.

JUNCTION TEMPERATURE MEASUREMENT

Temperature measurement is performed in the rage of +390°C...−275°C which means that the following equation

is valid for calculating the chip's junction temperature:

(10)

OTHER ITEM CURRENT VOLTAGE MEASUREMENT

(11)

For example: If ADC input SEL is set as 0011, it will measure the BATT voltage. Full_Scale_Value = 4.80V; so

VBATT = code(dec) * 4.8/4095.

Figure 23. LP3925 ADC Temperature Range

Product Folder Links: LP3925

ADC3

(SE0/VM)

REF_OUT

10 kÖ

10 kÖ @ 25YC

NTC in Battery

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

ADC ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V. (1)

Limits

Symbol Parameter Test Conditions Typ Unit

Min Max

Resolution 12 bits

INL Integral Nonlinearity (1) −4 +4 LSB

DNL Differential Nonlinearity No missing code (1) −2 +2

Conversion Time (1) 3ms

(1) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(1) Specified by design.

REFERENCE OUTPUT

Reference Output Reference output voltage is used by the external blocks (plug-in microphone, ADCs, etc). This

voltage is achieved by the reference buffer and is supplied to the REF_OUT bump. Reference buffer has a load

capability of 1mA and when not used can be disabled while the output is pulled by an internal resistor to the

ground. A presented diagram shows a typical application of REF_OUT signal for battery temperature

measurement purpose, using an internal battery thermistor.

Figure 24. Typical REF_OUT Battery

Temperature Measurement

Application Diagram

REFERENCE BUFFER ELECTRICAL CHARACTERISTICS

Typical values and limits appearing in normal type apply for TJ= 25ºC. Limits appearing in boldface type apply over the

entire junction temperature range for operation, TJ=−40°C to +125°C. Unless otherwise specified, the following applies for

VBATT = 3.6V. (2)

Limits Unit

Symbol Parameter Test Conditions Typ Min Max

ILOAD = 0mA 0.3

VREF Reference voltage accuracy %

ILOAD = 1mA 1

ILOAD Load Current −1 +1 mA

RPULL_DOWN Integral Nonlinearity 400 kΩ

(2) All electrical characteristics having room-temperature limits are tested during production with TJ= 25°C. All hot and cold limits are

Specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

Product Folder Links: LP3925

Time slot Pattern

(1...8 és) (9 cycles, 63 time slots)

Pattern reading in time Time slots filled by PWM

code Example:

PWM CODE=40

Cycle = 7 time slots

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

UVLO OPERATION

UVLO measures system voltage on pin VDD and compares it to selected voltages. The function uses 2

comparators, which are configured in register address 0x85 (possible values are stated in the table below).

These comparators are combined into UVLO_N state, which can affect startup, cause shutdown or generate

interrupt. The state is readable in register address 0x8E bit 2.

UVLO_N state can change on following conditions:

• If system voltage is lower than UVLO LEVEL1 and UVLO LEVEL2, then UVLO_N state is set to '0'.

• If system voltage is higher than UVLO LEVEL1 and UVLO LEVEL2, then UVLO_N state is set to '1'.

Using different values for levels 1 and 2 provides a window for voltage drops under high load working conditions.

UVLO_N state '0' indicates that the voltage is below normal working range, so the system is not allowed to start

up. This state can also cause the system to shut down. UVLO_N state '1' indicates that the voltage is in normal

working range, so the system is allowed to start up and operate. State transition '1'->'0' causes an UVLO

interrupt, which can be sent to IRQ_N output.

CURRENT SINKS

LP3925 provides 3 current sinks, which can sink current for LEDs, vibration motors or other external functions.

Current sinks have selectable DC current value and also PWM control options. SINK1, SINK2 and SINK3 are

multifunction pins, so current sink function and DC current value are selectable with respective GPIO control bits

(described in the table in Multifunctional pins section). SINK1 has a 250 mA maximum current value, SINK2 and

SINK3 provide up to 100 mA. If the pin is configured as a current sink with a certain current, then PWM CODE

bits will switch that current on and off, according to the PWM algorithm.

The smallest unit in PWM control is a time slot. The length of a time slot is set with ISINK PWM TIME SLOT

SIZE bits. Smaller time slot causes faster switching, but increases non-linearity. 7 time slots form a PWM cycle.

Cycle is the current sink on-off switching period, so the main PWM frequency can be calculated as: Fpwm =

1/(7*Ttimeslot).

9 cycles, which is 9*7=63 time slots, form a PWM pattern. ISINK PWM CODE bits select, during how many of

these 63 time slots the current sink is active. Code 000000 means that the sink is always off. Code 111111 (63 in

decimal) means that the sink is always on.

Figure 25. Current Sinks PWM Control

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

SUPPORT FUNCTIONS

REFERENCE

LP3925 has internal reference block creating all necessary references and biasing for all blocks.

OSCILLATOR

There is internal oscillator giving clock to the bucks and to logic control.

Table 11. VVBATT = 3.6V

Parameter Typ Min Max Unit

Oscillator Frequency 4.0 3.9 4.1 MHz

THERMAL SHUTDOWN

The Thermal Shutdown (TSD) function monitors the chip temperature to protect the chip from temperature

damage caused by excessive power dissipation. The temperature monitoring function has two threshold values

TSD_H and TSD_L that result in protective actions.

When TSD_L +125°C is exceeded, then IRQ_N is set to low and “1” is written to TSD_L bit in both STATUS

The POWER UP operation after Thermal Shutdown can be initiated only after the chip has cooled down to the

+115°C threshold

Parameter Typ Unit

TSDH (1) 160

TSDL (1) 125 °C

TSDL Hysteresis (1) 10

(1) Specified by design.

I2C-COMPATIBLE SERIAL BUS INTERFACE

INTERFACE BUS OVERVIEW

The I2C compatible synchronous serial interface provides access to the programmable functions and registers on

the device.

This protocol uses a two-wire interface for bi-directional communications between the IC’s connected to the bus.

The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be

connected to a positive supply, via a pullup resistor of 1.5 kΩ, and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the serial clock (SCL).

DATA TRANSACTIONS

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Product Folder Links: LP3925

SDA

SCL

START CONDITION STOP CONDITION

Data Line

Stable:

Data Valid

SDA

SCL

Change

of Data

Allowed

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

Figure 26. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

START AND STOP

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

Figure 27. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

ACKNOWLEDGE CYCLE

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pulldown the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

Product Folder Links: LP3925

SCL S

Start

Condition

1 2 3 - 6 7 8 9

Data Output

Transmitter

Data Output

Receiver

Transmitter Stays Off the

Bus During the

Acknowledgement Clock

Acknowledgement

Signal From Receiver

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

Figure 28. Bus Acknowledge Cycle

“ACKNOWLEDGE AFTER EVERY BYTE” RULE

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the “acknowledge after every byte” rule.

When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging

(“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the

acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

ADDRESSING TRANSFER FORMATS

Each device on the bus has a unique slave address. The LP3925 operates as a slave device with the address

7h’xx (binary nnnnnnnn). Before any data is transmitted, the master transmits the address of the slave being

addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends

on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

CONTROL REGISTER WRITE CYCLE

• Master device generates start condition.

• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').

• Slave device sends acknowledge signal if the slave address is correct.

• Master sends control register address (8 bits).

• Slave sends acknowledge signal.

• Master sends data byte to be written to the addressed register.

• Slave sends acknowledge signal.

• If master will send further data bytes the control register address will be incremented by one after

acknowledge signal.

• Write cycle ends when the master creates stop condition.

CONTROL REGISTER READ CYCLE

• Master device generates a start condition.

• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').

• Slave device sends acknowledge signal if the slave address is correct.

• Master sends control register address (8 bits).

• Slave sends acknowledge signal.

Product Folder Links: LP3925

R/W

SSlave Address

(7 bits) '0' A A

Control Register Add.

(8 bits)

From Slave to Master

From Master to Slave

Slave Address

(7 bits) ASr '1'

R/W Data transferred, byte +

Ack/NAck

(8 bits) P

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

NA - ACKNOWLEDGE (SDA High)

Sr - REPEATED START CONDITION

Direction of the transfer

will change at this point

R/W

SSlave Address

(7 bits) '0' A A A P

Control Register Add.

(8 bits) (8 bits)

Data transferred, byte +

Ack

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

From Slave to Master

From Master to Slave

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

• Master device generates repeated start condition.

• Master sends the slave address (7 bits) and the data direction bit (r/w = “1”).

• Slave sends acknowledge signal if the slave address is correct.

• Slave sends data byte from addressed register.

• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.

• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

Address Mode

Data Read <Start Condition>

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Slave Address><r/w = ‘1’>[Ack]

[Register Data]<Ack or NAck>

… additional reads from subsequent register address possible

Data Write <Start Condition>

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

… additional writes to subsequent register address possible

Figure 29. Register Write Format

Figure 30. Register Read Format

Product Folder Links: LP3925

LP3925

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

www.ti.com

For more detailed control register information, or to order samples, please contact your local Texas

Instruments sales office or visit http://www.ti.com.

Product Folder Links: LP3925

LP3925

www.ti.com

SNVS672C –FEBRUARY 2011–REVISED MAY 2013

REVISION HISTORY

Changes from Revision B (May 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 52

Product Folder Links: LP3925

PACKAGE OPTION ADDENDUM

www.ti.com 17-May-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3925RME-A/NOPB NRND DSBGA YQB 81 250 Green (RoHS

& no Sb/Br) SNAG Level-1-260C-UNLIM -40 to 125 V030

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3925RME-A/NOPB DSBGA YQB 81 250 178.0 12.4 3.81 3.81 0.76 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3925RME-A/NOPB DSBGA YQB 81 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 2

MECHANICAL DATA

YQB0081xxx

www.ti.com

RMD81XXX (Rev A)

0.650±0.075

4214915/A 12/12

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

D: Max =

E: Max =

3.64 mm, Min =

3.58 mm

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its

semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers

should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated

circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and

services.

Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is

accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced

documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements

different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the

associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers

remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have

full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products

used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with

respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous

consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and

take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will

thoroughly test such applications and the functionality of such TI products as used in such applications.

TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,

including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to

assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any

way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource

solely for this purpose and subject to the terms of this Notice.

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI

products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,

enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically

described in the published documentation for a particular TI Resource.

Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that

include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE

TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY

RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or

endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR

REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO

ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL

PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,

INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF

PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,

DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN

CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949

and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.

Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such

products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards

and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must

ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in

life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.

Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life

support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all

medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.

TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).

Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications

and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory

requirements in connection with such selection.

Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-

compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

LP3925RME-A/NOPB LP3925RMX-A/NOPB LP3925RME-E/NOPB LP3925RMX-E/NOPB