CY7C1355C, CY7C1357C
9-Mbit (256 K × 36 / 512 K × 18) Flow-through
SRAM with NoBL™ Architecture
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05539 Rev. *G Revised October 8, 2010
9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture
Features
■No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■Can support up to 133-MHz bus operations with zero wait
states
❐Data is transferred on every clock
■Pin compatible and functionally equivalent to ZBT™ devices
■Internally self-timed output buffer control to eliminate the need
to use OE
■Registered inputs for flow-through operation
■Byte write capability
■3.3 V / 2.5 V I/O power supply (VDDQ)
■Fast clock-to-output times
❐6.5 ns (for 133-MHz device)
■Clock enable (CEN) pin to enable clock and suspend operation
■Synchronous self-timed writes
■Asynchronous output enable
■Available in JEDEC-standard and Pb-free 100-pin TQFP,
Pb-free and non Pb-free 119-ball BGA package and 165-ball
FBGA package
■Three chip enables for simple depth expansion.
■Automatic power-down feature available using ZZ mode or CE
deselect
■IEEE 1149.1 JTAG-compatible boundary scan
■Burst capability—linear or interleaved burst order
■Low standby power
Functional Description
The CY7C1355C/CY7C1357C[1] is a 3.3 V, 256 K × 36 /
512 K × 18 synchronous flow-through burst SRAM designed
specifically to support unlimited true back-to-back read/write
operations without the insertion of wait states. The
CY7C1355C/CY7C1357C is equipped with the advanced
No Bus Latency (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four byte write
select (BWX) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 2 of 32
C
MODE
BWA
BWB
WE
CE1
CE2
CE3
OE READ LOGIC
DQs
DQP
A
DQP
B
DQP
C
DQP
D
MEMORY
ARRAY
E
INPUT
REGISTER
BWC
BWD
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0 Q1
Q0
A0
A1
ADV/LD
CE ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
SE
ZZ SLEEP
CONTROL
Logic Block Diagram – CY7C1355C (256 K × 36)
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 3 of 32
C
MODE
BWA
BWB
WE
CE1
CE2
CE3
OE READ LOGIC
DQs
DQP
A
DQP
B
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0 Q1
Q0
A0
A1
ADV/LD
CE ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
SE
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1357C (512 K × 18)
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 4 of 32
Contents
Selection Guide ................................................................5
Pin Configurations ...........................................................5
Pin Definitions ..................................................................9
Functional Overview ......................................................10
Single Read Accesses ..............................................10
Burst Read Accesses ................................................10
Single Write Accesses ...............................................10
Burst Write Accesses ................................................11
Sleep Mode ............................................................... 11
Interleaved Burst Address Table
(MODE = Floating or VDD) .............................................11
Linear Burst Address Table (MODE = GND) ................ 11
ZZ Mode Electrical Characteristics ...............................11
Truth Table ...................................................................... 12
Partial Truth Table for Read/Write ................................12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ......................................13
TAP Controller State Diagram .......................................13
Test Access Port (TAP) ............................................. 13
TAP Controller Block Diagram ......................................13
PERFORMING A TAP RESET .................................. 14
TAP REGISTERS ...................................................... 14
TAP Instruction Set ................................................... 14
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ...............................15
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent .........................16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent .........................16
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 16
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
119-ball BGA Boundary Scan Order ............................. 18
165-ball FBGA Boundary Scan Order ........................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read/Write Waveforms ............................................. 23
NOP, STALL and DESELECT Cycles ....................... 24
ZZ Mode Timing ........................................................ 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Package Diagrams ........................................................ 29
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC Solutions ......................................................... 32
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 5 of 32
Selection Guide
Description 133 MHz 100 MHz Unit
Maximum access time 6.5 7.5 ns
Maximum operating current 250 180 mA
Maximum CMOS standby current 40 40 mA
Pin Configurations
100-pin TQFP Pinout
A
A
A
A
A1
A0
NC/288M
NC/144M
VSS
VDD
NC/36M
A
A
A
A
A
A
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
Vss/DNU
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
WE
CEN
OE
NC/18M
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV/LD
ZZ
MODE
NC/72M
CY7C1355C
BYTE A
BYTE B
BYTE D
BYTE C
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 6 of 32
Pin Configurations (continued)
100-pin TQFP Pinout
A
A
A
A
A1
A0
NC/288M
NC/144M
VSS
VDD
NC/36M
A
A
A
A
A
A
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
Vss/DNU
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
WE
CEN
OE
NC/18M
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV/LD
ZZ
MODE
NC/72M
CY7C1357C
BYTE A
BYTE B
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Document Number: 38-05539 Rev. *G Page 7 of 32
Pin Configurations (continued)
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 8 of 32
Pin Configurations (continued)
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 9 of 32
Pin Definitions
Name I/O Description
A0, A1, A Input-
synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB
BWC, BWD
Input-
synchronous
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
WE Input-
synchronous
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
ADV/LD Input-
synchronous
Advance/load input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK Input-
clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
CE1Input-
synchronous
Chip enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2, and CE3 to select/deselect the device.
CE2Input-
synchronous
Chip enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
CE3Input-
synchronous
Chip enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
OE Input-
asynchronous
Output enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
CEN Input-
synchronous
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.
ZZ Input-
asynchronous
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
DQsI/O-
synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPXI/O-
synchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During
write sequences, DQPX is controlled by BWX correspondingly.
MODE Input strap pin Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst
sequence. When tied to VDD or left floating selects interleaved burst sequence.
VDD Power supply Power supply inputs to the core of the device.
VDDQ I/O power supply Power supply for the I/O circuitry.
VSS Ground Ground for the device.
TDO JTAG serial output
synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be left unconnected. This pin is not available on
TQFP packages.
TDI JTAG serial input
synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be left floating or connected to VDD through a pull-up
resistor. This pin is not available on TQFP packages.
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 10 of 32
Functional Overview
The CY7C1355C/CY7C1357C is a synchronous flow-through
burst SRAM designed specifically to eliminate wait states during
write-read transitions. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. The clock
signal is qualified with the clock enable input signal (CEN). If
CEN is HIGH, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified
with CEN. Maximum access delay from the clock rise (tCDV) is
6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 7.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output will be tri-stated immediately.
Burst Read Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Accesses section
above. The sequence of the burst counter is determined by the
MODE input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will wrap
around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal burst counter regardless of the state
of chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see Truth Table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1355C/CY7C1357C provides byte write
capability that is described in the Truth Table. Asserting the write
enable input (WE) with the selected byte write select input will
selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the Write operations. Byte write capability has been
included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1355C/CY7C1357C is a common I/O device,
data should not be driven into the device while the outputs are
active. The output enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQPX inputs. Doing so will
TMS JTAG serial input
synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK JTAG
clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
NC – No connects. Not internally connected to the die. 18-Mbit, 36-Mbit, 72-Mbit, 144-Mbit,
288-Mbit, 576-Mbit and 1-Gbit are address expansion pins and are not internally connected
to the die.
VSS/DNU Ground/DNU This pin can be connected to Ground or should be left floating.
Pin Definitions (continued)
Name I/O Description
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 11 of 32
tri-state the output drivers. As a safety precaution, DQs and
DQPX are automatically tri-stated during the data portion of a
write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four write operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Accesses section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct BWX
inputs must be driven in each cycle of the burst write, in order to
write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 50 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns
tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns
tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 – ns
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Document Number: 38-05539 Rev. *G Page 12 of 32
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation Address
Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK DQ
Deselect cycle None H X X L L X X X L L->H Tri-state
Deselect cycle None X X H L L X X X L L->H Tri-state
Deselect cycle None X L X L L X X X L L->H Tri-state
Continue deselect cycle None X X X L H X X X L L->H Tri-state
READ cycle (begin burst) External L H L L L H X L L L->H Data out (Q)
READ cycle (continue burst) Next X X X L H X X L L L->H Data out (Q)
NOP/DUMMY READ (begin burst) External L H L L L H X H L L->H Tri-state
DUMMY READ (continue burst) Next X X X L H X X H L L->H Tri-state
WRITE cycle (begin burst) External L H L L L L L X L L->H Data in (D)
WRITE cycle (continue burst) Next X X X L H X L X L L->H Data in (D)
NOP/WRITE ABORT (begin burst) None L H L L L L H X L L->H Tri-state
WRITE ABORT (continue burst) Next X X X L H X H X L L->H Tri-state
IGNORE CLOCK EDGE (stall) Current X X X L X X X X H L->H –
SLEEP MODE None X X X H X X X X X X Tri-state
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1355C) WE BWABWBBWCBWD
Read H X X X X
Write no bytes written L H H H H
Write byte A – (DQA and DQPA)LLHHH
Write byte B – (DQB and DQPB)LHLHH
Write byte C – (DQC and DQPC)LHHLH
Write byte D – (DQD and DQPD)LHHHL
Write all bytes L L L L L
Truth Table for Read/Write[2, 3, 9]
Function (CY7C1357C) WE BWABWB
Read H X X
Write - no bytes written L H H
Write byte A – (DQA and DQPA)LHH
Write byte B – (DQB and DQPB)LHH
Write all bytes L L L
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write
selects are asserted, see Truth Table for details.
3. Write is defined by BWX, and WE. See Truth Table for read/write.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 13 of 32
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1355C/CY7C1357C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The TQFP
package does not offer this functionality. This part operates in
accordance with IEEE Standard 1149.1-1900, but doesn’t have
the set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of the
SRAM. Note the TAP controller functions in a manner that does
not conflict with the operation of other devices using 1149.1 fully
compliant TAPs. The TAP operates using JEDEC-standard
3.3 V or 2.5 V I/O logic levels.
The CY7C1355C/CY7C1357C contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of the TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register. (See TAP Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
TEST-LOGIC
RESET
RUN-TEST/
IDLE SELECT
DR-SCAN SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1 1
0 0
1 1
1
0
0
0
0 0
0
0
0 0
1
0
1
1
0
1
0
1
1
1
1 0
Bypass Register
0
Instruction Register
012
Identification Register
012293031 ...
Boundary Scan Register
012..x ...
Selection
Circuitry
Selection
Circuitry
TCK
TMS TAP CONTROLLER
TDI TDO
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 14 of 32
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 13. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.The IDCODE instruction is
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK# captured in the boundary
scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 15 of 32
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range[10, 11]
Parameter Description Min Max Unit
Clock
tTCYC TCK clock cycle time 50 – ns
tTF TCK clock frequency – 20 MHz
tTH TCK clock HIGH time 20 – ns
tTL TCK clock LOW time 20 – ns
Output Times
tTDOV TCK clock LOW to TDO valid – 10 ns
tTDOX TCK clock LOW to TDO invalid 0 – ns
Set-up Times
tTMSS TMS set-up to TCK clock rise 5 – ns
tTDIS TDI set-up to TCK clock rise 5 – ns
tCS Capture set-up to TCK rise 5 – ns
Hold Times
tTMSH TMS hold after TCK clock rise 5 – ns
tTDIH TDI hold after clock rise 5 – ns
tCH Capture hold after clock rise 5 – ns
Notes
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
tTL
Test Clock
(TCK)
123456
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE UNDEFINED
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 16 of 32
3.3 V TAP AC Test Conditions
Input pulse levels................................................VSS to 3.3 V
Input rise and fall times....................................................1 ns
Input timing reference levels.......................................... 1.5 V
Output reference levels ................................................. 1.5 V
Test load termination supply voltage ............................. 1.5 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Test Conditions
Input pulse levels................................................VSS to 2.5 V
Input rise and fall time .....................................................1 ns
Input timing reference levels........................................ 1.25 V
Output reference levels ............................................... 1.25 V
Test load termination supply voltage ........................... 1.25 V
2.5 V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50
O
50
TDO
1.25V
20pF
Z = 50
O
50
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)[12]
Parameter Description Conditions Min Max Unit
VOH1 Output HIGH voltage IOH = –4.0 mA, VDDQ = 3.3 V
IOH = –1.0 mA, VDDQ = 2.5 V
2.4 – V
2.0 – V
VOH2 Output HIGH voltage IOH = –100 µA VDDQ = 3.3 V 2.9 – V
VDDQ = 2.5 V 2.1 – V
VOL1 Output LOW voltage IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V
IOL = 8.0 mA VDDQ = 2.5 V – 0.4 V
VOL2 Output LOW voltage IOL = 100 µA VDDQ = 3.3 V – 0.2 V
VDDQ = 2.5 V – 0.2 V
VIH Input HIGH voltage VDDQ = 3.3 V 2.0 VDD + 0.3 V
VDDQ = 2.5 V 1.7 VDD + 0.3 V
VIL Input LOW voltage VDDQ = 3.3 V –0.5 0.7 V
VDDQ = 2.5 V –0.3 0.7 V
IXInput load current GND < VIN < VDDQ –5 5 µA
Identification Register Definitions
Instruction Field CY7C1355C
(256 K × 36)
CY7C1357C
(512 K × 18) Description
Revision number (31:29) 010 010 Describes the version number
Device depth (28:24) 01010 01010 Reserved for Internal Use
Device width (23:18) 001001 001001 Defines memory type and architecture
Cypress device ID (17:12) 100110 010110 Defines width and density
Cypress JEDEC ID code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor
ID register presence indicator (0) 1 1 Indicates the presence of an ID register
Note
12. All voltages referenced to VSS (GND).
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 17 of 32
Scan Register Sizes
Register Name Bit Size (× 36) Bit Size (× 18)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary scan order (119-ball BGA package) 69 69
Boundary scan order (165-ball FBGA package) 69 69
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high Z state. This instruction is not 1149.1 compliant.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1 compliant.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 18 of 32
119-ball BGA Boundary Scan Order
CY7C1355C (256 K × 36) CY7C1357C (512 K × 18)
Bit# ball ID Signal
Name Bit# ball ID Signal
Name Bit# ball Id Signal
Name Bit# ball Id Signal
Name
1K4 CLK 37 R6 A 1 K4 CLK 37 R6 A
2H4 WE 38 T5 A 2 H4 WE 38 T5 A
3M4CEN39 T3 A 3 M4 CEN 39 T3 A
4F4 OE 40 R2 A 4 F4 OE 40 R2 A
5B4ADV/LD
41 R3 MODE 5 B4 ADV/LD 41 R3 MODE
6G4 A 42 P2 DQP
D6 G4 A 42 Internal Internal
7C3 A 43 P1 DQ
D7 C3 A 43 Internal Internal
8 B3 A 44 L2 DQD8 B3 A 44 Internal Internal
9D6DQP
B45 K1 DQD9 T2 A 45 Internal Internal
10 H7 DQB46 N2 DQD10 Internal Internal 46 P2 DQPB
11 G6 DQB47 N1 DQD11 Internal Internal 47 N1 DQB
12 E6 DQB48 M2 DQD12 Internal Internal 48 M2 DQB
13 D7 DQB49 L1 DQD13 D6 DQPA49 L1 DQB
14 E7 DQB50 K2 DQD14 E7 DQA50 K2 DQB
15 F6 DQB51 Internal Internal 15 F6 DQA51 Internal Internal
16 G7 DQB52 H1 DQC16 G7 DQA52 H1 DQB
17 H6 DQB53 G2 DQC17 H6 DQA53 G2 DQB
18 T7 ZZ 54 E2 DQC18 T7 ZZ 54 E2 DQB
19 K7 DQA55 D1 DQC19 K7 DQA55 D1 DQB
20 L6 DQA56 H2 DQC20 L6 DQA56 Internal Internal
21 N6 DQA57 G1 DQC21 N6 DQA57 Internal Internal
22 P7 DQA58 F2 DQC22 P7 DQA58 Internal Internal
23 N7 DQA59 E1 DQC23 Internal Internal 59 Internal Internal
24 M6 DQA60 D2 DQPC24 Internal Internal 60 Internal Internal
25 L7 DQA61 C2 A 25 Internal Internal 61 C2 A
26 K6 DQA62 A2 A 26 Internal Internal 62 A2 A
27 P6 DQPA63 E4 CE127 Internal Internal 63 E4 CE1
28 T4 A 64 B2 CE228 T6 A 64 B2 CE2
29 A3 A 65 L3 BWD29 A3 A 65 Internal Internal
30 C5 A 66 G3 BWC30 C5 A 66 G3 BWB
31 B5 A 67 G5 BWB 31 B5 A 67 Internal Internal
32 A5 A 68 L5 BWA32 A5 A 68 L5 BWA
33 C6 A 69 B6 CE333 C6 A 69 B6 CE3
34 A6 A 34 A6 A
35 P4 A0 35 P4 A0
36 N4 A1 36 N4 A1
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 19 of 32
165-ball FBGA Boundary Scan Order
CY7C1355C (256 K × 36) CY7C1357C (512 K × 18)
Bit# ball ID Signal
Name Bit# ball ID Signal
Name Bit# ball ID Signal
Name Bit# ball ID Signal
Name
1 B6 CLK 37 R4 A 1 B6 CLK 37 R4 A
2B7 WE 38 P4 A 2 B7 WE 38 P4 A
3A7CEN39 R3 A 3 A7 CEN 39 R3 A
4B8 OE 40 P3 A 4 B8 OE 40 P3 A
5A8ADV/LD
41 R1 MODE 5 A8 ADV/LD 41 R1 MODE
6 A9 A 42 N1 DQPD6 A9 A 42 Internal Internal
7B10 A 43 L2 DQ
D7 B10 A 43 Internal Internal
8A10 A 44 K2 DQ
D8 A10 A 44 Internal Internal
9C11DQP
B45 J2 DQD9 A11 A 45 Internal Internal
10 E10 DQB46 M2 DQD10 Internal Internal 46 N1 DQPB
11 F10 DQB47 M1 DQD11 Internal Internal 47 M1 DQB
12 G10 DQB48 L1 DQD12 Internal Internal 48 L1 DQB
13 D10 DQB49 K1 DQD13 C11 DQPA49 K1 DQB
14 D11 DQB50 J1 DQD14 D11 DQA50 J1 DQB
15 E11 DQB51 Internal Internal 15 E11 DQA51 Internal Internal
16 F11 DQB52 G2 DQC16 F11 DQA52 G2 DQB
17 G11 DQB53 F2 DQC17 G11 DQA53 F2 DQB
18 H11 ZZ 54 E2 DQC18 H11 ZZ 54 E2 DQB
19 J10 DQA55 D2 DQC19 J10 DQA55 D2 DQB
20 K10 DQA56 G1 DQC20 K10 DQA56 Internal Internal
21 L10 DQA57 F1 DQC21 L10 DQA57 Internal Internal
22 M10 DQA58 E1 DQC22 M10 DQA58 Internal Internal
23 J11 DQA59 D1 DQC23 Internal Internal 59 Internal Internal
24 K11 DQA60 C1 DQPC24 Internal Internal 60 Internal Internal
25 L11 DQA61 B2 A 25 Internal Internal 61 B2 A
26 M11 DQA62 A2 A 26 Internal Internal 62 A2 A
27 N11 DQPA63 A3 CE127 Internal Internal 63 A3 CE1
28 R11 A 64 B3 CE228 R11 A 64 B3 CE2
29 R10 A 65 B4 BWD29 R10 A 65 Internal Internal
30 P10 A 66 A4 BWC30 P10 A 66 Internal Internal
31 R9 A 67 A5 BWB31 R9 A 67 A4 BWB
32 P9 A 68 B5 BWA32 P9 A 68 B5 BWA
33 R8 A 69 A6 CE333 R8 A 69 A6 CE3
34 P8 A 34 P8 A
35 R6 A0 35 R6 A0
36 P6 A1 36 P6 A1
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 20 of 32
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND........–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
DC voltage applied to outputs
in tri-state...........................................–0.5 V to VDDQ + 0.5 V
DC input voltage .................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage........................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch-up current .................................................... > 200 mA.
Operating Range
Range Ambient
Temperature VDD VDDQ
Commercial 0 °C to +70 °C 3.3 V
– 5% / + 10%
2.5 V – 5%
to VDD
Industrial –40 °C to
+85 °C
Electrical Characteristics
Over the Operating Range[13, 14]
Parameter Description Test Conditions Min Max Unit
VDD Power supply voltage 3.135 3.6 V
VDDQ I/O supply voltage for 3.3 V I/O 3.135 VDD V
for 2.5 V I/O 2.375 2.625 V
VOH Output HIGH voltage for 3.3 V I/O, IOH =4.0 mA 2.4 – V
for 2.5 V I/O, IOH =1.0 mA 2.0 – V
VOL Output LOW voltage for 3.3 V I/O, IOL=8.0 mA – 0.4 V
for 2.5 V I/O, IOL= 1.0 mA – 0.4 V
VIH Input HIGH voltage[13] for 3.3 V I/O 2.0 VDD + 0.3 V V
for 2.5 V I/O 1.7 VDD + 0.3 V V
VIL Input LOW voltage[13] for 3.3 V I/O –0.3 0.8 V
for 2.5 V I/O –0.3 0.7 V
IXInput leakage current
except ZZ and MODE
GND VI VDDQ –5 5 µA
Input current of MODE Input = VSS –30 – µA
Input = VDD –5µA
Input current of ZZ Input = VSS –5 – µA
Input = VDD –30µA
IOZ Output leakage current GND VI VDDQ, output disabled –5 5 µA
IDD VDD operating supply
current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz – 250 mA
10-ns cycle, 100 MHz –180 mA
ISB1 Automatic CE
power-down
current—TTL inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL
f = fMAX, inputs switching
All speeds – 110 mA
ISB2 Automatic CE
power-down
current—CMOS inputs
VDD = Max, device deselected,
VIN 0.3 V or VIN > VDD – 0.3 V,
f = 0, inputs static
All speeds – 40 mA
ISB3 Automatic CE
power-down
current—CMOS inputs
VDD = Max, device deselected, or
VIN 0.3 V or VIN > VDDQ – 0.3 V
f = fMAX, inputs switching
All speeds – 100 mA
ISB4 Automatic CE
power-down
current—TTL Inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL, f = 0, inputs
static
All speeds – 40 mA
Notes
13. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
14. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 21 of 32
Capacitance[15]
Parameter Description Test Conditions 100 TQFP
Max
119 BGA
Max
165 FBGA
Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz,
VDD = 3.3 V.
VDDQ = 2.5 V
555pF
CCLK Clock input capacitance 5 5 5 pF
CI/O Input/output capacitance 5 7 7 pF
Thermal Resistance[15]
Parameter Description Test Conditions 100 TQFP
Package
119 BGA
Package
165 FBGA
Package Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
29.41 34.1 16.8 C/W
JC Thermal resistance
(junction to case)
6.31 14.0 3.0 C/W
AC Test Loads and Waveforms
Note
15. Tested initially and after any design or process change that may affect these parameters.
OUTPUT
R = 317
R = 351
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
V
T
= 1.5 V
3.3 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
OUTPUT
R = 1667
R = 1538
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
VT= 1.25 V
2.5 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
3.3 V I/O Test Load
2.5 V I/O Test Load
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 22 of 32
Switching Characteristics
Over the Operating Range [16, 17]
Parameter Description –133 –100 Unit
Min Max Min Max
tPOWER VDD(typical) to the first access[18] 1– 1–ms
Clock
tCYC Clock cycle time 7.5 – 10 – ns
tCH Clock HIGH 3.0 – 4.0 – ns
tCL Clock LOW 3.0 – 4.0 – ns
Output Times
tCDV Data output valid after CLK rise – 6.5 – 7.5 ns
tDOH Data output hold after CLK rise 2.0 – 2.0 – ns
tCLZ Clock to low Z[19, 20, 21] 0– 0–ns
tCHZ Clock to high Z[19, 20, 21] –3.5 –3.5ns
tOEV OE LOW to output valid – 3.5 – 3.5 ns
tOELZ OE LOW to output low Z[19, 20, 21] 0– 0–ns
tOEHZ OE HIGH to output high Z[19, 20, 21] –3.5 –3.5ns
Set-up Times
tAS Address set-up before CLK rise 1.5 – 1.5 – ns
tALS ADV/LD set-up before CLK rise 1.5 – 1.5 – ns
tWES WE, BWX set-up before CLK rise 1.5 – 1.5 – ns
tCENS CEN set-up before CLK rise 1.5 – 1.5 – ns
tDS Data input set-up before CLK rise 1.5 – 1.5 – ns
tCES Chip enable set-up before CLK rise 1.5 – 1.5 – ns
Hold Times
tAH Address hold after CLK rise 0.5 – 0.5 – ns
tALH ADV/LD hold after CLK rise 0.5 – 0.5 – ns
tWEH WE, BWX hold after CLK rise 0.5 – 0.5 – ns
tCENH CEN hold after CLK rise 0.5 – 0.5 – ns
tDH Data input hold after CLK rise 0.5 – 0.5 – ns
tCEH Chip enable hold after CLK rise 0.5 – 0.5 – ns
Notes
16. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 23 of 32
Switching Waveforms
Read/Write Waveforms[22, 23, 24]
Notes
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
WRITE
D(A1)
123456789
CLK
tCYC
tCL
tCH
10
CE
tCEH
tCES
WE
CEN
tCENH
tCENS
BWX
ADV/LD
tAH
tAS
ADDRESS A1 A2 A3 A4 A5 A6 A7
tDH
tDS
DQ
COMMAND
tCLZ
D(A1) D(A2) Q(A4)Q(A3)
D(A2+1)
tDOH tCHZ
tCDV
WRITE
D(A2) BURST
WRITE
D(A2+1)
READ
Q(A3) READ
Q(A4) BURST
READ
Q(A4+1)
WRITE
D(A5) READ
Q(A6) WRITE
D(A7) DESELECT
OE
tOEV
tOELZ
tOEHZ
DON’T CARE UNDEFINED
D(A5)
tDOH
Q(A4+1)
D(A7)Q(A6)
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 24 of 32
NOP, STALL and DESELECT Cycles[25, 26, 27]
Notes
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Switching Waveforms (continued)
WRITE
D(A1)
123456789
CLK
tCYC
tCL
tCH
10
CE
tCEH
tCES
WE
CEN
tCENH
tCENS
BW
X
ADV/LD
tAH
tAS
ADDRESS A1 A2 A3 A4 A5 A6 A7
tDH
tDS
DQ
COMMAND
tCLZ
D(A1) D(A2) Q(A4)Q(A3)
D(A2+1)
tDOH tCHZ
tCDV
WRITE
D(A2) BURST
WRITE
D(A2+1)
READ
Q(A3) READ
Q(A4) BURST
READ
Q(A4+1)
WRITE
D(A5) READ
Q(A6) WRITE
D(A7) DESELECT
OE
tOEV
tOELZ
tOEHZ
DON’T CARE UNDEFINED
D(A5)
tDOH
Q(A4+1)
D(A7)Q(A6)
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 25 of 32
ZZ Mode Timing[28, 29]
Notes
28. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
29. DQs are in high Z when exiting ZZ sleep mode.
Switching Waveforms (continued)
tZZ
ISUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q) High-Z
DESELECT or READ Only
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 26 of 32
Ordering Information
The following table contains only the list of parts that are currently available. If you do not see what you are looking for, contact
your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product
summary page at http://www.cypress.com/products.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the
office closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz) Ordering Code
Package
Diagram Part and Package Type Operating
Range
133 CY7C1355C-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Commercial
CY7C1357C-133AXC
CY7C1355C-133BGC 51-85115 119-ball Ball Grid Array (14 × 22 × 2.4 mm)
100 CY7C1357C-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Commercial
CY7C1355C-100BGC 51-85115 119-ball Ball Grid Array (14 × 22 × 2.4 mm)
CY7C1357C-100BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 × 15 × 1.4 mm)
Ordering Code Definitions
Temperature Range: C = Commercial
Package Type: XX = AX or BG or BZ
AX = 100-pin TQFP (Pb-free)
BG = 119-ball BGA
BZ = 165-ball FPBGA
Speed Grade (133 MHz / 100 MHz)
Process Technology 90nm
135X = 1355 / 1357
1355 = FT, 256 Kb × 36 (9 Mb)
1357 = FT, 512 Kb × 18 (9 Mb)
CY7C = Cypress SRAMs
CY7C 135X C - XXX XX C
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 27 of 32
Package Diagrams
51-85050 *C
100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm), 51-85050
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 28 of 32
Package Diagrams (continued)
51-85115 *C
119-ball BGA (14 × 22 × 2.4 mm), 51-85115
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 29 of 32
Package Diagrams (continued)
51-85180 *C
165-ball FBGA (13 × 15 × 1.4 mm), 51-85180
[+] Feedback
CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 30 of 32
Acronyms Document Conventions
Units of Measure
Acronym Description
BGA ball grid array
CE chip enable
CEN clock enable
FPBGA fine-pitch ball grid array
JTAG Joint Test Action Group
NoBL No Bus Latency
OE output enable
SEL single event latchup
TCK test clock
TDI test data input
TMS test mode select
TDO test data output
TQFP thin quad flat pack
WE write enable
Symbol Unit of Measure
ns nano seconds
VVolts
µA micro Amperes
mA milli Amperes
ms milli seconds
MHz Mega Hertz
pF pico Farad
WWatts
°C degree Celcius
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CY7C1355C, CY7C1357C
Document Number: 38-05539 Rev. *G Page 31 of 32
Document History Page
Document Title: CY7C1355C/CY7C1357C 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture
Document Number: 38-05539
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 242032 See ECN RKF New data sheet
*A 332059 See ECN PCI Changed Boundary Scan Order to match the B rev of these devices
Removed description on Extest Output Bus Tri-state
Removed 117 MHz Speed Bin
Changed IDDZZ from 35 mA to 50 mA on Pg # 9
Changed ISB1 and ISB3 from 40 mA to 110 and 100 mA respectively
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Modified VOL, VOH test conditions
Corrected ISB4 Test Condition from (VIN VDD – 0.3V or VIN 0.3V) to (VIN VIH
or VIN VIL) in the Electrical Characteristic Table on Pg #18
Changed JA and Jc for TQFP Package from 25 and 9 °C/W to 29.41 and
6.13 °C/W
respectively
Changed JA and Jc for BGA Package from 25 and 6 °C/W to 34.1 and 14.0
°C/W
respectively
Changed JA and Jc for FBGA Package from 27 and 6 °C/W to 16.8 and 3.0
°C/W respectively
Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA
Packages
Updated Ordering Information Table
Changed from Preliminary to Final
*B 351895 See ECN PCI Changed ISB2 from 30 to 40 mA
Updated Ordering Information Table
*C 377095 See ECN PCI Modified test condition in note# 14 from VIH < VDD to VIH VDD
*D 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Changed three-state to tri-state
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*E 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*F 2896585 03/20/2010 NJY Removed obsolete parts from Ordering Information table. Updated package
diagram, data sheet template, and Sales, Solutions, and Legal Information
section.
*G 3032633 09/17/2010 NJY Updated Ordering Information and added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
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Document Number: 38-05539 Rev. *G Revised October 8, 2010 Page 32 of 32
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
All product and company names mentioned in this document are the trademarks of their respective holders
CY7C1355C, CY7C1357C
© Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
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