ft u.PD2732A-2 NEC LS VCS su = .PD2732A, .PD2732A-3 NEC Electronics U.S.A. Inc 003554 32,768- (4K x 8) BIT microcomputer divisioa A U 469 yp UVERASABLE PROM Description Block Diagram The pPD2732A is a 32,768- (4,096 x 8) bit ultraviolet eras- Data Outputs able and electrically programmable read-only memory Vee QO-> Oo-O7 (EPROM). It operates from a single +5V supply, making it GND O> Taha ideal for microprocessor applications. It features an output | | | | | | enable control and offers a standby mode with an attendant Vee 5 : : . aa utput Enable 75% savings in power consumption. PGM ~+| Chip Enable and _. . . CE 2]_ Program Logic Output Buffers A distinctive feature of the .PD2732A is a separate out-_ OE ~ put enable control (OE) from the chip enable control (CE). Y- : v-Gating The OE control eliminates bus contention in multiple-bus 2|_Decoder microprocessor systems. The PD2732A features fast, Ap-Av2_ | >| . : Address . simple one-pulse programming controlled by TTL-level inputs. } > x . 65,536-bit signals. Total programming time for all 32,768 bits is only +| Decoder : Cell Matrix 210 seconds. . Features LJ Ultraviolet erasable and electrically programmable [-] Access time 200ns max Absolute Maximum Ratings* L] Single location programming T, = 25C O Programmable with single pulse . Operating Temperature 10C to + 80C [] Low power dissipation: 125mA max active current Storage Temperature 65C to 4 125C 30mA max standby current Output Voltage 0.3V to +6V LJ Input/Output TTL-compatible for reading and Input Voltage 0.3Vto +6.5V programming L. Supply Voltage Voc 0.3V to +6V CO Single +5V power supply @w Supply Voltage Vpp 0.3V to +22V (] 24-pin ceramic DIP 3 ~* L] 21V programming Q. ==" *COMMENT: Exposing the device to stresses above Pin Configuration ane J those listed in Absolute Maximum Ratings could cause @D 7a permanent damage. The device is not meant to be LS = operated under conditions outside the limits described a,Q] 1 241] Vee (+5) = @ in the operational sections of this specification. Expo- A. 2 2311 Ag . sure to absolute maximum rating conditions for As] 3 22D) Ao ~~ extended periods may affect device reliability. A, q 4 21 a) Ay Ts oO a, ~ [1 OEVpp Capacitance MQ 6 syn PA O T= 25C;f = 1MHz a,Q 7 18[] CE C > c Limits Ay q 8 17 F oO, 2 Parameter Symbol Min. Typ Max Unit _Test Conditions 0,0 9 16110, input Capacita ~ o, 10 150 0, @ Emcept CEN, Cons 4 8 pF Vin = OV 0,41 1400, OEM pp Input = (OV) GND CJ 12 1310, Capaci Sma * pF Ym = ov Output Capacitance Cour 12 pF Vour = OV Pin Names DC Characteristics Ao- An Addresses = Read Mode and Standby Mode Oe OutputEnable = TT, = OC to + 70C; Vec = +5V + 5% 0-0, Data Outputs Limits cE Chip Enable Parameter Symbol Min Typ Max Unit Test Conditions Output High Voltage Vou 2.4 Villon = -- 400A Mode Selection Output Low Voitage VoL 0.45 v lo, = 2.4mA = Input High Voltage Vin 2.0 Veo + 1 Vv Pins cE OEVpp Vee Outputs Input Low Voltage Vin =04 08 Vv Mode Output Leakage = Aead i 7 7s Bon Current lo 10 pA Voy = 5.25V Standby Vie Dont Care +5 High Z Input except OE/Vpp 411 10 pA Vin = 5.25V Program Vi Vep i +5 Din Current OEVpp hue 100 pA Vin = 5.25 Program Verify Vv, Vv, +5 Doyt CE = Vi, Program Inhibit _ Vn Ver +5 High z Voc a Standby Neer 300 MA EW pp = Vy _ Table 1 Mode Selection unen' Active __.!cca 125 mA _OEMpp = CE = Vu -REV/1- 1DC Characteristics (Cont.) Program, Program Verify, and Program Inhibit Modes Ty = 25C + 5C3 Voc = +5V + 5%; Vpp =G4 21V 3 O.5V Limits Symbol Min Typ Max Unit Parameter Test Conditions Input High Voltage Vin 2.0 Veco +1 Vv Input Low Voltage Vit -0.1 0.8 v Input Leak Current |y 10 pA Vin = Vi Or Vig Output High Voltage Vou 2.4 Viton = 4002A Output Low Voltage Voi 0.45 Vlg. = 2.1mA Vec Current lec 85 125 mA Vpp Current Ipp 30 mA CE = Vy, OE = Vpp AC Characteristics Read Mode and Standby Mode T,, = 0C to + 70C: Voc = +52 5%) Limits 2732A-2 2732A 2732A-3 Test Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Conditions Address to gg ong 300 CE = Output Delay acc wo. 200 (280 } 300 nd OENVep = Vu Belay Output tee 200 250 300 ns OE = Wy Output __ Enable to toe 70 100 150 ns cE=V Output Delay Enable H nable High CE = to Output tor 60 90 130 ns CE = Vin Float Address to _CE = Output Hold = ton 9 9 "mS OE= Test Conditions Output Load: 1 TTL gate and C, = 100pF Input Rise and Fall Times: 20ns Input Pulse Levels: 0.8V to 2.2V Timing Measurement Reference Levels: Inputs: 1.0V and 2.0V Outputs: 0.8V and 2.0V Program, Program Verify, and Program Inhibit Modes Ta = 25C + 5C; Vec = +5V+t 5%} Vep = +21V + 0.5V Limits Parameter Symbol! Min Typ Max Unit Test Conditions Address Setup Time tas 2 us OE Setup Time toes 2 Ss Data Setup Time tos 2 BS Address Hold Time tan 0 Bs OE Hold Time toen 2 ps Data Hold Time ton 2 us Sy tor 8 90m Data Valid from CE toy 1 us CE=V, OF = Vy. Program Pulse Width tow 45 50 55 ms program Pulse Rise teat 50 ns Vpp Recovery Time tyr 2 HS Test Conditions Input Pulse Levels: 0.8V to 2.2V Input Timing Reference Levels: 1.0V and 2.0V Output Timing Reference Levels: 0.8V and 2V Input Rise and Fall Times: 20ns Function The PD2732A operates from a single + 5V power supply, making it ideal for microprocessor applications. Programming of the .PD2732A is achieved with a single 50ms TTL pulse. Total programming time for all 32,768 bits is only 210 seconds. Due to the simplicity of the program- ming requirements, devices on boards and in systems may be easily programmed without any special programmer. The PD2732A features a Standby mode which reduces the power dissipation from a maximum active power dissipation of 656mW to a maximum standby power dissipation of 158mW. This results in a 75% savings with no increase in access time. Erasure of the PD2732A programmed datacanbe ~ attained when exposed to light with wavelengths shorter than approximately 4,000 Angstroms (A). It should be noted that constant exposure to direct sunlight or room level fluorescent lighting could erase the 4PD2732A. Con- sequently, if the 4PD2732A is to be exposed to these types of lighting conditions for long periods of time, its window should be masked to prevent unintentional erasure. The recommended erasure procedure for the .PD2732A is exposure to ultraviolet tight with wavelengths of 2,537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be not less than 15W-sec/cm2. The erasure time is approximately 15 to 20 minutes using an ultraviolet lamp of 12,000,.W/cm2 power rating. During erasure, the .PD2732A should be placed within 1 inch of the lamp tubes. If the lamps have filters on the tubes, the filters should be removed before erasure. Operation The five operation modes of the PD2732A are listed in Table 1. In the Read mode the only power supply required is a + 5V supply. During programming, all inputs are TTL levels except for OE/V,, which is pulsed from TTL level to 21V. Read Mode When CE and OE/Vpp are at a low (0) level, read is set and data is available at the outputs after tp, from the falling edge of OE and ta, after setting the address. Standby Mode The PD273z2A is placed in a Standby mode with the application of a high (1) level TTL signal to the CE input. In this mode, the outputs are in a high impedance state, independent of the OE/V,, input. The active power dissipa- tion is reduced by 75% from 656mW to 158mW. Program Mode Programming begins by erasing all data and consequently having all bits in the high (1) level state. Data is then entered by programming a low (0) level TTL signal into the chosen bit location. The pPD2732< is placed in the Program mode by __ applying a high (1) level TTL signal to the CE and with OE/ - Vpp at + 21V. The data to be programmed is applied to the output pins in 8-bit parallel form at TTL levels. Any location can be programmed at any time, either indi- vidually, sequentially, or at random. When multiple .PD2732As are connected in parallel, except for CE, individual PD2732As can be programmed by applying a low (0) level TTL pulse to the CE input of the desired 1PD2732A to be programmed. Programming of multiple .PD2732As in parallel with the same data is easily accomplished. All the like inputs are tied together and programmed by applying a low (0) level TTL pulse to the CE inputs. Program Inhibit Mode Programming multiple 1PD2732As in parallel with different data is easier with the Program Inhibit mode. Except for CE, all like inputs (including OE) of the parallel PD2732As may be common. Programming is accomplished by apply- ing the TTL-level program pulse to the CE input with OE/ Vpp at + 21V. A high (1) level applied to the CE of the other w.PD2732A will inhibit it from being programmed._. Timiag Waveforms Read Mode Ao-12 i Addresses Valid CE top >| OF eS t _ tor oe | et bwe tance =| ton > Oo-7 ______ Ql valid Output } High Impedance High impedance Notes: OE may be delayed up to tacc tog after the falling edge of CE for read mode without impact on tacc- tor is specified from OE or CE, whichever occurs first. Program Mode Program Program Verify Address N Ao m1 Valid Output Address N t Valid Input AS | Address N Oo-7 OE/Vpp cE uy Note: 0.1,.F capacitor must be connected between OE/Vpp and ground to suppress spurious voltage transients which may damage the device. Program Verify Mode A verify should be performed on the programmed bits to determine that the data was correctly programmed. The program verify can be performed with CE and OE/V,, at low (0) levels. Output Deselect The data outputs of two or more ~PD2732As may be wire- ORed together to the same data bus. In order to prevent bus contention problems between devices, all but the selected 4.PD2732As should be deselected by raising the OE/V pp input to a TTL high. Window Label An opaque window label is provided unattached for the convenience of the user. The window label filters ultra- violet light frequencies, thus preventing accidental era- sure or long-term degradation caused by ambient light or sunlight. Package Outline .PD2732AD (Cerdip) 24 13 0.64R C) 1 12 H 4 t 4 \ eat 4 | | i 6G F |< D p+| fei Felcher | sem es item Millimeters inches A 33.02 Max 1.3 Max B 2.54 0.1 c 2.54 + 0.25 0.1 + 0.01 Oo 0.5 + 0.10 0.020 + 0.004 E 27.94 1.10 F 1.3 0.05 G 2.54 Min 0.1 Min H 0.51 Min 0.020 Min 1 5.08 Max 0.20 Max J 5.59 Max 0.22 Max K 15.24 0.60 L 14.66 0.58 M 0.25 + 0.05 0.010 + 0.002One Natick Executive Park _ N. KE Cc ; Natick, Massachusers bens 617- NEC Electronics U.S.A. Inc. eee aio microcomputer division The information in this document is subject to change without notice. NEC Electronics U.S.A. Inc. makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. NEC Electronics U.S.A. Inc. Oo assumes no responsibility for any errors that may appear in this document. NEC Electronics U.S.A. Inc. makes no commitment to update nor to keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics U.S.A. Inc. 1983 NEC Electronics U.S.A. Inc. Printed in U.S.A. 2732DS - REV 1-4-83 - 8K/16K