1/12June 2004
■HIGH SPEED:
fMAX = 67MHz (TYP.) at VCC =6V
■LOW POWER DISSIPATION:
ICC =2µA(MAX.) at TA=25°C
■HIGH NOISE IMMUNITY:
VNIH =V
NIL = 28% VCC (MIN.)
■SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=I
OL =4mA(MIN)
■BALANCED PROPAGATION DELAYS:
tPLH ≅tPHL
■WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
■PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 74
■SPACE GRADE-1: ESA SCC QUALIFIED
■50 krad QUALIFIED,100 krad AVAILABLE ON
REQUEST
■NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
■DEVICE FULLY COMPLIANT WITH
SCC-9203-050
DESCRIPTION
The M54HC74 is an high speed CMOS DUAL D
TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C2MOS technology.
A signal on the D INPUT is transferred on the Q
OUTPUT during the positive going transition of the
clock pulse. CLEAR and PRESET are
independent of the clock and accomplished by a
low on the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M54HC74
RAD HARD DUAL D TYPE FLIP FLOP
WITH PRESET AND CLEAR
PIN CONNECTION
ORDER CODES
PACKAGE FM EM
DILC M54HC74D M54HC74D1
FPC M54HC74K M54HC74K1
Rev. 1
DILC-14 FPC-14
M54HC74
2/12
Figure 1: IEC Logic Symbols
Figure 2:Input And Output Equivalent Circuit Table 1: Pin Description
Table 2: Truth Table
X : Don’t Care
PIN N° SYMBOL NAME AND FUNCTION
1,13 1CLR,2CLR Asynchronous Reset -
Direct Input
2, 12 1D, 2D Data Inputs
3, 11 1CK, 2CK Clock Input
(LOW-to-HIGH,
Edge-Triggered)
4, 10 1PR,2PR AsynchronousSet - Direct
Input
5, 9 1Q, 2Q True Flip-Flop Outputs
6, 8 1Q,2Q Complement Flip-Flop
Outputs
7 GND Ground (0V)
14 VCC Positive Supply Voltage
INPUTS OUTPUTS FUNCTION
CLR PR DCKQ Q
LHXXLH CLEAR
H L X X H L PRESET
L L X X H H ----
H H L L H ----
H H H H L ----
HHX QnQnNO CHANGE
M54HC74
3/12
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
Table 3: Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 4: Recommended Operating Conditions
Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VIDC Input Voltage -0.5 to VCC +0.5 V
VODC Output Voltage -0.5 to VCC +0.5 V
IIK DC Input Diode Current ±20 mA
IOK DC Output Diode Current ±20 mA
IODC Output Current ±25 mA
ICC or IGND DC VCC or Ground Current ±50 mA
PDPower Dissipation 300 mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature (10 sec) 265 °C
Symbol Parameter Value Unit
VCC Supply Voltage 2to6 V
VIInput Voltage 0 to VCC V
VOOutput Voltage 0 to VCC V
Top Operating Temperature -55 to 125 °C
tr,t
f
Input Rise and Fall Time VCC =2.0V 0 to 1000 ns
VCC =4.5V 0 to 500 ns
VCC =6.0V 0 to 400 ns
M54HC74
4/12
Table 5: DC Specifications
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA= 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input
Voltage 2.0 1.5 1.5 1.5 V4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Low Level Input
Voltage 2.0 0.5 0.5 0.5 V4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH High Level Output
Voltage 2.0 IO=-20 µA1.9 2.0 1.9 1.9
V
4.5 IO=-20 µA4.4 4.5 4.4 4.4
6.0 IO=-20 µA5.9 6.0 5.9 5.9
4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-5.2 mA 5.68 5.8 5.63 5.60
VOL Low Level Output
Voltage 2.0 IO=20 µA0.0 0.1 0.1 0.1
V
4.5 IO=20 µA0.0 0.1 0.1 0.1
6.0 IO=20 µA0.0 0.1 0.1 0.1
4.5 IO=4.0 mA 0.17 0.26 0.33 0.40
6.0 IO=5.2 mA 0.18 0.26 0.33 0.40
IIInput Leakage
Current 6.0 VI=V
CC or GND ±0.1 ±1±1µA
ICC Quiescent Supply
Current 6.0 VI=V
CC or GND 22040µA
M54HC74
5/12
Table 6: AC Electrical Characteristics (CL= 50 pF, Input tr=t
f= 6ns)
Table 7: Capacitive Characteristics
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Referto Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) =C
PD xV
CC xf
IN +ICC/2(perFLIP/
FLOP)
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA= 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
tTLH tTHL Output Transition
Time 2.0 30 75 95 110 ns4.5 8 15 19 22
6.0 7 13 16 19
tPLH tPHL Propagation Delay
Time (CK - Q, Q)2.0 48 150 190 225 ns4.5 16 30 38 45
6.0 13 26 32 38
tPLH tPHL Propagation Delay
Time (CLR,PR-
Q, Q)
2.0 51 150 190 225 ns4.5 17 30 38 45
6.0 15 26 32 38
fMAX Maximum Clock
Frequency 2.0 6.2 21 5 4.2 MHz4.5 31632521
6.0 37673025
tW(H)
tW(L)
Minimum Pulse
Width (CK) 2.0 18 75 95 110 ns4.5 6 15 19 22
6.0 6 13 16 19
tW(L) Minimum Pulse
Width (CLR,PR)2.0 21 75 95 110 ns4.5 7 15 19 22
6.0 6 13 16 19
tsMinimum Set-up
Time 2.0 15 75 95 110 ns4.5 4 15 19 22
6.0 3 13 16 19
thMinimum Hold
Time 2.0 0 0 0 ns4.5 0 0 0
6.0 0 0 0
tREM Minimum Removal
Time (CLR,PRto
CK)
2.0 0 25 30 35 ns4.5 0 5 6 7
6.0 0 4 5 6
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA= 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 5.0 5 10 10 10 pF
CPD Power Dissipation
Capacitance (note
1) 5.0 34 pF
M54HC74
6/12
Figure 4: Test Circuit
CL= 50pF or equivalent (includes jig and probe capacitance)
RT=Z
OUT of pulse generator (typically 50Ω)
Figure 5: Waveform - nCK To nQ, nQ Propagation Delay Times, and To nCK Setup And Hold
Times, nCK Minimum Pulse Width, Maximum nCK Frequency (f=1MHz; 50% duty cycle)
M54HC74
7/12
Figure 6: Waveform - nQ , nQ TO CLR,PRPropagation Delay Times, Minimum Pulse Width (nCLR
and nPR)(f=1MHz; 50% duty cycle)
Figure 7: Waveform - Minimum Pulse Width (nCLR and nPR), Minimum Removal Time (nCLR and
nPR TO nCK) (f=1MHz; 50% duty cycle)
M54HC74
8/12
Figure 8: Waveform - Minimum Pulse Width (nCLR,nPR,nCK)(f=1MHz; 50% duty cycle)
M54HC74
9/12
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 2.1 2.54 0.083 0.100
a1 3.00 3.70 0.118 0.146
a2 0.63 0.88 1.14 0.025 0.035 0.045
B 1.82 2.03 2.39 0.072 0.080 0.094
b 0.40 0.45 0.50 0.016 0.018 0.020
b1 0.20 0.254 0.30 0.008 0.010 0.012
D 18.79 19.00 19.20 0.740 0.748 0.756
E 7.36 7.62 7.87 0.290 0.300 0.310
e 2.54 0.100
e1 15.11 15.24 15.37 0.595 0.600 0.605
e2 7.62 7.87 8.12 0.300 0.310 0.320
F 7.11 7.75 0.280 0.305
I 3.70 0.146
K 10.90 12.1 0.429 0.476
L 1.14 1.27 1.5 0.045 0.050 0.059
DILC-14 MECHANICAL DATA
0016173H
M54HC74
10/12
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 6.75 6.91 7.06 0.266 0.272 0.278
B 9.76 9.95 10.14 0.384 0.392 0.399
C 1.49 1.95 0.059 0.077
D 0.10 0.127 0.15 0.004 0.005 0.006
E 7.50 7.62 7.75 0.295 0.300 0.305
F 1.27 0.050
G 0.38 0.43 0.48 0.015 0.017 0.019
H 6.0 0.236
L 18.75 22.0 0.738 0.866
M 0.38 0.015
N 4.31 0.170
FPC-14 MECHANICAL DATA
016029E
17
814
FG
D
H
A
B
M
N
H
C
L
E
M54HC74
11/12
Table 8: Revision History
Date Revision Description of Changes
01-Jun-2004 1 First Release
M54HC74
12/12
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