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02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
CM3131
3
Functional Description
The CM3131-01 / -11 and CM3131-02 provide
power for DDR-I/DDR-II memories from three
voltage regulators on-chip with either one or two
external N-FETs respectively. There is an over-
temperature thermal shutdown if any of the
regulators overheat. Each regulator has reverse
current protection in the event of any being shut
down.
The linear regulator-driver/s with external N-FET/s
can provide up to 15A at 2.5V/1.8V for the VDDQ of
DDR-I/-II memory, from an input supply voltage of
2.8V-3.6V. An external feedback resistor divider,
connected to the SENSE1 pin, enables selection of
VDDQ output voltages from 2.2V to 2.8V for use with
DDR-I memories requiring other than 2.5V for VDDQ.
VDDQ = 1.25V x (R1+R2)/R2. When SENSE1 is
connected to GND or left open, VDDQ is fixed at
2.50V (and VTT at 1.25V). For DDR-II operation,
VDDQ can be set from 1.7V to 1.9V.
The VTT regulator is a linear source-sink regulator
powered from the VDDQ output that supplies the VTT
supply required by DDR-I memory termination
resistors. This regulator sinks or sources up to 2A at
1.25V to or from the DDR-I bus termination resistors.
For DDR-II applications, the regulator sinks or
sources 0.65A at 0.9V. The VTT output voltage
accurately tracks VDDQ/2 to 1%. When there is no
VCC provided, VTT is powered down and its output is
0V. This regulator has overload current limiting of
2.5A.
The standby regulator is a LDO regulator that is
powered from a standby voltage, VSTBY, of 3.3V or
5V, and supplies a regulated output of up to 500mA
to the VDDQ of the DDR memory to enable it to retain
its contents during the standby mode. It provides
2.5V for DDR-I and 1.8V for DDR-II.
The CM3131-01 and CM3131-11 differ with regards
the selection of truth table for determining which S0-
S5 sequencing matrix the chip is set for. The
CM3131-02 has both EN and SEL pins to more
accurately define each Sx stage without monitoring
the VCC or VSTBY voltages.
Two CM3131s can be ganged together to provide
VDDQ power to dual channels of DDR memory, and
the memory controller chip of any chip set.
VTT
Linear
Source-Sink
VTT Reg
VDDQ
VDDQ
VDDQ
LDO Drive
SEL / EN
CCC
CSBY
CTT
CDDQ
5VSTBY / 3.3VSTBY
GND
GND
2.8V / 3.0V / 3.3V for DDR-I,
2.2V /2.5V / 3.3V for DDR-II
DRIVE
SENSE
VDDQ
LDO
VDDQ /V
TT
Control
VDDQ
FET
VTT
VCC
Only needed for
DDR-I if VDDQ is
not 2.5V, e.g. 2.6V
or 2.7V.
Set to 1.7V to
1.9V for DDR-II
PSOP-8
Internal VSBY voltage
doubler ensures VG> 5.3V
Drives any N-FET with CGS
<1200pF
R1
R2
VTT
Linear
Source-Sink
VTT Reg
VDDQ
VDDQ1
VDDQ
LDO Drives
CCC
CSBY
CTT
CDDQ 2
5VSTBY / 3.3VSTBY
GND
DRIVE1
CDDQ1
DRIVE2
VDDQ2
SENSE1
SENSE2
VDDQ1
VDDQ2
VDDQ
LDOs
VDDQ /V
TT
Control
SEL
GND
N-FET1
N-FET2
VTT
2.8V / 3.0V / 3.3V for DDR-I,
2.2V /2.5V / 3.3V for DDR-II
EN
VCC
CM3131-02
R1
R2
R3
R4
Examples of Single and Dual N-FET Drive Configurations
CM3131-01/11