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This document provides an overview of the MPC885 PowerQUICC™ family, describing

major functions and fea tures.

The MPC885 Power QUICC famil y cont ains a PowerPC™ proces sor c ore. I t is a 0.1 8-micr on

version of the MPC860 PowerQUICC family and can operate up to 133 MHz (2:1 mode) on

the MPC8xx core and up to 80 MHz (1: 1 mode) on the extern al bus. The MPC885 family ha s

a 1.8-V core and a 3.3-V I/O operation with 5-V TTL compatibility. The MPC885 integrated

communications controller family is a versatile one-chip integrated microprocessor and

peripheral combination that can be used in a variety of controller applications. It particularly

excels in both communications and networking systems.

The MPC885 family is a PowerPC architecture-based quad integrated communications

controller (PowerQUICC). The CPU on the MPC885 has a MPC8xx core, a 32-bit

microprocessor that implements the PowerPC architecture, incorporating memory

management un its (MMUs) and ins truction and data caches. The MPC885 is a super set of this

family of devices and is the main focus of this document.

Table 1 shows the functionality supported by the members of the MPC885 family:

Table 1. MPC885 Family

Part Cache Ethernet SCC SMC USB ATM Support Security

Engine

I Cache D Cache 10BaseT 10/100

MPC885 8 Kbyte 8 Kbyte Up to 3 2 3 2 1 Serial ATM and

UTOPIA

interface

Yes

MPC880 8 Kbyte 8 Kbyte Up to 2 2 2 2 1 Serial ATM and

UTOPIA

interface

Technical Summary

MPC885TS

Rev. 2.0, 12/2003

MPC885/MPC880

PowerQUICC™ Family

Technical Summary

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2MPC885/MPC880 PowerQUICC™ Family Technical Summary MOTOROLA

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Features Features

1Features

The MPC885 fami ly is compr is ed of thre e mod ules that ea ch use the 32- bit i nternal bus: a MPC8x x co re, a

system integration unit (SIU), and a communication processor module (CPM).

The following list summarizes the key MPC885 family features:

• Embedded MPC8xx core up to 133 MHz

• Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)

— The 133-MHz core frequency supports 2:1 mode only.

— The 66-/80-MHz core frequencies support both 1:1 and 2:1 modes.

• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two

32-bit general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch, without conditional execution.

— 8-Kbyte data cache and 8-Kbyt e instruction cache (see Table 1)

– 8-Kbyte instruction cache is two-way, set-associative with 256 sets in 2 blocks.

– 8-Kbyte data cache is t wo-way, set-associative with 256 sets.

– Cache coherency for both instruction and data caches is maintained on 16 bytes (4-word)

cache blocks.

– Caches are physically addressed, implement a least re cently used (LRU) replacem ent

algorithm, and are lockable on a cache block basis.

— MMUs with 32-ent ry TLB, fully associative instruction and data TLBs

— MMUs support multipl e page s izes of 4, 16, and 512 Kbyt es, and 8 Mbyt es; 16 vi rtual addres s

spaces and 16 protection groups

— Advanced on-chip-emulation debug mode

• Provides enhanced ATM functionality as found on the MPC862 and MPC866 families. The

MPC885 family includes the following:

— Improved ope ration, admin istration and maintenance (OAM) suppo rt

— OAM performance monitoring (PM) support

— Multiple APC priority levels available to support a range of traffic pace requirements

— Port-to-port switching capability without the need for RAM-based microcode

— Simultaneous MII (100BaseT) and UTOPIA (half- or full-duplex) capability

— Optional statistical cell counters per PHY

— U TOP IA L 2-compliant in terface with ad ded F IFO buffering to reduc e the total cell

transmission time and multi-PHY support. (The earlier UTOPIA L1 specification is also

supported.)

— Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode

— Supports full-duple x UT OPIA both mast er (ATM side) an d slave (P HY side) operation usi ng a

split bus

— AAL2/VBR functionality is ROM-resident

• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

• Thirty- two addr es s line s

• Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank

— Up to 30 wait states programmable per memory bank

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MOTOROLA MPC885/MPC880 PowerQUICC™ Family Technical Summary 3

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Features

— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory

devices

— DRAM controller programmable to support most size and speed memory interfaces

— Four CAS lines, fo ur WE lines, one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbyte–256 Mbyte)

— Selectable write protection

— On-chip bus arbitration logic

• General-purpose timers

— Four 16-bit timers or two 32-bit timers

— G ate m ode c an ena ble/d isab le cou nting

— Interrupt can be masked on reference match and event capture

• T wo fast Ethernet controllers (FEC)—T wo 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS interface

through MII and/or RMII interfaces

• System integration unit (SIU)

— Bus monitor

— Software w atchdog

— Periodic interrupt timer (PIT)

— Clock synthe siz er

— Decrementer and time base

— Reset controller

— IEEE 1149.1 test access port (JTAG)

• Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,

802.11i, and iSCSI processing. Available on the MPC885, the security engine contains one

crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:

— Data encryption standard execution unit (DEU)

– DES, 3DES

– Two key (K1, K2, K1) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rijndael symmetric key cipher

– ECB, CBC, and counter modes

– 128-, 192-, 256-bi t key len g th s

— Message digest execution unit (MDEU)

– SHA with 160- or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Crypto-channel supporting multi-command descriptor chains

— Integrated controller managing internal resources and bus mastering

— Buffer size of 256 bytes for the DEU, AESU, and MDEU, with flow control for large data sizes

• Interrupts

— Six extern al interrupt req uest (IRQ) lines

— Twelve port pins with interrupt capability

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4MPC885/MPC880 PowerQUICC™ Family Technical Summary MOTOROLA

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Features Features

— 23 internal interrupt sources

— Programmable priority between SCCs

— Programmable highest priority request

• Communications processor module (CPM)

— R ISC controlle r

— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT

MODE, and RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels

— 8-Kbytes of dual-port RAM

— Several serial DMA (SDMA) channels to support the CPM

— Three parallel I/O registers with open-drain capability

• On-chip 16 x 16 multiply accumulate controller (MAC)

— One operation per clock (two clock latency, one clock blockage)

— MAC operates concurrently with other instructions

— FIR loop—Four clocks per four multiplies

• Four ba ud ra te genera tors

— Independent (can be connected to any SCC or SMC)

— Allow changes during operation

— Autobaud support option

• Up to three se rial comm unicatio n con trollers (SCCs) sup portin g the following protocols:

— Serial ATM capability on SCCs

— Optional UTOPIA port on SCC4

— Ethernet/IEEE 802.3 optional on the SCC(s), supporting full 10-Mbps operation

— HDLC/SDLC

— HDLC bus (implements an HDLC-based local area network (LAN))

— Asynchronous HDLC to support PPP (point-to-point protocol)

—AppleTalk

— Universal asynchronous receiver transmitter (UART)

— Synchronous UART

— S erial infrared (IrDA )

— Binary synchronous communication (BISYNC)

— Totally transparent (bit st reams)

— Totally transparent (frame based with optional cyclic redundancy check (CRC))

• Up to two serial management channels (SMCs) supporting the following protocols:

— UART (low-spee d opera ti on)

— Transparent

— General circuit interface (GCI) controller

— Provide management for BRI devices as GCI controller in time-division multiplexed (TDM)

channels

• Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host controller,

or both for testing purposes (loopback diagnostics)

— USB 2.0 full-/low-speed compatible

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MOTOROLA MPC885/MPC880 PowerQUICC™ Family Technical Summary 5

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Features

— The USB function mode features are as follows:

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– CRC5 checking

– NRZI encoding/decoding with bit stuffing

– 12- or 1.5-Mbps data rate

– Flexible data buffers wit h multiple buffer s per frame

– Automatic retransmission upon transmit error

— The USB host controller features are as follows:

– Supports control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– NRZI encoding/decoding with bit stuffing

– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data

rate configuration). Note that low-speed operation requires an external hub.

– Flexible data buffers wit h multiple buffer s per frame

– Supports local loopback mode for di agnostics (12 Mbps only)

• SPI (serial peripheral interface)

— Supports master and slave modes

— Supports multiple-master operation on the same bus

•I

2C (inter-integrated circuit) port

— Supports master and slave modes

— Supports a multiple-master environment

• Time-slot assigner (TSA)

— Allows SCCs and SMCs to run in multip lexed and/o r non-mult iplexed operation

— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined

— 1- or 8-bit resolution

— Allows independ ent transmi t and receive routing , fra me synchro nization, and clocking

— Allows dynamic ch anges

— Can be internally co nnected to five serial channels (thr ee SCCs and two SMCs)

• Paralle l interface port (PIP)

— Centroni cs int er fa ce support

— Supports fast connection between compatible ports on MPC885/880 and ot her MPC8xx

devices

• Tw o PCMCIA interfaces

— Master (socket) interface, PCI 2.1–complian t

— Supports two independent PCMCIA sockets

— Eight memory or I/O windo ws support ed

• De bug interfa ce

— Eight comparator s: four operate on inst ruction add ress, two operate on data address, an d two

operate on data

— Supports conditions: = ≠ < >

— Each wa tch point can generate a b reakpoint in ternally

• Normal high and normal low power modes to conserve power

• 1.8-V core and 3.3-V I/O operation

• The MPC885/880 comes in a 357-pin ball grid array (PBGA) package

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6MPC885/MPC880 PowerQUICC™ Family Technical Summary MOTOROLA

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Features Features

The MPC885 block diagram is shown in Figure 1.

Figure 1. MPC885 Block Diagram

Bus

System Interface Unit (SIU)

Embedded

Parallel I/O

Memory Controller

Timers Interrupt

Controllers 8-Kbyte

Dual-Port RAM

System Functions

8-Kbyte

Instruction Cache

32-Entry ITLB

Instruction MMU

8-Kbyte

Data Cache

32-Entry DTLB

Data MMU

Instruction

Bus

Load/Store

Bus

Unified

4 Baud Rate

Generators

Parallel Interface Port

Internal

Bus Interface

Unit

External

Bus Interface

Unit

Timers

32-Bit RISC Controller

and Program

ROM

Serial Interface

I2C

SPISMC2SMC1

MPC8xx

Processor

Core

SCC2

Serial Interface

PCMCIA-ATA Interface

Virtual IDMA

and

Serial DMAs

SCC4/

Security Engine

AESU DEU MDEU

Controller

Channel

DMAs

FIFOs

10/100

MIII / RMII

BaseT

Media Access

Control

Fast Ethernet

Controller

UTOPIA

SCC3 USB

Slave/Master IF

Time-S lot Assigner

DMAs

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MOTOROLA MPC885/MPC880 PowerQUICC™ Family Technical Summary 7

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Embedded MPC8xx Core

The MPC880 block diagram is shown in Figure 2.

Figure 2. MPC880 Block Diagram

2 Embedded MPC8xx Core

The MPC885 family int eg rat es an embedded MPC8xx c or e wi th high-performan ce, low-power perip her al s

to extend the Motorola data communications family of embedded processors further into high-end

communications and networking products.

The core is compliant with the UISA (user instruction set architecture) portion of the PowerPC architecture.

It has an integer unit (IU) and a load/store unit (LSU) that execute all integer and load/store operations in

hardware. The co re supports integer operations on a 32-bit int ernal data path and 32-bit a rithmetic hardware.

The core interf ace to the internal and external buse s is 32 bits.

The IU uses thirty-two 32-bit GPRs for source and target operands. Typically, it can execute one integer

instruction per cl ock cycle. Eac h ele m ent in th e int eger block is clocked onl y when valid dat a is in the data

queue and is ready for operation. This holds power consumption of the device to the absolute minimum.

Bus

System Interface Unit (SIU)

Embedded

Parallel I/O

Memory Controller

Timers Interrupt

Controllers 8-Kbyte

Dual-Port RAM

System Functions

8-Kbyte

Instruction Cache

32-Entry ITLB

Instruction MMU

8-Kbyte

Data Cache

32-Entry DTLB

Data MMU

Instruction

Bus

Load/Store

Bus

Unified

4 Baud Rate

Generators

Parallel Interface Port

Internal

Bus Interface

Unit

External

Bus Interface

Unit

Timers

32-Bit RISC Controller

and Program

ROM

Serial Interface

I2C

SPISMC2SMC1

MPC8xx

Processor

Core

SCC3

Serial Interface

PCMCIA-ATA Interface

Virtual IDMA

and

Serial DMAs

SCC4/

DMAs

FIFOs

10/100

MIII / RMII

BaseT

Media Access

Control

Fast Ethernet

Controller

UTOPIA

USB

Slave/Master IF

Time Slot Assigner

DMAs

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8MPC885/MPC880 PowerQUICC™ Family Technical Summary MOTOROLA

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System Interfa ce Unit (SIU) System Interfa ce Unit (SIU)

The core is integrated with MMUs as well as instruction and data caches. Each MMU provides a 32-entry,

fully-associative instruction and data TLB, with multiple page sizes of 4, 16, 512, and 256 Kbytes and

8 Mbytes. It supports 16 virtual address spaces with 8 protection groups. Three special scratch registers

support software table search and update operations.

The inst ruction ca che is two-way, set-ass ociative wi th physic al address ing . I t allows si ngl e- cycle access on

hits wit h no added laten cy for misses. It has fou r words per block, sup porting a fo ur-bea t burst line fill usi ng

an LRU (le ast rec ently us ed) repl acement al gorithm. Th e cache c an be loc ked on a pe r cache block bas is fo r

application-critical routines.

The data cache is two-way, set-associative with physical addressing. It allows single-cycle accesses on hits

with one added clock latency for misses. It has four words per cache block, supporting burst line fill using

LRU replacement. The cache can be locked on a per block basis for application critical routines. The data

cache can be programmed through the MMU to support copy back or write through. Cache-inhibit mode

can be programmed per MMU page.

The deb ug interf ace provide s debug capa bilitie s without de grading ope ration sp eed. This int erface s upports

six watch point pins that are us ed to detect software events. Four of its eight interna l compara tors oper ate on

the effective address on the address bus, two operate on the effective address on the data address bus, and

two operate on the data bus. The core can make =, ≠, < , an d > com pa ri so n s to ge ne ra te wa tc hp oi nts . Ea ch

watchpoint can then generate a break point that can be configured to trigger in a programmable number of

events.

3 System Interface Unit (SIU)

The SIU on the MPC885 family integrates general-purpose features useful in almost any 32-bit processor

system . Dynamic bus s izing al lows 8-, 16-, and 32-bit periphe rals and memory t o exist in the 3 2-bit system

bus mode.

The SIU also provides power management functions, reset control, a decrementer, and a time base.

The memory controller supports up to eight memory banks with glueless interfaces to DRAM, SRAM,

SSRAM, EPROM, Flash EPROM, SDRAM, EDO, and other peripherals with 2-clock cycle access to

external SRAM and bursting support. It provides variable block sizes from 32 Kbytes to 256 Mbytes. The

memory controller provides 0–30 wait states for each memory bank and can use address type matching to

qualif y each memory bank acces s. It provi des four byte -enable signals, an output-enable signal, and a boot

chip select available a t reset.

The DRAM interface supports port sizes of 8, 16, and 32 bits. Memory banks can be defined in depths of

256 or 512 Kbytes or 1, 2, 4, 8, 16, 32, or 64 Mbytes for all port sizes. The memory depth can be 64 and

128 Kbytes for 8-bit memory or 128 and 256 Mbytes for 32-bit memory. The DRAM controller supports

page-mode access for successive transfers within bursts. The MPC885 supports a glueless interface to one

bank of DRAM wh il e ex ter nal buffers are requi red for additional memory ban k s. Th e re fr esh unit p rov ides

CAS before RAS, a pr ogrammable r ef re sh t i mer, refresh act ive du ri ng e xternal reset, disable r efresh mod e,

and stack ing up to seven refresh cycles. The DRAM interface uses a programmable state machine to sup port

almost any memory interface.

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MOTOROLA MPC885/MPC880 PowerQUICC™ Family Technical Summary 9

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PCMCIA Controller

4 PCMCIA Controller

The P CMC IA in terf a ce is a m a ster (s oc ket ) c o ntro ll e r and is PCI 2.1 - co mp li ant . Th e inte rf ac e su p por ts up

to two independent PCMCIA sockets requiring only external transceivers/buffers. The interface provides

eight memory or I/O windows, where each window can be allocated to a particular socket. If only one

PCMCIA port is used, the unused port may be used as general-purpose input with interrupt capability.

5 Power Management

The MPC885 family supports two power management features including normal high and normal low

power modes. The full on mode leaves the MPC885 processor fully powered with all internal units operating

at full processor speed. A gear mode is determined by a clock divider, allowing the operating system to

reduce the processor’s operational frequency and operate in normal low mode.

6 Security Engine

A block diagram of the security engine’s internal architecture is shown in Figure 3. The MPC8xx bus

interface (8xx/IF) module is designed to transfer 32-bit words between the MPC8xx bus and any register

inside the security engine core.

An operation begins with a write of a pointer to the crypto-channel fetch register, which points to a data

packet descriptor. The channel requests the descriptor and decodes the operation to be performed. The

channel then requests the controller to assign crypto-execution units and fetch the keys, IVs, and data

needed to perform the given operation. The controller satisfies the requests by assigning execution units to

the channel and by making requests to the master interface. As data is processed, it is written to the

individual execution unit’s output buffer and then back to system memory through the 8xx/IF module.

Figure 3. Security Engine Functional Blocks

7 Fast Ethernet Controller (FEC)

The FECs comply with the IEEE 802.3 specification for 10- and 100-Mbps connectivity. Full-duplex

100-Mbps operation is supported at system clock rates of 40 MHz and higher. A 25-MHz system clock

supports 10-Mbps operation or half-duplex 100-Mbps operation.

8xx

Bus/IF

Unit

Controller

Channel

FIFO

FIFO FIFO

MDEUAESUDEU

Crypto-

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10 MPC885/MPC880 PowerQUICC™ Family Technical Summary MOTOROLA

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Universal Serial Bus (USB) Universal Serial Bus (USB)

The implementation of bursting DMA reduces bus usage. Independent DMA channels for accessing BDs

and transmit and receive data minimize latency and FIFO depth requirements.

T ransmit and receiv e FIFOs further reduce bus usage by localizin g all collisions to the FEC. T ransmit FI FOs

maintain a full collision window of transmit frame data, eliminating the need for repeated DMA over the

system bus when collisions occ ur . On the r eceive side, a full collision wi ndow of data is recei ved before any

receive data is transferred into system memory, allowing the FIFO to be flushed in the event of a runt or

collid ed fram e, with no DMA activi ty. However, external memory for buf fer s and BDs is requi red; on- chip

FIFO s are desi gned only t o compens ate fo r collisions an d system bus la tency.

Independent TxBD and RxBD rings in external memory allow nearly unlimited flexibility in memory

management of transmit and receive data frames. External memory is inexpensive, and because BD rings

in external memory have no inherent size limitations, memory management can be easily optimized to

system needs.

8 Universal Serial Bus (USB)

The univ ersal serial bus (USB) is an indus try-standar d extension to the PC archite cture. The USB control ler

on the MPC885 family supports data exchange between a wide range of simultaneously accessible

peripherals. Attached peripherals share USB bandwidth through a host-scheduled, token-based protocol.

The USB physical interconnect is a tiered-star topology, and the center of each star is a hub. Each wire

segment is a point-to-poin t connection betwee n the host and a hub or func tion, or a hub connected to another

hub or a f unction. T he USB transf ers sign al and power over a fou r- wire cable , and t he signali ng occurs over

two wires and point-to-point segments. The USB full-speed signaling bit rate is 12 Mbps. Also, a limited

capability low-speed signaling mode is defined at 1.5 Mbps. Refer to revisions 1.1 and 2.0 of the USB

Specification for fu rther deta ils. They c an be downloaded from http:/ /www. usb.org.

The MPC885 USB controller consists of a transmitter module, receiver module, and two protocol state

machines. The protocol state machines control the receiver and transmitter modules. One state machine

implements the func tion state diagram, and the other implements the host state diag ram. The USB controller

can implement a USB function endpoint, a USB host, or both for testing purposes (loopback diagnostics).

9 Communications Processor Module (CPM)

The MPC885 family is the next generation MPC8xx family of devices. Like its predecessor it implements

a dual-processor architecture, which provides both a high-performance, general-purpose processor for

applica tion programming us e and a special-p urpose communication proce ssor (CPM) uniquely designed for

communications applications.

The CPM contai ns feature s that, like its pre decessor, allow the MPC885 family to exc el in communicat ions

and networking products. These features are grouped as follows:

• Communications processor (CP)

• Independent DMA (SDMA) controllers

• Four general-purpose timers

The CP provides the communication features of the MPC885 family. Included are a RISC processor, three

serial communication controllers (SCCs), two serial management controllers (SMCs), a serial peripheral

interface (SPI), an I2C interface, 8 Kbytes of dual-port RAM, an interrupt controller, a time-slot assigner

(TSA), five parallel ports, a parallel interface port, four independent baud rate generators, and serial DMA

channels to support the SCCs, SMCs, SPI, and I2C.

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MOTOROLA MPC885/MPC880 PowerQUICC™ Family Technical Summary 11

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ATM Capabilities

The SDMAs provide two channels of general-purpose DMA capability for each communications channel.

They offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and

acknowledge logic.

The four ge neral-p urpose ti mers on the CPM are identic al to the t imers foun d on all of the MPC8xx devices

and support the internal cascading of two timers to form a 32-bit timer.

10 ATM Capabilities

The MPC885 family can be used as an adaptable ATM controller suited for a variety of applications,

including the following:

• DSLAM line cards

• Access concentrators

• LAN/WAN switches

• Hubs/gateways

• PBX systems

• Wireless base stations

11 Revision History

Table 2 provides a revision history for this document.

Table 2. Revision History

Revision

Number Date Change

0 01/2003 Initial doc um ent .

0.1 02/2003 Added 5-V capability.

Took out PIP interface.

0.2 03/2003 Modified the first three bullets under the Features list and removed the questions with

question marks.

0.3 03/2003 Removed question about interrupts, added preliminary, and modified the section on ATM

under the Features list.

0.4 05/2003 Put in new Features list.

0.5 8/2003 Added refe rence to USB 2.0 to the Features l ist and re moved 1. 1 from USB Figures 1 an d

2. Added USB 2.0 to Section 8, “Universal Serial Bu s (USB)”.

0.6 8/2003 Changed USB description to full-/low-speed compatible.

1.0 9/2003 Added DSP information to the Features list.

Released to the external web.

2.0 12/2003 Changed the Maximum operating frequency to 133 MHz.

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MPC885TS

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Motorola reserves the right to make changes without further notice to any products herein.

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Motorola data sheets and/or specification s can and do vary in different applicati ons and actual

performance may vary over time. All operating parameters, including “Typicals” must be validated

for each customer application by customer’s technical experts. Motorola does not convey any

license under its patent rights nor the rights of others. Motorola products are not designed,

intended, or authorized for use as components in systems intended for surgical implant into the

body , or other applications intended to support or sustain life, or for any other application in which

the failure of the Motorola product could create a situation where personal injury or death may

occu r. Shou l d Bu ye r pu r ch a se or us e Mot o rol a pr od ucts for any s uc h un int e nd ed or un a ut h or iz ed

application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,

affiliates, and distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was

negligent regarding the design or manufacture of the part.

Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office.

digital dna is a trademark of Motorola, Inc. The described product contains a PowerPC processor

core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product

or service names are the property of their respective owners. Motorola, Inc. is an Equal

Opportunity/Affirmative Action Employer.

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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