CL8452A Laser-Configured ASIC Family Key Features u Laser-Configured ASIC (LASIC(R)) technology offers the ultimate combination of performance, flexibility, and low cost u Functionally, architecturally, and electrically compatible with industry-standard FLEX(R) 8000 series FPGAs u High Density - 4,000 Usable gates - 452 Flip-flops - 120 Maximum user I/O pins u Laser fuse technology provides very fast, dense interconnect routing u Optional Instant-On configuration eliminates the need for an external configuration EPROM u Fabricated using 0.5 micron CMOS process u Very low current consumption (active and standby) u Alpha particle immune CL8000 Product Family Overview Parameter CL8282A CL8452A CL8636A CL8820A CL81188A Available Gates 5,000 8,000 12,000 16,000 24,000 Useable Gates 2,500 4,000 6,000 8,000 12,000 Flip-flops 282 452 636 820 1,188 Logic Elements 208 336 504 672 1,008 78 120 136 152 184 84 pin PLCC 100 pin TQFP 84 pin PLCC 100 pin TQFP 160 pin PQFP 84 pin PLCC 160 pin PQFP 208 pin PQFP 144 pin TQFP 160 pin PQFP 208 pin PQFP 208 pin PQFP 240 pin PQFP Max user I/O pins Packages 8K tbl 01 December 2000 Page 1 CL8452A Laser-Configured ASIC Description The Clear Logic CL8000 Laser-Configured ASIC (LASIC(R)) family offers the ultimate combination of performance, flexibility, and cost. This family is a system level second source to Altera FLEX(R) 8000 products. For designs not requiring in-system reprogrammability, design verification can be performed using the programmable Altera devices, and Clear Logic LASICs can be used for low cost, high volume production. Clear Logics innovative laser ASIC technology eliminates NRE costs, test vector development, ordering minimums and long lead times. No re-simulation or re-layout is required, as the device is engineered using a cell-based, PLD-like architecture. Clear Logics TestCell technology ensures complete test coverage through the use of specialized testing modes which are transparent to the user. The Clear Logic CL8000 Laser-Configured ASIC family is based upon a large array of logic elements. Each logic element contains a configurable look up table for combinatorial functions and a register for sequential operations. A group of eight logic elements forms a block. Laser-configured metal fuses implement logical functions and control signal routing Laser configuration provides reduced cost and enhanced performance. These inherent performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events. Configuration Clear Logics CL8000 LASIC(R) family is compatible with all six configuration modes defined for the FLEX(R) 8000 product family. These configuration modes include the following: u Active Serial u Active Parallel Up u Active Parallel Down u Passive Parallel Synchronous u Passive Parallel Asynchronous u Passive Serial Page 2 CL8452A Laser-Configured ASIC The CL8000 is already configured when it is shipped, and can be configured to bypass the FLEX(R) 8000 configuration modes. This Instant-On configuration mode eliminates the need for external EPROMs or microcode. In the Instant-On mode, the CL8000 device begins Initialization immediately upon a low-tohigh transition on the nCONFIG pin. Additional Information For further information on designing with the CL8000 LASIC family, please refer to the following documents: u AN-01: Requesting a First Article. This document provides instructions on how to submit a bitstream file for generation of first articles. u AN-02: Clear Logic Packaging Guide. This document provides specifications and drawings for packages used by the CL10K family and other Clear Logic devices. u AN-03: CL8000 and System Configuration. This document contains a detailed discussion of all aspects of configuring CL8000-based systems. u AN-04: CL8000 Technology White Paper. This document outlines the technologies employed by the CL8000 LASIC family. u AN-05: Calculating CL8000 Power Consumption. This document provides guidelines for calculating power consumption based on CL8000 design characteristics. u AN-06: Eliminating the Serial EPROM from FLEX 8000 Designs. This document outlines how additional savings can be achieve by removing the EPROM from the CL8000 LASIC family. u AN-07: CL8000 Test Methodology. This document describes how Clear Logic provides 100% stuck-at fault coverage. u AN-08: CL8000 LASIC Timing and Function Compatibility. This document shows how a seamless conversion from FPGA to ASIC can be achieve with no additional engineering can be achieved with Clear Logic. Page 3 CL8452A Laser-Configured ASIC Block Diagram DI IOE IOE IOE IOE LBB LBB LBB IOE LBB Array Size: 42 LBBs (2 Rows by 21 Columns) LBB User-Defined Input/Outputs LBB IOE IOE Configuration and Emulation Logic IOE IOE Page 4 IOE nSP MSEL0 MSEL1 nCONFIG nWS nRS nCS CS CLKUSR nSTATUS DCLK CONF_DONE DATA7 DATA[0:6] RDCLK RDYnBUSY ADD[0:17] TDI TDO TCK TMS nTRST User-Defined Input/Outputs LBB: Logic Building Block IOE: Input/Output Element DI: Dedicated Input 8452A drw 01 CL8452A Laser-Configured ASIC Pin Configuration Pin Name 84 pin PLCC 100 pin TQFP 160 pin PQFP nSP 75 76 120 MSEL0 74 75 117 MSEL1 53 51 84 nSTATUS 32 25 37 nCONFIG 33 26 40 DCLK 10 100 1 CONF_DONE 11 1 4 nWS 30 23 30 nRS 48 45 71 RDCLK 49 46 73 nCS 29 22 29 CS 28 21 27 RDYnBUSY 77 78 125 CLKUSR 50 47 76 ADD17 51 48 78 ADD16 55 54 91 ADD15 56 55 92 ADD14 57 57 94 ADD13 58 58 95 ADD12 60 60 96 ADD11 61 61 97 ADD10 62 62 98 ADD9 63 64 99 ADD8 64 65 101 ADD7 65 66 102 ADD6 66 67 103 8452A tbk 01A Page 5 CL8452A Laser-Configured ASIC Pin Configuration Pin Name 84 pin PLCC 100 pin TQFP 160 pin PQFP ADD5 67 68 104 ADD4 69 70 105 ADD3 70 71 106 ADD2 71 72 109 ADD1 72 73 110 ADD0 76 77 123 DATA7 2 89 144 DATA6 4 91 150 DATA5 6 95 152 DATA4 7 96 154 DATA3 8 97 157 DATA2 9 98 159 DATA1 13 4 11 DATA0 14 5 12 TDI 45 - - TDO 27 - - TCLK 44 - - TMS 43 - - nTRST 52 - - Dedicated Inputs 12, 31, 54, 73 3, 24, 53, 74 5, 36, 85, 116 VCCINT 17, 38, 59, 80 9, 32, 49, 59, 82 21, 41, 53, 67, 80, 81, 100, 121, 133, 147, 160 5, 26, 47, 68 19, 44, 69, 94 13, 14, 28, 46, 60, 75, 93, 107, 108, 126, 140, 155 GND NC (No Connect) - Total user I/O pins 64 2, 6, 13, 30, 37, 42, 43, 50, 2, 3, 38, 39, 70, 82, 83, 118, 52, 56, 63, 80, 87, 92, 93, 99 119, 148 64 116 8452A tbk 01B Page 6 CL8452A Laser-Configured ASIC DC Electrical Specifications Absolute Maximum Ratings Symbol Min Max Unit Supply voltage -2.0 7.0 V DC input voltage [1] -2.0 7.0 V IOUT DC output current, per pin -25 25 mA TSTG Storage temperature No bias -65 150 C TAMB Ambient temperature Under bias -65 135 C TJ Junction temperature Under bias 135 C VCC VI Parameter Conditions 8K tbl 02 Recommended Operating Conditions Symbol Parameter VCCINT VCCIO [2] Conditions Min Max Unit Supply voltage, internal logic and input buffers Commercial Grade Devices Industrial Grade Devices 4.75 4.50 5.25 5.50 V V DC input voltage 5.0 volt commercial 5.0 volt industrial 3.3 volt operation 4.75 4.50 3.00 5.25 5.50 3.60 V V V VI Input voltage 0 VCCINT V VO Output voltage 0 VCCIO V TA Operating temperature Commercial temperature range Industrial temperature range 0 -40 70 85 C C tR Input signal rise time 40 ns tF Input signal fall time 40 ns VCC rise time 100 ms tRVCC 8K tbl 03 Page 7 CL8452A Laser-Configured ASIC DC Electrical Specifications cont. DC Electrical Characteristics (over the operating range) Symbol Parameter Conditions Min Typ[3] Max Unit VIH Input HIGH Voltage 2.0 VCCINT + 0.3 V VIL Input LOW Voltage -0.3 0.8 V VOH Output HIGH Voltage IOH = -4.0 mA, VCCIO = VCCIO[Min] VOL Output LOW Voltage IOL = 12.0 mA, VCCIO = VCCIO[Min] IIN Input Leakage Current VI = VCC or GND IOZ Output Leakage Current VO = VCC or GND ICC0 Standby Current VI = GND, no load 2.4 V 0.45 V -10 10 A -40 40 A 10 mA 0.5 8K tbl 04 Capacitance Symbol Parameter Conditions C IN Input Capacitance COUT Output Capacitance Min Max Unit VIN = 0 V, f = 1.0 MHz 10 pF VOUT = 0 V, f = 1.0 MHz 10 pF 8K tbl 05 Page 8 CL8452A Laser-Configured ASIC AC Electrical Specifications I/O Element Timing Parameters Symbol Parameter [5] Conditions Speed: -2 Min Max Speed: -3 Min Max Speed: -4 Min Max Unit tIOD IOE register data delay 0.7 0.8 0.9 ns tIOC IOE register control signal delay 1.7 1.8 1.9 ns tIOE Output enable delay 1.7 1.8 1.9 ns IOE register clock to output delay 1.0 1.0 1.0 ns 0.3 0.2 0.1 ns tIOCO tIOCOMB IOE combinatorial delay tIOSU IOE register setup time before clock 1.4 1.6 1.8 ns tIOH IOE register hold time after clock 0.0 0.0 0.0 ns tIOCLR tIN IOE register clear delay 1.2 1.2 1.2 ns Input pad and buffer delay 1.5 1.6 1.7 ns [6] Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 1.1 1.4 1.7 ns Output buffer and pad delay [6] Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 0.0 1.9 2.2 ns tOD3 Output buffer and pad delay[6] Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 4.6 4.9 5.2 ns tZX Output buffer disable delay[6] C L = 5 pF 1.4 1.6 1.8 ns tZX1 Output buffer and pad delay [6] Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 1.4 1.6 1.8 ns tZX2 Output buffer and pad delay[6] Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 0.0 2.1 2.3 ns tZX3 Output buffer and pad delay[6] Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 4.9 5.1 5.3 ns tOD1 Output buffer and pad delay tOD2 8K tbl 06B External Timing Parameters[4] Symbol Parameter tDRR Register to register delay via four LEs, three row interconnects, and four local interconnects tODH Output data hold time after clock Conditions Speed: -2 Min Max Speed: -3 Min 16 1.0 Max Speed -4 Min 20 1.0 Max Unit 25 1.0 ns ns 8K tbl 07B Page 9 CL8452A Laser-Configured ASIC AC Electrical Specifications cont. Logic Element Timing Parameters[5] Symbol Parameter Conditions Speed: -2 Min Max Speed: -3 Min Max Speed: -4 Min Max Unit tLUT Look up table delay for data-in 2.0 2.3 3.0 ns tCLUT Look up table delay for carry-in 0.0 0.2 0.1 ns tRLUT Look up table delay for LE register feedback 0.9 1.6 1.6 ns tGATE Cascade gate delay 0.0 0.0 0.0 ns tCASC Cascade chain routing delay 0.6 0.7 0.9 ns tCICO Carry-in to carry-out delay 0.4 0.5 0.6 ns tCGEN Data-in to carry-out delay 0.4 0.9 0.8 ns tCGENR LE register feedback to carry-out delay 0.9 1.4 1.5 ns tC LE register control signal delay 1.6 1.8 2.4 ns tCH Clock high time 1.7 1.7 2.7 ns tCL Clock low time 1.7 1.7 2.7 ns tCO LE register clock-to-output delay 0.4 0.5 0.6 ns Combinatorial delay 0.4 0.5 0.6 ns tCOMB tSU LE register setup time before clock 0.8 1.0 1.1 ns tH LE register hold time after clock 0.9 1.1 1.4 ns tPRE LE register preset delay 0.6 0.7 0.8 ns tCLR LE register clear delay 0.6 0.7 0.8 ns 8K tbl 08B Interconnect Timing Parameters[5] Symbol Parameter Conditions Speed: -2 Min Max Speed: -3 Min Max Speed: -4 Min Max Unit tLABCASC Cascade delay between LEs in different LABs 0.3 0.4 0.4 ns tLABCARRY Carry delay between LEs in different LABs 0.3 0.4 0.4 ns tLOCAL LAB local interconnect delay 0.5 0.5 0.7 ns tROW Row interconnect routing delay 5.0 5.0 5.0 ns tCOL Column interconnect routing delay 3.0 3.0 3.0 ns tDIN_C Dedicated input to LE control delay 5.0 5.0 5.5 ns tDIN_D Dedicated input to LE data delay 7.0 7.0 7.5 ns tDIN_IO Dedicated input to IOE control delay 5.0 5.0 5.5 ns 8K tbl 09B Page 10 CL8452A Laser-Configured ASIC AC Test Conditions (A) (B) 464 VCCIO OUTPUT Includes jig capacitance All Input Pulses 464 VCCIO 3.0V 90% 90% OUTPUT 250 35 pF Includes jig capacitance 250 5 pF GND 10% 10% 3ns 3ns 8K drw 01 A: Test fixture set-up A is for general testing. B: Test fixture set-up B is for high Z testing (tZX#). Notes to Tables 1. During transitions, inputs may undershoot to -2.0V for periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.3V. 2. The following devices do not have VCCIO pins: CL8282A, CL8452A. For these devices, all references to VCCIO should be changed to VCCINT 3. Typical values are at VCC of 5.0 volts and ambient temperature of 25 C. 4. Guaranteed but not tested. Characterized initially, and after any design changes which may affect these parameters. 5. Internal timing delays are based on characterization, and cannot be explicitly tested. Internal timing parameters should be used for performance estimation only. 6. Use AC Test Conditions set-up B for these parameters. Revision History 16 Jan. 1998: Created new document 31 Jul. 1999: Recompiled databook, 8820 package update. 29 Nov. 1999: Remove reference to the 8282AV device which is not supported. 01 Dec. 2000: Review and reprint. Ordering Information Part Number CL8452ALC84-4 Temperature Range Commercial Package Type 84-pin PLCC CL8452ALC84-3 100-pin Thin QFP CL8452ATC100-3 -4 (slowest) EPF8452ALC84-4 -4 (slowest) EPF8452ATC100-4 -3 (fastest) EPF8452ATC100-3 CL8452AQC160-4 160-pin Plastic QFP CL8452AQC160-3 -4 (slowest) EPF8452AQC160-4 -3 CL8452AQC160-2 CL8452AQI160-3 Altera Equivalent -3 (fastest) EPF8452ALC84-3 CL8452ATC100-4 CL8452ALI84-4 Speed EPF8452AQC160-3 -2 (fastest) EPF8452AQC160-2 Industrial 84-pin PLCC -4 EPF8452ALI84-4 160-pin PQFP -3 EPF8452AQI160-3 8452A tbl 02 Page 11 CL8452A Laser-Configured ASIC Page 12