Parameter CL8282A CL8452A CL8636A CL8820A CL81188A
Available Gates 5,000 8,000 12,000 16,000 24,000
Useable Gates 2,500 4,000 6,000 8,000 12,000
Flip-flops 282 452 636 820 1,188
Logic Elements 208 336 504 672 1,008
Max user I/O pins 78 120 136 152 184
Packages
84 pin PLCC
100 pin TQFP
84 pin PLCC
100 pin TQFP
160 pin PQFP
84 pin PLCC
160 pin PQFP
208 pin PQFP
144 pin TQFP
160 pin PQFP
208 pin PQFP
208 pin PQFP
240 pin PQFP
8K tbl 01
December 2000 Page 1
uLaser-Configured ASIC (LASIC®) technology offers the
ultimate combination of performance, flexibility, and low
cost
uFunctionally, architecturally, and electrically compatible
with industry-standard FLEX®8000 series FPGAs
uHigh Density
- 4,000 Usable gates
- 452 Flip-flops
- 120 Maximum user I/O pins
uLaser fuse technology provides very fast, dense
interconnect routing
uOptional Instant-On configuration eliminates the need
for an external configuration EPROM
uFabricated using 0.5 micron CMOS process
uVery low current consumption (active and standby)
uAlpha particle immune
CL8000 Product Family Overview
CL8452A
Laser-Configured ASIC Family
Key Features
The Clear Logic CL8000 Laser-Configured ASIC (LASIC®) family
offers the ultimate combination of performance, flexibility, and
cost. This family is a system level second source to Altera
FLEX®8000 products. For designs not requiring in-system
reprogrammability, design verification can be performed using
the programmable Altera devices, and Clear Logic LASICs can be
used for low cost, high volume production.
Clear Logics innovative laser ASIC technology eliminates NRE
costs, test vector development, ordering minimums and long lead
times. No re-simulation or re-layout is required, as the device is
engineered using a cell-based, PLD-like architecture. Clear
Logics TestCell technology ensures complete test coverage
through the use of specialized testing modes which are
transparent to the user.
The Clear Logic CL8000 Laser-Configured ASIC family is based
upon a large array of logic elements. Each logic element contains
a configurable look up table for combinatorial functions and a
register for sequential operations. A group of eight logic
elements forms a block. Laser-configured metal fuses implement
logical functions and control signal routing
Laser configuration provides reduced cost and enhanced
performance. These inherent performance benefits include
extremely consistent propagation delays, reduced power
consumption, and improved immunity to noise and upset events.
Clear Logics CL8000 LASIC®family is compatible with all six
configuration modes defined for the FLEX®8000 product family.
These configuration modes include the following:
uActive Serial
uActive Parallel Up
uActive Parallel Down
uPassive Parallel Synchronous
uPassive Parallel Asynchronous
uPassive Serial
Description
CL8452A Laser-Configured ASIC
Page 2
Configuration
The CL8000 is already configured when it is shipped, and can be
configured to bypass the FLEX®8000 configuration modes.
This Instant-On configuration mode eliminates the need for
external EPROMs or microcode. In the Instant-On mode, the
CL8000 device begins Initialization immediately upon a low-to-
high transition on the nCONFIG pin.
For further information on designing with the CL8000 LASIC
family, please refer to the following documents:
uAN-01: Requesting a First Article. This document provides
instructions on how to submit a bitstream file for generation
of first articles.
uAN-02: Clear Logic Packaging Guide. This document provides
specifications and drawings for packages used by the CL10K
family and other Clear Logic devices.
uAN-03: CL8000 and System Configuration. This document
contains a detailed discussion of all aspects of configuring
CL8000-based systems.
uAN-04: CL8000 Technology White Paper. This document
outlines the technologies employed by the CL8000 LASIC
family.
uAN-05: Calculating CL8000 Power Consumption. This
document provides guidelines for calculating power
consumption based on CL8000 design characteristics.
uAN-06: Eliminating the Serial EPROM from FLEX 8000
Designs. This document outlines how additional savings can
be achieve by removing the EPROM from the CL8000 LASIC
family.
uAN-07: CL8000 Test Methodology. This document describes
how Clear Logic provides 100% stuck-at fault coverage.
uAN-08: CL8000 LASIC Timing and Function Compatibility.
This document shows how a seamless conversion from FPGA
to ASIC can be achieve with no additional engineering can be
achieved with Clear Logic.
Additional
Information
CL8452A Laser-Configured ASIC
Page 3
CL8452A Laser-Configured ASIC
Page 4
LBB LBB LBB
LBB LBB LBB
Configuration
and
Emulation
Logic
nSP
MSEL0
MSEL1
nCONFIG
nWS
nRS
nCS
CS
CLKUSR
nSTATUS
DCLK
CONF_DONE
DATA7
DATA[0:6]
RDCLK
RDYnBUSY
ADD[0:17]
TDI
TDO
TCK
TMS
nTRST
U s e r - D e f i n e d I n p u t / O u t p u t s
IOE
IOE
IOE
LBB: Logic Building Block
IOE: Input/Output Element
DI: Dedicated Input
IOE
IOE
U s e r - D e f i n e d
I n p u t / O u t p u t s
Array Size: 42 LBBs
(2 Rows by 21 Columns)
IOE
IOE
IOE
IOE
IOE
DI
8452A drw 01
Block Diagram
CL8452A Laser-Configured ASIC
Page 5
Pin Configuration
Pin Name 84 pin PLCC 100 pin TQFP 160 pin PQFP
nSP 75 76 120
MSEL0 74 75 117
MSEL1 53 51 84
nSTATUS 32 25 37
nCONFIG 33 26 40
DCLK 10 100 1
CONF_DONE 11 1 4
nWS 30 23 30
nRS 48 45 71
RDCLK 49 46 73
nCS 29 22 29
CS 28 21 27
RDYnBUSY 77 78 125
CLKUSR 50 47 76
ADD17 51 48 78
ADD16 55 54 91
ADD15 56 55 92
ADD14 57 57 94
ADD13 58 58 95
ADD12 60 60 96
ADD11 61 61 97
ADD10 62 62 98
ADD9 63 64 99
ADD8 64 65 101
ADD7 65 66 102
ADD6 66 67 103
8452A tbk 01A
CL8452A Laser-Configured ASIC
Page 6
Pin Configuration
Pin Name 84 pin PLCC 100 pin TQFP 160 pin PQFP
ADD5 67 68 104
ADD4 69 70 105
ADD3 70 71 106
ADD2 71 72 109
ADD1 72 73 110
ADD0 76 77 123
DATA7 2 89 144
DATA6 4 91 150
DATA5 6 95 152
DATA4 7 96 154
DATA3 8 97 157
DATA2 9 98 159
DATA1 13 4 11
DATA0 14 5 12
TDI 45 - -
TDO 27 - -
TCLK 44 - -
TMS 43 - -
nTRST 52 - -
Dedicated Inputs 12, 31, 54, 73
3, 24, 53, 74 5, 36, 85, 116
VCCINT 17, 38, 59, 80
9, 32, 49, 59, 82
21, 41, 53, 67, 80, 81, 100,
121, 133, 147, 160
GND 5, 26, 47, 68
19, 44, 69, 94
13, 14, 28, 46, 60, 75, 93,
107, 108, 126, 140, 155
NC (No Connect) -
2, 6, 13, 30, 37, 42, 43, 50,
52, 56, 63, 80, 87, 92, 93, 99
2, 3, 38, 39, 70, 82, 83, 118,
119, 148
Total user I/O pins 64 64 116
8452A tbk 01B
CL8452A Laser-Configured ASIC
Page 7
Absolute Maximum Ratings
Recommended Operating Conditions [2]
DC Electrical Specifications
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage, internal logic and input buffers
Commercial Grade Devices 4.75 5.25 V
Industrial Grade Devices 4.50 5.50 V
VCCIO DC input voltage
5.0 volt commercial 4.75 5.25 V
5.0 volt industrial 4.50 5.50 V
3.3 volt operation 3.00 3.60 V
VIInput voltage 0 VCCINT V
VOOutput voltage 0 VCCIO V
TAOperating temperature
Commercial temperature range 0 70 °C
Industrial temperature range -40 85 °C
tRInput signal rise time 40 ns
tFInput signal fall time 40 ns
tRVCC VCC rise time 100 ms
8K tbl 03
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage -2.0 7.0 V
VIDC input voltage[1] -2.0 7.0 V
IOUT DC output current, per pin -25 25 mA
TSTG Storage temperature No bias -65 150 °C
TAMB Ambient temperature Under bias -65 135 °C
TJJunction temperature Under bias 135 °C
8K tbl 02
CL8452A Laser-Configured ASIC
Page 8
Capacitance
DC Electrical Specifications cont.
Symbol Parameter Conditions Min Max Unit
CIN Input Capacitance VIN = 0 V, f = 1.0 MHz 10 pF
COUT Output Capacitance VOUT = 0 V, f = 1.0 MHz 10 pF
8K tbl 05
DC Electrical Characteristics (over the operating range)
Symbol Parameter Conditions Min
Typ[3] Max Unit
VIH Input HIGH Voltage 2.0 VCCINT + 0.3 V
VIL Input LOW Voltage -0.3 0.8 V
VOH Output HIGH Voltage IOH = -4.0 mA, VCCIO = VCCIO[Min] 2.4 V
VOL Output LOW Voltage IOL = 12.0 mA, VCCIO = VCCIO[Min] 0.45 V
IIN Input Leakage Current VI = VCC or GND -10 10 µA
IOZ Output Leakage Current VO = VCC or GND -40 40 µA
ICC0 Standby Current VI = GND, no load 0.5 10 mA
CL8452A Laser-Configured ASIC
Page 9
AC Electrical Specifications
Symbol Parameter Conditions Min Max Min Max Min Max Unit
tIOD IOE register data delay 0.7 0.8 0.9 ns
tIOC IOE register control signal delay 1.7 1.8 1.9 ns
tIOE Output enable delay 1.7 1.8 1.9 ns
tIOCO IOE register clock to output delay 1.0 1.0 1.0 ns
tIOCOMB IOE combinatorial delay 0.3 0.2 0.1 ns
tIOSU IOE register setup time before clock 1.4 1.6 1.8 ns
tIOH IOE register hold time after clock 0.0 0.0 0.0 ns
tIOCLR IOE register clear delay 1.2 1.2 1.2 ns
tIN Input pad and buffer delay 1.5 1.6 1.7 ns
tZX Output buffer disable delay[6] CL = 5 pF 1.4 1.6 1.8 ns
2.3
ns
2.2
ns
tZX2
Output buffer and pad delay[6]
Slow Slew Rate = off,
VCCIO = 5.0v, CL = 35 pF
0.0
2.1
0.0
1.9
tOD2
Output buffer and pad delay[6]
Slow Slew Rate = off,
VCCIO = 5.0v, CL = 35 pF
5.3
ns
8K tbl 06B
1.8
ns
tZX3
Output buffer and pad delay[6]
Slow Slew Rate = off,
VCCIO = 5.0v, CL = 35 pF
4.9
5.1
5.2
ns
tZX1
Output buffer and pad delay[6]
Slow Slew Rate = off,
VCCIO = 5.0v, CL = 35 pF
1.4
1.6
1.7
ns
tOD3
Output buffer and pad delay[6]
Slow Slew Rate = off,
VCCIO = 5.0v, CL = 35 pF
4.6
4.9
Speed: -2
Speed: -3
Speed: -4
tOD1
Output buffer and pad delay[6]
Slow Slew Rate = off,
VCCIO = 5.0v, CL = 35 pF
1.1
1.4
I/O Element Timing Parameters [5]
Symbol Parameter Conditions Min Max Min Max Min Max Unit
tDRR
Register to register delay via four LEs,
three row interconnects, and
four local interconnects
16 20 25 ns
tODH Output data hold time after clock 1.0 1.0 1.0 ns
Speed: -2
Speed: -3
Speed -4
8K tbl 07B
External Timing Parameters[4]
CL8452A Laser-Configured ASIC
Page 10
Symbol Parameter Conditions Min Max Min Max Min Max Unit
tLABCASC Cascade delay between LEs in different LABs 0.3 0.4 0.4 ns
tLABCARRY Carry delay between LEs in different LABs 0.3 0.4 0.4 ns
tLOCAL LAB local interconnect delay 0.5 0.5 0.7 ns
tROW Row interconnect routing delay 5.0 5.0 5.0 ns
tCOL Column interconnect routing delay 3.0 3.0 3.0 ns
tDIN_C Dedicated input to LE control delay 5.0 5.0 5.5 ns
tDIN_D Dedicated input to LE data delay 7.0 7.0 7.5 ns
tDIN_IO Dedicated input to IOE control delay 5.0 5.0 5.5 ns
Speed: -2
Speed: -3
Speed: -4
8K tbl 09B
Symbol Parameter Conditions Min Max Min Max Min Max Unit
tLUT Look up table delay for data-in 2.0 2.3 3.0 ns
tCLUT Look up table delay for carry-in 0.0 0.2 0.1 ns
tRLUT Look up table delay for LE register feedback 0.9 1.6 1.6 ns
tGATE Cascade gate delay 0.0 0.0 0.0 ns
tCASC Cascade chain routing delay 0.6 0.7 0.9 ns
tCICO Carry-in to carry-out delay 0.4 0.5 0.6 ns
tCGEN Data-in to carry-out delay 0.4 0.9 0.8 ns
tCGENR LE register feedback to carry-out delay 0.9 1.4 1.5 ns
tCLE register control signal delay 1.6 1.8 2.4 ns
tCH Clock high time 1.7 1.7 2.7 ns
tCL Clock low time 1.7 1.7 2.7 ns
tCO LE register clock-to-output delay 0.4 0.5 0.6 ns
tCOMB Combinatorial delay 0.4 0.5 0.6 ns
tSU LE register setup time before clock 0.8 1.0 1.1 ns
tHLE register hold time after clock 0.9 1.1 1.4 ns
tPRE LE register preset delay 0.6 0.7 0.8 ns
tCLR LE register clear delay 0.6 0.7 0.8 ns
Speed: -2
Speed: -3
Speed: -4
8K tbl 08B
AC Electrical Specifications cont.
Logic Element Timing Parameters[5]
Interconnect Timing Parameters[5]
CL8452A Laser-Configured ASIC
Page 11
Ordering Information
16 Jan. 1998: Created new document
31 Jul. 1999: Recompiled databook, 8820 package update.
29 Nov. 1999: Remove reference to the 8282AV device which is not supported.
01 Dec. 2000: Review and reprint.
AC Test Conditions
464 Ω
250 Ω35 pF
VCCIO
OUTPUT
Includes jig
capacitance
464 Ω
250 Ω5 pF
VCCIO
OUTPUT
Includes jig
capacitance
(A) (B)
≤ 3ns
≤ 3ns
3.0V 90%
10%
GND
90%
10%
All Input Pulses
8K drw 01
Notes to Tables
Revision History
Part Number Temperature Range Package Type Speed Altera Equivalent
CL8452ALC84-4 Commercial 84-pin PLCC -4 (slowest) EPF8452ALC84-4
CL8452ALC84-3 -3 (fastest) EPF8452ALC84-3
CL8452ATC100-4 100-pin Thin QFP -4 (slowest) EPF8452ATC100-4
CL8452ATC100-3 -3 (fastest) EPF8452ATC100-3
CL8452AQC160-4 160-pin Plastic QFP -4 (slowest) EPF8452AQC160-4
CL8452AQC160-3 -3 EPF8452AQC160-3
CL8452AQC160-2 -2 (fastest) EPF8452AQC160-2
CL8452ALI84-4 Industrial 84-pin PLCC -4 EPF8452ALI84-4
CL8452AQI160-3 160-pin PQFP -3 EPF8452AQI160-3
8452A tbl 02
1. During transitions, inputs may undershoot to -2.0V for periods shorter than
20ns. Otherwise, minimum DC input voltage is -0.3V.
2. The following devices do not have VCCIO pins: CL8282A, CL8452A. For these
devices, all references to VCCIO should be changed to VCCINT
3. Typical values are at VCC of 5.0 volts and ambient temperature of 25 ºC.
4. Guaranteed but not tested. Characterized initially, and after any design changes
which may affect these parameters.
5. Internal timing delays are based on characterization, and cannot be explicitly
tested. Internal timing parameters should be used for performance estimation
only.
6. Use AC Test Conditions set-up B for these parameters.
A: Test fixture set-up A is for general testing.
B: Test fixture set-up B is for high Z testing (tZX#).
CL8452A Laser-Configured ASIC
Page 12