LF155/155A/LF255/LF355/355A/355B/LF 156/ 156A/LF256/LF356/LF356A/356B/LF 157/157A/LF257/LF357/357A/357B National Semiconductor LF155/LF156/LF157 Series Monolithic JFET Input Operational Amplifiers LF155/LF155A/LF255/LF355/LF355A/ LF355B Low Supply Current LF 156/LF 156A/LF256/LF356/LF356A/ LF356B Wide Band LF157/LF157A/LF257/LF357/LF357A/ LF357B Wide Band Decompensated (Ayjjn = 5) General Description These are the first monolithic JFET input operational ampli- fiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET Tech- nalogy}. These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which dogs not degrade drift or common- w Photocell amplifiers mw Sample and Hold circuits Common Features (LF155A, LF156A, LF157A) mode rejection. The devices are also designed for high slew Low input bias current 30 pA rata, wide bandwidth, extremely fast sattling time, low volt- Low Input Offset Current 3 pA age and current noise and a low 1/f noise corner. High input impedance 101290 @ Low input offset voltage 1 mv Advantages Low input offset voltage temp. drift 3 VPC m Replace expensive hybrid and module FET op amps @ Low input noise current 0.01 pA/VHz m Rugged JFETs allow biow-out free handling compared High common-mode rejection ratio 100 dB with MOSFET input devices m@ Large dc voltage gain 106 dB m Excellent for low noise applications using either high or low source impedancevery low 1/f corner Uncommon Features @ Offset adjust does not degrade drift or common-mode LF157A rejection as in most monolithic amplifiers LFISSA LFIS6A (45) Units @ New output stage allows use of large capacitive loads = Extremely 4 15 15 us (10,000 pF) without stability problems fast settling m@ Internal compensation and large differential input volt- time to age capability 0.01% : . @ Fast slew Applications rate 12 50 V/s m@ Precision high speed integrators m Wide gain 25 5 20 MHz m@ Fast D/A and A/D converters bandwidth m@ High impedance buffers m Low input m Wideband, low noise, low drift amplifiers noise voltage 20 12 120 nV/JAz m@ Logarithmic amplifiers Simplified Schematic a, BALANCE q , | * (5 OCI) ol | 4 : 9 i) ee Tw rf en @ ) i * 4} *2 pF in F157 series. . Vee TL/H/5646-1 3-24Absolute Maximum Ratings if Milltary/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for availability and specifications. (Note &} Supply Voltage Differential Input Voltage Input Voltage Range (Note 2) Output Short Circuit Duration TIMAX H-Package N-Package J-Package M-Package LF155A/GA/7A +22V +40V +20V Continuous 150C Power Dissipation at Ta = 25C (Notes 1 and 9) H-Package (Still Air) H-Package (400 LF/Min Air Flaw) N-Package J-Package M-Package Thermal Resistance (Typical) @j, H-Package (Still Air) H-Package (400 LF/Min Air Flow) N-Package J-Package M-Package (Typical) 6 Jc H-Packaga Storage Temperature Range Soldering Information (Lead Temp.) Metai Can Package 560 mW 1200 mW 160C/W 65C/W 23aC/W 65C to + 150C LF155/6/7 +22V +40V +20V Continuous 150C 150C 560 mW 1200 mW 1260 mW 160C/W 65C/W 100C/W 23C/W 65C to + 160C LF3558/6B/7B LF255/6/7 Continuous +22V +40V +20V 115C 100C 115C 100C 400 mw 1000 mW 670 mW 900 mW 380 mW 160C/W 65C/W 130C/W 100C/W 195C/W 23C/W 66C to + 150C LF355/6/7 LF3S5A/6A/7A + 18V +30V +16V Continuous 118C 100C 118C 100C 400 mw 1000 mW 670 mW 900 mW 380 mW 160C/W BeC/w 130C/W 100C/W 195C/W 23C/W 85C to + 150C Soldering (10 sec.) 300C 300C 300C 300C Dual-In-Line Package Soldering (10 sec.) 260C 260C 260C Small Outline Package Vapor Phase (60 sec.) 218C 215C Infrared (15 sec.) 220C 220C See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices. ESD tolerance (100 pF discharged through 1.5 kn) 1200V 1200V 1200V 1200V DC Electrical Characteristics (note 3) T, = 1, = 25C Symbol Parameter Conditions LFISSA/GA/7A LFOS5A/6A/TA Units Min Typ Max Min Typ Max Vos Input Offset Voltage Rsg=500, Ta=25C 1 2 1 2 mV Over Temperature 25 23 mv AVos/AT Average TC of Input Rg=500 Offset Voltage 3 3 6 nV iC ATC/AVosg | ChangeinAverageTC | Rg=500N, (Note 4) 05 05 pV with Vos Adjust . per mV los Input Offset Current Tj= 25C, (Notes 3, 5) a 10 3 10 pA TjS THIGH 10 1 nA lB Input Bias Current Tj= 25C, (Notes 3, 5) 30 50 30 50 pA T)STHIGH 25 5 nA Fin Input Resistance T= 26C 1012 1012 2 AVOL Large Signal Voltage Vsg= 15V, Ta= 25C 50 200 50 200 VimvV Gain Vo= +10V, Ry = 2k Over Temperature 25 25 Vim Vo Output Voltage Swing Vs= 15V, Ry = 10k 12 +13 +12 +13 Vv Vsg= +15V, RL=2k +10 +12 +10 +12 Vv 3-25 GlSE/VZSE/ZSE41/2S7A V/VLS1-/ 2514 1/G9SE/V9SES 1/9SE4 1/9524 1/V9S1 /9Sb41/ASSE/VSSE/SSE4T1/SSZ41/VSS1/SSh 4LF155/155A/LF255/LF355/355A/355B/LF156/156A/LF256/LF356/LF356A/356B/LF157/157A/LF257/LF357/357A/357B DC Electrical Characteristics (Note 3) T, = 1; = 25C (Continued) Symbol Parameter Conditions LFISSA/GA/7A LFSSSA/6A/7A Units Min Typ Max Min Typ Max Vom Input Common-Mods _ +15.1 +15.1 v Voltage Range Vs= + 15V #1 12 #11 12 Vv CMRR common-Mode Rejection 85 400 85 100 dB atio PSRR supply Voltage Rejection (Note 8) 85 400 a5 4100 dB atio AC Electrical Characteristics 1, = 1, = 25C, vs= +15v Symbol Parameter Conditions LF155A/355A LF156A/356A LF157A/357A Units Min | Typ | Max | Min | Typ | Max | Min | Typ | Max SR Slew Rate LF1I55A/6A; Ay=1,] 3 5 10 12 Vins LF157A; Ay=5 40 | 50 Vips GBW Gain Bandwidth Product 2.5 4 4.5 15 20 MHz ts Settling Time to 0.01% | (Note 7) 4 1.5 145 BS en Equivalent Input Noise | Rg=100n Voltage f= 100 Hz 25 15 15 nv/JHz t= 1000 Hz 25 12 12 nVv/JHz in Equivalent input f=100 Hz 0.01 0.01 0.01 pA/ {Hz Noise Current f= 1000 Hz 0.04 0.01 0.01 pA/JHz Cin Input Capacitance 3 g 3 pF DC Electrical Characteristics (note 3) LF255/6/7 Symbol Parameter Conditions LFIS5/6/7 LF3558/6B/7B LF355/6/7 Units Min | Typ |Max| Min | Typ | Max} Min| Typ | Max Vos Input Offset Voltage | Rg=50N, Ta=25C 3 5 3 5 3 10 mV Over Temperature 7 6.5 13 mV AVos/AT | Average TC of input Rg=500 Offset Voltage s 5 5 HVE ATC/AVog | Change in Average TC | Rg = 502, (Note 4) 05 05 05 pVvieG with Vos Adjust . permV los Input Offset Current Tj = 28C, (Notes 3, 5) 3 20 3 20 3 50.) pA TjS THIGH 20 1 2 nA I3 Input Bias Current T= 25C, (Notes 3, 5) 30 {100 30 | 100 30 | 200| pA Tj<THiGH 50 5 8 nA Rin Input Resistance T,= 26C 1012 1012 1012 a AVOL Large Signal Voltage {Vs=+15V,Ta=25C| 50 | 200 50 | 200 25 | 200 V/mV Gain Vo= +10V, RL=2k Over Temperature 25 25 15 V/mV Vo Output Voltage Swing |Vg=+15V,R,=10k | +12) +13 +12) +13 +12) +413 Vv Vg= +15V, RL=2k +10; +12 10; +12 +10} +12 Vv Vom Input Common-Mode _ + 15.1 +15.1 + 15.1 Vv Voltage Range Vs= +15V +11 12 +11 12 +10 -12 V CMRR Common-Modce Rejec- tion Ratio 85 100 BS 100 80 100 dB PSRA Supply Voltage Rejec- | (Note 6) 85 4100 a5 100 80 100 dB tion Ratio 3-26DC Electrical Characteristics 1, = 1, = 25c, vs = +15v LF155A/155, LF156A/ 156, LF1S7A/157 LF255, LF355 , LF356A/356 LF357A/357 Parameter LF355A/355B LF256/3568 LF257/357B Units Typ Max | Typ | Max | Typ Max Typ Max Typ Max Typ Max Supply Current 2 4 2 4 7 5 10 5 7 5 10 mA AC Electrical Characteristics 1, = 1, = 25c, vs = +15v LF155/255/ | LF 156/256, | LF156/256/ | .F 157/257, | LF167/257/ Symbol Parameter Conditions 355/355B LF356B 356/356B LF357B 357/357B | Units Typ Min Typ Min Typ SR Slew Rate LF155/6: Ay=1, 5 75 12 Vips LF157: Ay=5 30 50 V/ us GBW Gain Bandwidth 2.5 5 20 MHz Product ts Settling Time to 0.01% | (Note 7) 4 1.5 1.5 ps en Equivalent Input Noise | Rg= 1000 Voltage f= 100 Hz 25 15 15 nv/VHz f= 1000 Hz 20 12 12 nv/VAz in Equivalent Input f= 100 Hz 0.01 0.01 0.01 pA/JHz Current Noise f= 1000 Hz 0.01 0.01 0.01 pA/VHz Cin Input Capacitance 3 3 3 pF Notes for Electrical Characteristics Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by Timax, 8a, and the ambient temperature, Ta. The maximum available power dissipation at any tamperature is Pyg= (Timax Ta)/@ja or the 25C Payax, whichever is lass, Note 2: Unless otherwise specified the absolute maximum nagative input voltage is equal to the negative power supply voltage. Note 3: Unless otherwise stated, these test conditions apply: LFASSA/6A/7A LF4#55//6/7 LF255//6/7 LF355A/6A/7A | LF355B/6B/7B LF355//6/7 Supply Voltage, Vg | +15V<Vg< +20V t1IBVSVg<s+t20V | +15V<Vg< +18V | +15V<Vg4t20V | Vg= +15V Ta 55C<Tas + 128C | 25C<Tax+85C | O'C<Tas+70C | OC<Tas+70C | O'C<Tas+70C THIGH +125C +85C +70C +70C +70C and Vos, |g and log are measured at Voy =0. Note 4: The Temperature Coefficient of the adjusted input offset voltage changes oniy a small amount (0.5.V/"C typically) for each mY of adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment. Note 5: The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, Tj. Due to limited Production test time, the input bias currents measured are correlated to junction temperature, in normal operation the junction tamperature rises above the ambient temperature as a result of internal power dissipation, Pd. Tj\=Ta+ ja Pd where 4a is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice. Note 7: Settling time is defined here, for a unity gain inverter connection using 2 kf resistors for the LF155/6. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter, For the LF 157, Ay= 5, the fesdback rasistor from output to input is 2 kO and the output step is 10V (See Sattting Time Test Circuit). Note 8: Rafer to RETS155AX for LFiS5A, RETS155x for LF155, RETSF156AX for LF1ISGA, RETS156X for LF158, RETS157A for LF157A and RETS187X% for LF157 military specifications. Note : Max. Power Dissipation is defined by the package characteristics. Operating tha part near the Max. Power Dissipation may cause the part to operate outside guaranteed fimits. 3-27 GLSE/VLSE/ZSE4 1/2924 1/VZSb /2S141/E9SE/V9SEI1/9SE4 1/9524 1/V9S1 /9SLI1/GSS6/VSSe/SSE41/SS74 1/VSSL/SSL 4LF155/155A/LF255/LF355/355A/355B/LF 156/ 156A/LF256/LF356/LF356A/356B/LF 157/157A/LF257/LF357/357A/357B Typical DC Performance Characteristics Curves are for LF155, LF156 and LF157 unless otherwise specified. Input Bias Current Input Bias Current 1k ok = & a ' 5 - L220 Ve. z * 20s =: * 18 Vs 2 = a] vg a 1 eye Z 2 | Vg 2 5 5 rT = , E LFIBG LFIbE/? a J a1 ! 5 -28 65 a 68 WH 125 65 -2 = 66 S 8 SH 125 CASE TEMPERATURE (C) CASE TEMPERATURE {*C) Voitage Swing Supply Current a a Ry = 2k = Tas 28C i i a fa = Te= -56C Ma E : S a Ton zee < 52 e & P a Tp = 128 = < I LF 155 1 ? 6 18 18 2 10 18 20 ab SUPPLY VOLTAGE (3] SUPPLY VOLTAGE i:) Negative Current Limit Positive Current Limit 15 = 7 ev = 4 z= z 5 E & uw = -te < g 3 J E E = z 8 t 5 0 18 0 68 H a 50h 2H RH BH OUTPUT SINK CURRENT (eA) QUTPUT SOURCE CURRENT (mA) Negative Common-Mode Input Voltage Limit Open Loop Voltage Gain -20 10M < ose as 5 Tae -$8C $e -18 fry -s5e = za Tye 2G o IM i a Ta = 125C 3 Se -10 5 ae ws Se 25 > z5 5 100k 3 z & 9g 0 10% 5 10 -15 ~20 5 10 15 20 NEGATIVE SUPPLY VOLTS (V) SUPPLY VOLTAGE (+ ) INPUT Z1AS CURRENT (pA) POSITIVE COMMON-MODE INPUT VOLTAGE LIMIT () SUPPLY CURRENT (mA) PEAK TO PEAK OUTPUT SWING (V} Input Bias Current Ta2 28C a -18 -i 8 $ 1a COMMON-MODE VOLTAGE (V) Supply Current 7 o* 58C A Te = 28C Tee 126C 4 ye LA rise? 2 1 a 5 10 18 Fs] 25 SUPPLY VOLTAGE {:) Positive Common-Mode Input Voltage Limit 20 Sta 5 16 16 2 POSITIVE SUPPLY VOLTS (Vv) TL/H/5646-2 Output Voitage Swing f Vg = 216V Ta* 26C 8 10 OUTPUT LOAD Ay, (k) 40 TL/H/5646-3 3-28Typical AC Performance Characteristics Gain Bandwidth 5 LF155 Vg = 10 Vg = H15V Vg > 20V GAIN BANDWIDTH (MHz} 1 ~5 -35 -15 5 25 45 GS 86 105 125 TEMPERATURE (C) Output Impedance 1000 Ta = 26C = t15V 100 1 Ay =10 OUTPUT IMPEDANCE (2) = at tk 18k 180k 1 10 FREQUENCY {Hz} LF155 Small Signal Pulse Response, Ay= +1 OUTPUT VOLTAGE SWING (50 mv/OlV) TIME (0.5 s/OIV) TL/H/5646-5 LF155 Large Signal Pulse Response, Ay = +1 OUTPUT VOLAGE SWING (5V/DIV} TIME (1 ps/DtV) TL/H/S646-8 UTPUT NG (50 mV/BIV; OUTPUT VOLTAGE SWING (50 mv/OIV) OUTPUT IMPEDANCE (2) OUTPUT VOLTAGE SWING (5V/DiV} UNITY GAIN BANDWIDTH (MHz) a Gain Bandwidth a LF15?7 CURVES EDENTICAL BUT MULTIPLIED BY 4 ~ - -B5-35 -16 5 25 45 65 85 105 128 TEMPERATURE (C) Output Impedance 100 Tas 26C Ay = 100 Vg t15V 10 Ay=1 T 1 Ay=10 rs) LF156 9 ost th 10k 100k 1 10 FREQUENCY (Hz) LF 156 Small Signal Pulse Response, Ay= +1 TIME (0.5 ys/OIV) TL/H/5646-6 LF156 Large Signal Pulse Response, Ay= +1 vs TIME (1 .s/ONV) TL/H/5646-9 OUTPUT VOLTAGE swiNG (sv/dlv) OUTPUT IMPEDANCE {2} OUTPUT VOLTAGE SWING {50 mv/DIV) Normalized Slew Rate 1.8 16 Vg = 15 1.4 12 1.0 08 O86 04 a2 6 55-35-15 5 26 45 BS 85 105 125 TEMPERATURE (C) TL/H/5646-4 Output Impedance 100 ET a = 25C L Vg 2 215V Ww eH Ay = 100 S + | 1 Ay =t0 01 tt Yt Lis? 0.01 JUL Aree drmclretiedeilelreeeecleaola Tk 10k 100k 4M 10M FREQUENCY (Hz) TL/H/5646-12 Small Signal Pulse Response, Ay= +5 TEME (0.1 us/OIV) TLAH/5646-~7 LF157 Large Signal Pulse Response, Ay= +5 TIME (0.5 ,:s/DIV) TL/H/564610 3-29 G2Se/V2ZSe/ZSE41/2S74 1/V 251/254 1/G9S8/V9SE4 1/9984 1/9S241/V9Sl /9S141/ESSe/VSse/SSe41/SSe41/WSS1/SSl41LF155/155A/LF255/LF355/355A/355B/LF 156/ 156A/LF256/LF356/LF356A/356B/LF157/ 157A/LF257/LF357/357A/357B Typical AC Performance Characteristics (continued) COMMON-MODE REJECTION RATIO (48) GAIN (48) OUTPUT SWING (v) FROM OV PP OUTPUT VOLTAGE SHANG (V) Inverter Settling Time LF16B Az 2eC Vg i15 . 05 1s 5 10 SETTLING TIME (us) Bode Plot 0 100 6 LFIE5 ns Vg = 2t8V -6 25 -10 k -1 ~i6 8 20 8 # -% - 0 18 -35 125 1 10 100 FREQUENCY (MHz) Commor-Mode Rejection Ratio 108 TT ey Vg #15V 8 Ns moa _ Tas 26C " Ne " NN t N 10 100k 1k 1k IM 10M FREQUENCY (Hi) Undistorted Output Voltage Vg = 2iBV h Ta= 25C 1 <8 10k 1004 14 FREQUENCY (Hz) 1 POWER SUPPLY REJECTION RATIO (eB) GAIN (d8) OUTPUT VOLTAGE SWING FROM OV (V) EQUIVALENT INPUT MOISE VOLTAGE (#//Az) Inverter Settling Time 10 TTiTtTitt Vg= t1hV Tas 2e'e 6 Lie diiy ev AA av | MN || LPIBE, Ay=-1 TT trte7, Ay=-6 amv AL tv 5 ~10 a1 ' 10 SETTLING TIME (a) Bode Plot 15 128 if 100 jt - Vge 2tiv 7] t a 3 -+ ws 8 -18 @ -18 4 5 - se =. | -5 2 | -100 -35 128 ~- 168 1 10 108 FREQUENCY (Miz) Power Supply Rejection Ratio 8 r _- LFISS N. nA Tac 2c WN sv N POSITIVE \ surety | a NEGATIVE SUPPLY N\ n XN ; N i th 1k 10h TM FREQUENCY (Hz) Equivaient Input Noise Voltage Ta? 1 10 1 th 10% FREQUENCY (Hz) POWER SUPPLY REJECTION RATIO (48) GAIN (dB) GPEN LOOP vuLTAGE GAIR (48) EQUIVALENT INPUT NOISE VOLTAGE (aV//Az) Open Loop Frequency Response 1% 100k 1% 10M FREQUENCY (Hz) Bade Plot 3 x % 26 se Fa % 6 :- aT] as 8 8 a ee 6 10? 18 126 16 ~158 it ~1%8 1 il} 10 FREQUENCY (MHz) Power Supply Rejection Ratio 128 Tar = t1h 198 SUPPLY. " r a | NEGATIVE SUPPLY 6 ings 1m: 36k 6h iM 1M FREQUENCY (Hz) Equivalent Input Noise Voltage (Expanded Scale) Tas 2ere =i16 a tk 100k FREQUENCY {Hz) TL/H/5646-11 3-30Detailed Schematic i) L ty a a ih a nO Ver in La oe) =e a ,y vy AA Ae =O OUT *G = 3 pF in LF157 series. Connection Diagrams (op views) Metal Can Package (H} TL/H/5646-14 Order Number LF155AH, LF156AH, LF157AH, LF155H, LF156H, LF157H, LF255H, LF256H, LF257H, LF355AH, LF356AH, LF357AH, LFS355BH, LF356BH, LF357BH, LF355H, LF356H or LF357H See NS Package Number HOSC Dual-In-Line Package (J) wom Nhe Nos Bc BALANCE 2c INPUT Sted = ye INPUT Std 10 OUTPUT yr 1S BALANCE we2J Bic TL/H/5646-30 Order Number LF155J, LF156J, LF157J, LF356J, LF356/, LF357J, LF355BJ, LF356BJ or LF357BJ See NS Package Number J14A ) -Vee a TL/H/5646-13 Duai-In-Line Package (M and N) 1 GALANCE == Zz - rT . HAUT a] 6 ourrut v- + 7 BALANCE TL/H/5646-29 Order Number LF355M, LF356M, LF357M, LF356BM, LF355BN, LF356BN, LF357BN, LF355N, LF3S6N or LF357N See NS Package Number MO8A or NOSE 3-31 82S0/VZSE/ ZSE41/2ZSe4d1/V2ZSb /ZSbL41/89SE/V9SES 1/9984 1/9524 1/V9SE /9SL41/ASSe/VSSE/SSE41/SS241/VSS1/SSl41 aLF155/155A/LF255/LF355/355A/355B/LF 156/ 156A/LF256/LF356/LF356A/356B/LF157/157A/LF257/LF357/357A/357B Application Hints The LF155/6/7 series are op amps with JFET input de- vices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accomodated without a large in- crease in input current. The maximum differential input volt- age is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the nega- tive supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. in neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier ina normal operating made. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common- mode voltage can exceed the positive supply by approxi- mately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for exam- ple, in a supply current monitor and/or limiter. Precautions should be taken to ensure that the power sup- ply for the integrated circuit never becomes reversed in Typical Circuit Connections Vos Adjustment yr Driving Capacitive Loads * Vos is adjusted with a 25k potenti- ometer LF155/6 R= 5k The potentiometer wiper is con- LFt657) R=1,25k nected to V+ For potentiometers with tempera- ture coefficient of 100 ppm/*C or less tha additional drift with adjust is = 0.5 pV/C/mv of adjustment HF. * Typical overall drift 5 pV/C + (0.5 EV /eC/ mV of adj.) Overshoot < 20% Settling time (t,) = 5 ps polarity or that the unit is not inadvertently installed back- wards in a socket as an unlimited current surge through the resulting forward ciode within the IC could cause fusing of the internal conductors and result in a destroyed unit. Because these amplifiers are JFET rather than MOSFET input op amps they do not require special handling. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in or- der to ensure stability. For example, resisters from the out- put to an input should be placed with the body close to the input to minimize pickup and maximize the frequency of the feedback pole by minimizing the capacitance fram the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capaci- tance from the input of the device (usually the inverting in- put} to ac ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the fesdback poie is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the AC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. LF157. A Large Power BW Amplifier o Your TL/H/5646- 15 For distortion < 1% and @ 20 Vp-p Vour swing, power bandwidth is: 500 kHz. Due to a unique output stage design, these am- plifiers have the ability ta drive larga capacitive loads and still maintain stability. CLajagg = 0.01Typical Applications Settling Time Test Circult o tw 2neai6 V DUT 6 Te * Settling time is tasted with the LF155/6 connected 1.0K, ur $i as unity gain inverter and LF157 connacted for Ay = 5 FET used to isolate the probe capacitance Output = 10V step Ay = 5 for LF157 OSCILLOSCOPE TL/H/S646- 16 Large Signal inverter Output, Vout (from Settling Time Circuit) LF356 sv/Div Sv/olv 2 s/DiV tualDtV Vus/DIV TL/H/5646-17 TL/H/5646-18 TL/H/5646-19 Low Drift Adjustable Voltage Reference A VouT/AT= 0,002% C * All resistors and potentiometers should be wire-wound P1: drift adjust @ P2: Vout adjust * Use LF155 for = Low Ip Vour" 10 = Low drift = Low supply current 2N4116 TL/H/5648-20 3-33 GZS/VZSE/ZSE4 1/2504 1/V 251/251 41/9S8/V9S841/9SE41/9Se5 1/V9S 1 /9S1 4 1/ESSb/VSSe/SSb41/SSe41/ VSS /SStatLF155/155A/LF255/LF355/355A/355B/LF 156/ 156A/LF256/LF356/LF356A/356B/LF157/157A/LF257/LF357/357A/357B Typical Applications (Continued) Fast Logarithmic Converter +1 I, ae Dynamic range: 100 pA < | s 1 mA (5 dec- ades}, \Vo|=1V/decade Transient response: 3 ps for Al\= 1 decade C1, G2, R2, R3: added dynamic compensation Vos adjust the LF156 to minimize quiescent error Fr: Tel Labs type 081 + 0.9% /*C TL/H/584B-21 R2 | kT R, 1 lVourl = [: 4 Fe InV; = log Vi R2 = 15.7k, Ry = 1k, 0.3%/*C (for temperature compensation) RrJq VREF Ri Rily Precision Current Monitor s e . a : T J Vo=5 R1/R2 (V/mA of Is) v"O- Sie - - * Rt, R2, AG: 0.1% resistors Su Lr , SYSTEM Use LF155 for 1 + = Gommon-mode range to supply range = L = Low Ip ~ = = Low Vog ae Low Supply Current Ye no ET = TL/H/5646~31 8-Bit D/A Converter with Symmetrical Offset Binary Operation th fl agin wee 188 : wv #1 62 Bt bb es 8? Ladadeto tate taleta vace* tv OAAAAY Ip : > 7 DACeE LPS . HO Eo ee tyflmel+ |! = + v7} Rt * ~1v = TL/H/5646-32 * R41, R2 should be matched within +0.05% e Full-scale response time: 3ps Eo Bt B2 B3 64 BS B6 B7 B8 Comments +9.920} 1 1 #+ #%@ jd +t +1 += 1 *| Positive Full-Scale +0.040'1 0 0 0 90 0 0 90 (+) Zero-Scale ~0.040; 0 1 1 #1 161 1 1 () Zero-Scala -9.920;909 0 0 0 0 6 O- 0 | Negative Full-Scale 3-34Typical Applications (continued) Wide BW Low Noise, Low Drift Amplifier @ J | W fax = OO tity wis = S, *P IW: f = = 240 kx: lower BW: fivax 2nVp = ra Parasitic input capacitance C1 =< (3 pF for LF155, LF156 and LF 157 plus any additional layout capacitance) interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such that R2C2a R1C1. Boosting the LF 156 with a Current Amplifier at $k JouTimang = 150 mA (will drive RL 2 10020) AVour _ 0.15 . AT 1028 V/,8 (with C_ shown) No additional phase shift added by the current amplifier 3 Decades VCO c G31 uF IL W OA = TL/H/5646-24 Vo (R8+A7) * (6 Vpy RB RA) C Ri, R4 matched. Linearity 0.1% over 2 decades. O<Vo<390V, 10 Hz<f<10 kHz Isolating Large Capacitive Loads Vout Ri Oth + an -wv * Overshoot 6% ot, 10 ys When driving large G,. the Vout slew rate determinad by C_ and louTIMAXy: AVout _ lout . 9.02 AT CL 0.5 Low Drift Peak Detector AAs vVv TL/H/5646-22 V/s = 0.04 V/28 (with C, shown) +16 F 4i3 q TL/H/ 5646 a -iv * By adding D1 and Ry, Vp1 =0 during hold mode. Leakage of D2 provided by feedback path through Ar. * Leakage of circuit is essentially ld (LF 155, LF 156) plus capacitor leakage of Ce. Dioda 03 clamps Vout (A1) to VijVp3 to improve speed and to limit reverse bias of D2. Maximum input frequency should be << 4wFrCoo where Cop is the shunt capacitance of D2. Non-Inverting Unity Gain Operation for LF 157 RIC 2 Oo IS MAE) _ A2+ As 4 Ayocy = 1 f_gqp = 5 MHz Ri 2 R Inverting Unity Gain for LF 157 Re ANS - Ric 2 _ c (277) (58 MHz) LESS? 2 RI Re Ay(0c) =-1 = MHz TL/H/5646-25 w a Q t 3-35 GZSE/VLSE/2SE4 1/2524 1/V ZS /ZS5141/89SE/V9SEs1/9SE4 1/974 1/V9S1 /9S141/SSSe/VSSe/SSE41/SS741/VSSi/SSl 41LF155/155A/LF255/LF355/355A/355B/LF156/ 156A/LF256/LF356/LF356A/356B/LF 157/157A/LF257/LF357/357A/357B Typical Applications (Continues) High Impedance, Low Drift instrumentation Amplifier +15V ~1b Ra | 2R2 Vout = Bln + i] AV, V- + 2V < Vin common-mode < V+ * System Vog adjusted via A2 Vos adjust * Trim R3 to boost up CMRA to 120 dB. instrumentation amplifier resistor array recommended for besi accuracy and lowest drift TL/H/5648-26 3-36Typical Applications (Continued) Fast Sample and Hold = Vout SFET SWITCHES LFI1za1 > ~tav {5V TL/H/5646-33 * Both amplifiers (A1, A2) have faedback loops individuaily closed with stable responses (overshoot negligible) * Acquisition time T,, estimated by: [Rowe VIN, Sn] % provided that: Ta oe Ss Vin G Vin < 2S; Ron Chand Ts > Row is of SW1 louTiman . . og: Vin Ch If lity not satisfied: T, = inequality not sal A 20 mA LF156 develops full S, output capability for Vij 2 1V * Addition of SW2 improves accuracy by putting the voltage drop across SW inside the feedback Icop * Overall accuracy of system determined by tha accuracy of both amplifiers, At and A2 High Accuracy Sampie and Hold Ri Stk b0 vous TL/H/5646-27 By closing the loop through A2, the Vout accuracy will be determined uniquely by A1. No Vos adjust required for A2. T, can be estimated by same considerations as previously but, because of the added propagation delay in the feedback loop (A2) tha overshoot is not negligible. Overall system slower than fast sample and hold R1, Co: additional compensation Use LF156 for Fast settling time Low Vos GLSE/VWLSE/ZSE41/LS7I1/VLS1 / 2515 1/G9SE/V9SE41/SSE4 1/9524 1/951 /9S141/ESS8/VSSe/SSE41/SSed 1/VSSh/SS147 3-37LF155/155A/LF255/LF355/355A/355B/LF156/156A/LF256/LF356/LF356A/356B/LF157/157A/LF257/LF357/357A/357B Typical Applications (continued) High Q Band Pass Filter teF J 1. tT] * By adding positive feedback (R2} aaa Q increases to 40 wy EV OAT * fpp= 100 kHz s20k ye vi RE 7 SOUT _ 1NG Ok 2 Vin WY - = * Clean layout recommended rae Vour * Response to a 1 Vp-p tone burst: i 300 pus FC Ol oF Ru A oa = ~18V = TL/H/5646-28 High Q Notch Filter 2R1 = R= 10MQ 2C = G1 = 300 pf * Capacitors should be matched to obtain high Q *tnoTcH = 120 Hz, notch = 55 dB, Q > 100 Use LF155 for = Low Ig = Low supply current t c TL/H/5646-34 3-38