TLV702xx
GND
EN
IN OUT
VIN VOUT
On
Off
CIN COUT
1 F
Ceramic
m
TLV702xxDBV
SOT23-5
(TOPVIEW)
OUT
N/C
IN
GND
EN
1
2
3
5
4
EN
N/C
N/C
6
5
4
IN
GND
OUT
1
2
3
TLV702xxDSE
1,5mm 1,5mmSON
(TOPVIEW)
´
TLV702xx
www.ti.com
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
300-mA, Low-I
Q
, Low-Dropout Regulator
1FEATURES DESCRIPTION
234•Very Low Dropout: The TLV702xx series of low-dropout (LDO) linear
regulators are low quiescent current devices with
–37 mV at IOUT = 50 mA, VOUT = 2.8 V excellent line and load transient performance. These
–75 mV at IOUT = 100 mA, VOUT = 2.8 V LDOs are designed for power-sensitive applications.
–220mV at IOUT = 300 mA, VOUT = 2.8 V A precision bandgap and error amplifier provides
•2% Accuracy overall 2% accuracy. Low output noise, very high
power-supply rejection ratio (PSRR), and low-dropout
•Low IQ: 35 μAvoltage make this series of devices ideal for a wide
•Fixed-Output Voltage Combinations Possible selection of battery-operated handheld equipment. All
from 1.2 V to 4.8 V device versions have thermal shutdown and current
limit for safety.
•High PSRR: 68 dB at 1 kHz
•Stable with Effective Capacitance of 0.1 μF(1) Furthermore, these devices are stable with an
effective output capacitance of only 0.1 μF. This
•Thermal Shutdown and Overcurrent Protection feature enables the use of cost-effective capacitors
•Packages: SOT23-5 and 1,5mm ×1,5mm SON-6 that have higher bias voltages and temperature
(1) See the Input and Output Capacitor Requirements in the derating. The devices regulate to specified accuracy
Application Information section. with no output load.
The TLV702xxP series also provides an active
APPLICATIONS pulldown circuit to quickly discharge the outputs.
•Wireless Handsets The TLV702xx series of LDO linear regulators are
•Smart Phones, PDAs available in SOT23-5 and 1,5mm ×1,5mm SON-6
•MP3 Players packages.
•ZigBee®Networks
•Bluetooth®Devices
•Li-Ion Operated Handheld Products
•WLAN and Other PC Add-on Cards
Typical Application Circuit
(Fixed-Voltage Versions)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Bluetooth is a registered trademark of Bluetooth SIG.
3ZigBee is a registered trademark of the ZigBee Alliance.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. ©2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV702xx
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TLV702xx(x)Pyyyz XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in
the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 475 = 4.75 V).
Pis optional; devices with P have an LDO regulator with an active output discharge.
YYY is the package designator.
Zis package quantity. Use "R" for reel (3000 pieces), and "T" for tape (250 pieces).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Output voltages from 1.2 V to 4.8 V in 50-mV increments are available. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
MIN MAX
IN –0.3 +6.0 V
Voltage(2) EN –0.3 +6.0 V
OUT –0.3 +6.0 V
Current (source) OUT Internally Limited
Output short-circuit duration Indefinite
Operating virtual junction, TJ–55 +150 °C
Temperature Storage, Tstg –55 +150 °C
Human Body Model (HBM) QSS 009-105 (JESD22-A114A) 2 kV
Electrostatic Discharge Rating(3) Charge Device Model (CDM) QSS 009-147 500 V
(JESD22-C101B.01)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
DISSIPATION RATINGS(1)
PACKAGE RθJA TA<+25°C TA= +70°C TA= +85°C
DBV 200°C/W 500mW 275mW 200mW
DSE 180°C/W 555mW 305mW 222mW
(1) For board details, see the Thermal Information section.
2Submit Documentation Feedback ©2010–2011, Texas Instruments Incorporated
TLV702xx
www.ti.com
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
ELECTRICAL CHARACTERISTICS
At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = 0.9 V, COUT = 1.0 μF, and TJ=–40°C to
+125°C, unless otherwise noted. Typical values are at TJ= +25°C.
SPACE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2.0 5.5 V
VOUT DC output accuracy –40°C≤TJ≤+125°C–2 0.5 +2 %
VOUT(NOM) + 0.5 V ≤VIN ≤5.5 V,
ΔVO/ΔVIN Line regulation 1 5 mV
IOUT = 10 mA
ΔVO/ΔIOUT Load regulation 0 mA ≤IOUT ≤300 mA 1 15 mV
VIN = 0.98 ×VOUT(NOM), IOUT = 50 mA, 37 mV
VOUT = 2.8 V
VIN = 0.98 ×VOUT(NOM), IOUT = 100 mA,
VDO Dropout voltage(1) 75 mV
VOUT = 2.8 V
VIN = 0.98 ×VOUT(NOM), IOUT = 300 mA, 260 375 mV
VOUT = 2.35 V
ICL Output current limit VOUT = 0.9 ×VOUT(NOM) 320 500 860 mA
IOUT = 0 mA 35 55 μA
IGND Ground pin current IOUT = 300 mA, VIN = VOUT + 0.5 V 370 μA
VEN ≤0.4 V, VIN = 2.0 V 400 nA
ISHDN Ground pin current (shutdown) VEN ≤0.4 V, 2.0 V ≤VIN ≤4.5 V, 1 2 μA
TJ=–40°C to +85°C
VIN = 2.3 V, VOUT = 1.8 V,
PSRR Power-supply rejection ratio 68 dB
IOUT = 10 mA, f = 1 kHz
BW = 100 Hz to 100 kHz,
VNOutput noise voltage 48 μVRMS
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
tSTR Startup time(2) COUT = 1.0 μF, IOUT = 300 mA 100 μs
VEN(HI) Enable pin high (enabled) 0.9 VIN V
VEN(LO) Enable pin low (disabled) 0 0.4 V
IEN Enable pin current VIN = VEN = 5.5 V 0.04 μA
UVLO Undervoltage lockout VIN rising 1.9 V
Active pulldown resistance
RDISCHARGE VEN = 0 V 120 Ω
(TLV702xxP only) Shutdown, temperature increasing +165 °C
TSD Thermal shutdown temperature Reset, temperature decreasing +145 °C
TJOperating junction temperature –40 +125 °C
(1) VDO is measured for devices with VOUT(NOM) ≥2.35 V.
(2) Startup time = time from EN assertion to 0.98 ×VOUT(NOM).
©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Thermal
Shutdown
Current
Limit
UVLO
Bandgap
IN
EN
OUT
LOGIC
GND
TLV702xxSeries
Thermal
Shutdown
Current
Limit
UVLO
Bandgap
IN
EN
OUT
LOGIC
GND
TLV702xxPSeries
120W
TLV702xx
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. TLV702xx
Figure 2. TLV702xxP
4Submit Documentation Feedback ©2010–2011, Texas Instruments Incorporated
OUT
NC
IN
GND
EN
1
2
3
5
4
EN
N/C
N/C
6
5
4
IN
GND
OUT
1
2
3
TLV702xx
www.ti.com
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
PIN CONFIGURATIONS
DBV PACKAGE
SOT23-5
(TOP VIEW)
DSE PACKAGE
1,5mm ×1,5mm SON-6
(TOP VIEW)
PIN DESCRIPTIONS
PIN SOT23-5 SON-6
NAME DBV DSE DESCRIPTION
Input pin. A small 1-μF ceramic capacitor is recommended from this pin to ground to assure stability and
IN 1 1 good transient performance. See Input and Output Capacitor Requirements in the Application Information
section for more details.
GND 2 2 Ground pin
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into
shutdown mode and reduces operating current to 1 μA, nominal.
EN 3 6 For TLV702xxP, output voltage is discharged through an internal 120-Ωresistor when device is shut
down.
NC 4 4, 5 No connection. This pin can be tied to ground to improve thermal dissipation.
Regulated output voltage pin. A small 1-μF ceramic capacitor is needed from this pin to ground to assure
OUT 5 3 stability. See Input and Output Capacitor Requirements in the Application Information section for more
details.
©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
VOUT (V)
2.1 2.6 3.1 3.6 4.1 4.6 5.1
V (V)
IN
5.6
+125 C°
+85 C°
+25 C°
-40 C°
V =1.8V
I =10mA
OUT
OUT
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
VOUT (V)
2.3 2.7 3.1 3.5 3.9 4.3 4.7
V (V)
IN
5.5
5.1
+125 C°
+85 C°
+25 C°
-40 C°
V =1.8V
I =300mA
OUT
OUT
0 100 150 300
I (mA)
OUT
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
V (V)
OUT
50 200
+125 C°
+85 C°
+25 C°
-40 C°
V =1.8V
OUT
250
350
300
250
200
150
100
50
0
V (mV)
DO
2.25 2.75 3.25 3.75 4.25 4.75
V (V)
IN
+125 C°
+85 C°
+25 C°
-40 C°
I =300mA
OUT
0 100 150 300
I (mA)
OUT
300
250
200
150
100
50
0
V (mV)
DO
50 200
+125 C°
+85 C°
+25 C°
-40 C°
V =4.8V
OUT
250
TLV702xx
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS
Over operating temperature range (TJ=–40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater;
IOUT = 10 mA, VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ= +25°C.
LINE REGULATION LINE REGULATION
Figure 3. Figure 4.
LOAD REGULATION DROPOUT VOLTAGE vs INPUT VOLTAGE
Figure 5. Figure 6.
DROPOUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs TEMPERATURE
Figure 7. Figure 8.
6Submit Documentation Feedback ©2010–2011, Texas Instruments Incorporated
50
45
40
35
30
25
20
15
10
5
0
IGND ( Am)
2.1 2.6 3.1 3.6 4.1 4.6 5.1
V (V)
IN
5.6
+125 C°
+85 C°
+25 C°
-40 C°
V =1.8V
OUT
50
45
40
35
30
25
20
15
10
5
0
I ( A)m
GND
-40 -25 -10 5 20 35 50 65 80 95 110
Temperature( C)°
125
V =1.8V
OUT
2.5
2
1.5
1
0.5
0
ISHDN ( Am)
2.1 2.6 3.1 3.6 4.1 4.6 5.1
V (V)
IN
5.6
+125 C°
+85 C°
+25 C°
-40 C°
V =1.8V
OUT
700
600
500
400
300
200
100
0
ILIM (mA)
2.3 2.7 3.1 3.5 3.9 4.3 4.7
V (V)
IN
5.5
5.1
V =1.8V
OUT
+125 C°
+85 C°
+25 C°
-40 C°
100
90
80
70
60
50
40
30
20
10
0
PSRR(dB)
10 100 1k 10k 100k 1M 10M
Frequency(Hz)
I =150mA
OUT
I =10mA
OUT
V V =0.5V
IN OUT
-
TLV702xx
www.ti.com
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ=–40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater;
IOUT = 10 mA, VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ= +25°C.
GROUND PIN CURRENT vs INPUT VOLTAGE GROUND PIN CURRENT vs LOAD
Figure 9. Figure 10.
GROUND PIN CURRENT vs TEMPERATURE SHUTDOWN CURRENT vs INPUT VOLTAGE
Figure 11. Figure 12.
CURRENT LIMIT vs INPUT VOLTAGE POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
Figure 13. Figure 14.
©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
10
1
0.1
0.01
0.001
OutputSpectralNoiseDensity( V/ )m ÖHz
10 100 1k 10k 100k 1M 10M
Frequency(Hz)
V =1.8V
OUT
I =10mA
C =C =1 F
OUT
IN OUT m
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
InputVoltage(V)
80
70
60
50
40
30
20
10
0
PSRR(dB)
10kHz
100kHz
1kHz V =1.8V
OUT
100mA/div
50mV/div
10 s/divm
VOUT
IOUT
200mA
0mA
t =t =1 s
R F m
VOUT =1.8V
20mA/div
5mV/div
10 s/divm
VOUT
VOUT =1.8V
IOUT
10mA
0mA
t =t =1 s
R F m
50mA/div
20mV/div
10 s/divm
VOUT
IOUT 50mA
0mA
t =t =1 s
R F m
VOUT =1.8V
200mA/div
100mV/div
10 s/divm
VOUT
300mA
0mA
t =t = s
R F m1
IOUT
VOUT =1.8V
TLV702xx
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ=–40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater;
IOUT = 10 mA, VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ= +25°C.
POWER-SUPPLY RIPPLE REJECTION vs INPUT VOLTAGE OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
Figure 15. Figure 16.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 17. Figure 18.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 19. Figure 20.
8Submit Documentation Feedback ©2010–2011, Texas Instruments Incorporated
1V/div
5mV/div
1ms/div
VOUT
SlewRate=1V/ sm
VIN
2.9V
2.3V
V =1.8V
I 300mA
OUT
OUT =
1V/div
5mV/div
1ms/div
VOUT
VIN 2.9V
2.3V
V =1.8V
I 1mA
OUT
OUT =
SlewRate=1V/ sm
1V/div
10mV/div
1ms/div
SlewRate=1V/ sm
V =1.8V
I =300mA
OUT
OUT
5.5V
VIN
2.1V
VOUT
1V/div
200ms/div
VOUT
VIN
V =1.8V
OUT
I 1mA
OUT =
TLV702xx
www.ti.com
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ=–40°C to +125°C), VIN = VOUT(TYP) + 0.5 V or 2.0 V, whichever is greater;
IOUT = 10 mA, VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ= +25°C.
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 21. Figure 22.
LINE TRANSIENT RESPONSE VIN RAMP UP, RAMP DOWN RESPONSE
Figure 23. Figure 24.
©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
t=(120 R )
(120+R )
L
L
··COUT
TLV702xx
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
www.ti.com
APPLICATION INFORMATION
The TLV702xx belongs to a new family of BOARD LAYOUT RECOMMENDATIONS TO
next-generation value LDO regulators. These devices IMPROVE PSRR AND NOISE PERFORMANCE
consume low quiescent current and deliver excellent Input and output capacitors should be placed as
line and load transient performance. These close to the device pins as possible. To improve ac
characteristics, combined with low noise and very performance such as PSRR, output noise, and
good PSRR with little (VIN –VOUT) headroom, make transient response, it is recommended that the board
this family of devices ideal for portable RF be designed with separate ground planes for VIN and
applications. This family of regulators offers current VOUT, with the ground plane connected only at the
limit and thermal protection, and is specified GND pin of the device. In addition, the ground
from –40°C to +125°C. connection for the output capacitor should be
connected directly to the GND pin of the device. High
INPUT AND OUTPUT CAPACITOR ESR capacitors may degrade PSRR performance.
REQUIREMENTS
1.0-μF X5R- and X7R-type ceramic capacitors are INTERNAL CURRENT LIMIT
recommended because these capacitors have The TLV702xx internal current limit helps to protect
minimal variation in value and equivalent series the regulator during fault conditions. During current
resistance (ESR) over temperature. limit, the output sources a fixed amount of current
However, the TLV702xx is designed to be stable with that is largely independent of the output voltage. In
an effective capacitance of 0.1 μF or larger at the such a case, the output voltage is not regulated, and
output. Thus, the device is stable with capacitors of is VOUT = ILIMIT ×RLOAD. The PMOS pass transistor
other dielectric types as well, as long as the effective dissipates (VIN –VOUT)×ILIMIT until thermal shutdown
capacitance under operating bias voltage and is triggered and the device turns off. As the device
temperature is greater than 0.1 μF. This effective cools, it is turned on by the internal thermal shutdown
capacitance refers to the capacitance that the LDO circuit. If the fault condition continues, the device
sees under operating bias voltage and temperature cycles between current limit and thermal shutdown.
conditions; that is, the capacitance after taking both See the Thermal Information section for more details.
bias voltage and temperature derating into The PMOS pass element in the TLV702xx has a
consideration. In addition to allowing the use of built-in body diode that conducts current when the
lower-cost dielectrics, this capability of being stable voltage at OUT exceeds the voltage at IN. This
with 0.1-μF effective capacitance also enables the current is not limited, so if extended reverse voltage
use of smaller footprint capacitors that have higher operation is anticipated, external limiting to 5% of the
derating in size- and space-constrained applications. rated output current is recommended.
NOTE: Using a 0.1-μF rated capacitor at the output
of the LDO does not ensure stability because the SHUTDOWN
effective capacitance under the specified operating The enable pin (EN) is active high. The device is
conditions would be less than 0.1 μF. Maximum ESR enabled when voltage at EN pin goes above 0.9V.
should be less than 200 mΩ.This relatively lower value of voltage required to turn
Although an input capacitor is not required for the LDO on can be exploited to power the LDO with a
stability, it is good analog design practice to connect GPIO of recent processors whose GPIO Logic 1
a 0.1-μF to 1.0-μF, low ESR capacitor across the IN voltage level is lower than traditional microcontrollers.
pin and GND pin of the regulator. This capacitor The device is turned off when the EN pin is held at
counteracts reactive input sources and improves less than 0.4V. When shutdown capability is not
transient response, noise rejection, and ripple required, EN can be connected to the IN pin.
rejection. A higher-value capacitor may be necessary The TLV702xxP version has internal active pull-down
if large, fast rise-time load transients are anticipated, circuitry that discharges the output with a time
or if the device is not located close to the power constant of:
source. If source impedance is more than 2 Ω, a
0.1-μF input capacitor may be necessary to ensure
stability.
where:
•RL= Load resistance
•COUT = Output capacitor (1)
10 Submit Documentation Feedback ©2010–2011, Texas Instruments Incorporated
P =(V V ) I- ´
D IN OUT OUT
TLV702xx
www.ti.com
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
DROPOUT VOLTAGE The internal protection circuitry of the TLV702xx has
been designed to protect against overload conditions.
The TLV702xx uses a PMOS pass transistor to It was not intended to replace proper heatsinking.
achieve low dropout. When (VIN –VOUT) is less than Continuously running the TLV702xx into thermal
the dropout voltage (VDO), the PMOS pass device is shutdown degrades device reliability.
in the linear region of operation and the
input-to-output resistance is the RDS(ON) of the PMOS POWER DISSIPATION
pass element. VDO scales approximately with output
current because the PMOS device behaves as a The ability to remove heat from the die is different for
resistor in dropout. each package type, presenting different
considerations in the printed circuit board (PCB)
As with any linear regulator, PSRR and transient layout. The PCB area around the device that is free
response are degraded as (VIN –VOUT) approaches of other components moves the heat from the device
dropout. This effect is shown in Figure 15 in the to the ambient air.
Typical Characteristics section. Thermal performance data for TLV702xx were
TRANSIENT RESPONSE gathered using the TLV700 evaluation module (EVM),
a 2-layer board with two ounces of copper per side.
As with any regulator, increasing the size of the The dimensions and layout for the SOT23-5 (DBV)
output capacitor reduces over-/undershoot magnitude EVM are shown in Figure 25 and Figure 26.
but increases the duration of the transient response. Corresponding thermal performance data are given in
Table 1. Note that this board has provision for
UNDERVOLTAGE LOCKOUT (UVLO) soldering not only the SOT23-5 package on the
bottom layer, but also the SC-70 package on the top
The TLV702xx uses an undervoltage lockout circuit to layer. The dimensions and layout of the SON-6 (DSE)
keep the output shut off until internal circuitry is EVM is shown in Figure 27 and Figure 28.
operating properly. Corresponding thermal performance data is again
given in Table 1. Using heavier copper increases the
THERMAL INFORMATION effectiveness in removing heat from the device. The
Thermal protection disables the output when the addition of plated through-holes to heat-dissipating
junction temperature rises to approximately +165°C, layers also improves heatsink effectiveness.
allowing the device to cool. When the junction Power dissipation depends on input voltage and load
temperature cools to approximately +145°C, the conditions. Power dissipation (PD) is equal to the
output circuitry is again enabled. Depending on power product of the output current and the voltage drop
dissipation, thermal resistance, and ambient across the output pass element, as shown in
temperature, the thermal protection circuit may cycle Equation 2.
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of (2)
overheating. PACKAGE MOUNTING
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an Solder pad footprint recommendations for the
inadequate heatsink. For reliable operation, junction TLV702xx are available from the Texas Instruments
temperature should be limited to +125°C maximum. web site at www.ti.com. The recommended land
pattern for the DBV and DSE packages are shown in
To estimate the margin of safety in a complete design Figure 29 and Figure 30, respectively.
(including heatsink), increase the ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions.
Table 1. EVM Dissipation Ratings
PACKAGE RθJA TA<+25°C TA= +70°C TA= +85°C
DBV 200°C/W 500mW 275mW 200mW
DSE 180°C/W 555mW 305mW 222mW
©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
18.16mm
20.7mm
18.16mm
20.7mm
TLV702xx
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
www.ti.com
Figure 25. HPA503 EVM Top Layer
Figure 26. HPA503 EVM Bottom Layer
12 Submit Documentation Feedback ©2010–2011, Texas Instruments Incorporated
17mm
20.5mm
17mm
20.5mm
TLV702xx
www.ti.com
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
Figure 27. DSE EVM Top Layer
Figure 28. DSE EVM Bottom Layer
©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
ExampleBoardLayout
StencilOpenings
BasedonStencilThickness
of0,127mm(.005in)
TLV702xx
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
www.ti.com
(1) All linear dimensions are in millimeters.
(2) Customers should place a note on the circuit board fabrication drawing not to alter the center solder mask defined
pad.
(3) Publication IPC-7351 is recommended for alternate designs.
(4) Laser-cutting apertures with trapedzoidal walls and also rounding corners will offer better paste release. Customers
should contact their board assembly site for stencil design recommendations. Example stencil design based on a 50%
volumetric load solder paste. Refer to IPC-7525 for other stencil recommendations.
Figure 29. Recommended Land Pattern for DBV Package
14 Submit Documentation Feedback ©2010–2011, Texas Instruments Incorporated
TLV702xx
www.ti.com
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
Figure 30. Recommended Land Pattern for DSE Package
©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
TLV702xx
SLVSAG6B –SEPTEMBER 2010–REVISED FEBRUARY 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2010) to Revision B Page
•Added SON-6 (DSE) package and related references to data sheet ................................................................................... 1
Changes from Original (September 2010) to Revision A Page
•Updated ordering number in Ordering Information table ...................................................................................................... 2
16 Submit Documentation Feedback ©2010–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 3-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV70212DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70212DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70218DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70218DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70220PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70220PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70225DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70225DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70225DSER ACTIVE WSON DSE 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70225DSET ACTIVE WSON DSE 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70228DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70228DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70228DSER ACTIVE WSON DSE 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70228DSET ACTIVE WSON DSE 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70228PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70228PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70229DSER ACTIVE WSON DSE 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 3-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV70229DSET ACTIVE WSON DSE 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70230DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70230DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70231DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70231DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70233DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70233DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70233DSER ACTIVE WSON DSE 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70233DSET ACTIVE WSON DSE 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70235DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70235DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70236DSER ACTIVE WSON DSE 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70236DSET ACTIVE WSON DSE 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70237DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70237DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70245DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70245DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV702475DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 3-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV702475DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV70212DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TLV70212DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70212DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TLV70218DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70220PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TLV70220PDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TLV70225DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TLV70225DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70225DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TLV70225DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2
TLV70225DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2
TLV70228DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70228DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2
TLV70228DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2
TLV70228PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TLV70228PDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TLV70229DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2
TLV70229DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV70230DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70231DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70233DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70233DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2
TLV70233DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2
TLV70235DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70236DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2
TLV70236DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2
TLV70237DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70245DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV702475DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV70212DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
TLV70212DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70212DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
TLV70218DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70220PDBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
TLV70220PDBVT SOT-23 DBV 5 250 202.0 201.0 28.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV70225DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
TLV70225DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70225DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
TLV70225DSER WSON DSE 6 3000 203.0 203.0 35.0
TLV70225DSET WSON DSE 6 250 203.0 203.0 35.0
TLV70228DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70228DSER WSON DSE 6 3000 203.0 203.0 35.0
TLV70228DSET WSON DSE 6 250 203.0 203.0 35.0
TLV70228PDBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
TLV70228PDBVT SOT-23 DBV 5 250 202.0 201.0 28.0
TLV70229DSER WSON DSE 6 3000 202.0 201.0 28.0
TLV70229DSET WSON DSE 6 250 202.0 201.0 28.0
TLV70230DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70231DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70233DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70233DSER WSON DSE 6 3000 203.0 203.0 35.0
TLV70233DSET WSON DSE 6 250 203.0 203.0 35.0
TLV70235DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70236DSER WSON DSE 6 3000 203.0 203.0 35.0
TLV70236DSET WSON DSE 6 250 203.0 203.0 35.0
TLV70237DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70245DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV702475DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2012
Pack Materials-Page 3
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