Publication Number 23544 Revision CAmendment 3Issue Date February 26, 2009
Am29LV065D
Am29LV065D Cover Sheet
Data Sheet (Retired Product)
This product has been retired and is not recommended for designs. For new and current designs, S29GL064N supercedes
Am29LV065D. This is the factory-recommended migration path. Please refer to the S29GL-N data sheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
2 Am29LV065D 23544_C3 February 26, 2009
Data Sheet (Retired Product)
This page left intentionally blank.
DATA SHEET
Publication# 23544 Rev: CAmendment: 3
Issue Date: February 26, 2009
Refer to AMD’s Website (www.amd.com) for the latest information.
Am29LV065D
64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileIOTM Control
This product has been retired and is not recommended for designs. For new and current designs, S29GL064N supercedes
Am29LV065D. This is the factory-recommended migration path. Please refer to the S29GL-N data sheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— 3.0 to 3.6 volt read, erase, and program operations
■VersatileIOTM control
— Device generates output voltages and tolerates input
voltages on the DQ I/Os as determined by the voltage
on VIO input
■High performance
— Access times as fast as 90 ns
■Manufactured on 0.23 µm process technology
■CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
■SecSi (Secured Silicon) Sector region
— 256-byte sector for permanent, secure identification
through an 16-byte random Electronic Serial Number
— May be programmed and locked at the factory or by
the customer
— Accessible through a command sequence
■Ultra low power consumption (typical values at 3.0 V,
5 MHz)
— 9 mA typical active read current
— 26 mA typical erase/program current
— 200 nA typical standby mode current
■Flexible sector architecture
— One hundred twenty-eight 64 Kbyte sectors
■Sector Protection
— A hardware method to lock a sector to prevent
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
■Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
■Minimum 1 million erase cycle guarantee per sector
■Package options
— 48-pin TSOP
— 63-ball FBGA
■Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
■Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
■Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
■Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
■Hardware reset pin (RESET#)
— Hardware method to reset the device for reading array
data
■ACC pin
— Accelerates programming time for higher throughput
during system production
■Program and Erase Performance (VHH not applied to
the ACC input pin)
— Byte program time: 5 µs typical
— Sector erase time: 0.9 s typical for each 64 Kbyte
sector
■20-year data retention at 125°C
— Reliable operation for the life of the system
4 Am29LV065D February 26, 2009
GENERAL DESCRIPTION
The Am29LV065D is a 64 Mbit, 3.0 Volt (3.0 V to 3.6
V) single power supply flash memory devices orga-
nized as 8,388,608 bytes. Data appears on DQ0-DQ7.
The device is designed to be programmed in-system
with the standard system 3.0 volt VCC supply. A 12.0
volt VPP is not required for program or erase opera-
tions. The device can also be programmed in standard
EPROM programmers.
The device offers access times of 90, 100, and 120 ns.
The device is offered in standard 48-pin TSOP and
63-ball FBGA packages. To eliminate bus contention
each device has separate chip enable (CE#), write en-
able (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. VIO is available in two
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various system environments.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
gle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The SecSiTM (Secured Silicon) Sector provides an
minimum 256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to VHH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
February 26, 2009 Am29LV065D 5
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11
Table 1. Am29LV065D Device Bus Operations ..............................11
VersatileIOTM (VIO) Control ...................................................... 11
Requirements for Reading Array Data ................................... 11
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation ............................................. 12
Autoselect Functions .............................................................. 12
Standby Mode ........................................................................ 12
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 13
Table 2. Sector Address Table ........................................................13
Autoselect Mode ..................................................................... 17
Table 3. Am29LV065D Autoselect Codes, (High Voltage Method) 17
Sector Group Protection and Unprotection ............................. 18
Table 4. Sector Group Protection/Unprotection Address Table .....18
Temporary Sector Group Unprotect ....................................... 19
Figure 1. Temporary Sector Group Unprotect Operation................ 19
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Table 5. SecSi Sector Contents ......................................................21
Figure 3. SecSi Sector Protect Verify.............................................. 22
Hardware Data Protection ...................................................... 22
Low VCC Write Inhibit ............................................................ 22
Write Pulse “Glitch” Protection ............................................... 22
Logical Inhibit .......................................................................... 22
Power-Up Write Inhibit ............................................................ 22
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 6. CFI Query Identification String.......................................... 23
System Interface String................................................................... 23
Table 8. Device Geometry Definition .............................................. 23
Table 9. Primary Vendor-Specific Extended Query ........................ 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................ 25
Reset Command ..................................................................... 25
Autoselect Command Sequence ............................................ 25
Enter SecSi Sector/Exit SecSi Sector
Command Sequence .............................................................. 25
Byte Program Command Sequence ....................................... 26
Unlock Bypass Command Sequence ..................................... 26
Figure 4. Program Operation .......................................................... 26
Chip Erase Command Sequence ........................................... 27
Sector Erase Command Sequence ........................................ 27
Erase Suspend/Erase Resume Commands ........................... 27
Figure 5. Erase Operation............................................................... 28
Command Definitions ............................................................. 29
Table 10. Am29LV065D Command Definitions ............................. 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . 30
DQ7: Data# Polling ................................................................. 30
Figure 6. Data# Polling Algorithm .................................................. 30
RY/BY#: Ready/Busy# ............................................................ 31
DQ6: Toggle Bit I .................................................................... 31
Figure 7. Toggle Bit Algorithm........................................................ 31
DQ2: Toggle Bit II ................................................................... 32
Reading Toggle Bits DQ6/DQ2 ............................................... 32
DQ5: Exceeded Timing Limits ................................................ 32
DQ3: Sector Erase Timer ....................................................... 32
Table 11. Write Operation Status ................................................... 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 8. Maximum Negative Overshoot Waveform ..................... 34
Figure 9. Maximum Positive Overshoot Waveform....................... 34
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 36
Figure 11. Typical ICC1 vs. Frequency ............................................ 36
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Test Setup.................................................................... 37
Table 12. Test Specifications ......................................................... 37
Figure 13. Input Waveforms and Measurement Levels ................. 37
Key to Switching Waveforms. . . . . . . . . . . . . . . . 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Read-Only Operations ........................................................... 38
Figure 14. Read Operation Timings ............................................... 38
Hardware Reset (RESET#) .................................................... 39
Figure 15. Reset Timings ............................................................... 39
Erase and Program Operations .............................................. 40
Figure 16. Program Operation Timings.......................................... 41
Figure 17. Accelerated Program Timing Diagram.......................... 41
Figure 18. Chip/Sector Erase Operation Timings .......................... 42
Figure 19. Data# Polling Timings (During Embedded Algorithms). 43
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 44
Figure 21. DQ2 vs. DQ6................................................................. 44
Temporary Sector Unprotect .................................................. 45
Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 45
Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 46
Figure 24. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 48
Erase And Programming Performance . . . . . . . 49
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 49
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 49
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 50
TS 048—48-Pin Standard Pinout Thin Small Outline
Package (TSOP) ..................................................................... 50
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
11 x 12 mm package .............................................................. 51
6 Am29LV065D February 26, 2009
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Part Number Am29LV065D
Speed Option
VCC = 3.0–3.6 V, VIO = 3.0–5.0 V 90R 120R
VCC = 3.0–3.6 V, VIO = 1.8–2.9 V 101R 121R
Max Access Time (ns) 90 100 120
CE# Access Time (ns) 90 100 120
OE# Access Time (ns) 35 35 50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
ACC
CE#
OE#
STB
STB
DQ0–DQ7
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A22
VIO
February 26, 2009 Am29LV065D 7
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
48
47
46
45
44
43
42
41
30
29
28
27
26
A16
A5
A15
NC
A22
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
NC
NC
A17
DQ0
VSS
NC
NC
NC
NC
A20
A19
A10
DQ7
DQ6
DQ5
OE#
VSS
CE#
A0
DQ4
VCC
VIO
A21
DQ3
DQ2
DQ1
48-Pin Standard TSOP
8 Am29LV065D February 26, 2009
CONNECTION DIAGRAMS
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
C2 D2
C3 D3
E2
E3
F2
F3
G2
G3
H2
H3
J2
J3
K2
A3 A4 A2 A1 A0 CE# OE# V
SS
A7 A18 A6 A5 DQ0 NC NC DQ1
RY/BY# ACC NC NC DQ2 DQ3 V
IO
A21
WE# RESET# A22 NC DQ5 NC V
CC
DQ4
A9 A8 A11 A12 A19 A10 DQ6 DQ7
A14 A13 A15 A16 A17 NC A20 V
SS
C4 D4 E4
A1 B1
A2
NC* NC*
NC*
F4 G4 H4 J4 K4
C5 D5 E5 F5 G5 H5 J5 K5
C6 D6 E6 F6 G6 H6 J6 K6
C7 D7 E7
NC*NC*
NC* NC*
A7 B7
A8 B8
F7 G7 H7 J7 K7
NC* NC*
NC* NC*
L7 M7
L8 M8
K3
L1
L2
M1
NC* NC*
NC* NC*
M2
* Balls are shorted together via the substrate but not connected to the die.
63-Ball FBGA
Top View, Balls Facing Down
February 26, 2009 Am29LV065D 9
PIN DESCRIPTION
A0–A22 = 23 Addresses inputs
DQ0–DQ7 = 8 Data inputs/outputs
CE# = Chip Enable input
OE# = Output Enable input
WE# = Write Enable input
ACC = Acceleration Input
RESET# = Hardware Reset Pin input
RY/BY# = Ready/Busy output
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VIO = Output Buffer power
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
23
8
DQ0–DQ7
A0–A22
CE#
OE#
WE#
RESET#
RY/BY#
ACC
VIO
10 Am29LV065D February 26, 2009
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29LV065D U 90R WH I N
OPTIONAL PROCESSING
Blank = Standard Processing
N = 16-byte ESN devices
(Contact an AMD representative for more information)
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
F = Industrial (–40°C to +85°C) with Pb-free package
PAC KAG E TY PE
E = 48-Pin Standard Pinout Thin Small Outline Package (TS 048)
WH = 63-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 11 x 12 mm package (FBE063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE
U = Uniform sector device
DEVICE NUMBER/DESCRIPTION
Am29LV065D
64 Megabit (8 M x 8-Bit) CMOS Uniform Sector Flash Memory with VersatileIO™ Control
3.0 Volt-only Read, Program, and Erase
Valid Combinations for TSOP
Packages Speed/VIO Range
AM29LV065DU90R,
AM29LV065DU90R EI, EF
90ns,
VIO = 3.0 V – 5.0 V
AM29LV065DU101R,
AM29LV065DU101R
100 ns,
VIO = 1.8 V – 2.9 V
AM29LV065DU120R,
AM29LV065DU120R EI, EF
120 ns,
VIO = 3.0 V – 5.0 V
AM29LV065DU121R,
AM29LV065DU121R
120 ns,
VIO = 1.8 V – 2.9 V
Valid Combinations for FBGA Packages
Speed/
VIO RangeOrder Number
Package
Marking
AM29LV065DU90R WHI,
WHF
L065DU90R I,
F
90 ns, VIO =
3.0 V – 5.0 V
AM29LV065DU101R L065DU01R 100 ns, VIO =
1.8 V – 2.9 V
AM29LV065DU120R WHI,
WHF
L065DU12R I,
F
120 ns, VIO =
3.0 V – 5.0 V
AM29LV065DU121R L065DU21R 120 ns, VIO =
1.8 V – 2.9 V
February 26, 2009 Am29LV065D 11
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Ta bl e 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV065D Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, V HH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A22:A0. Sector addresses are A22:A16.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version
ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileIOTM (VIO) Control
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. VIO is available in two
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various system environments.
For example, a VI/O of 4.5–5.0 volts allows for I/O at
the 5 volt level, driving and receiving signals to and
from other 5 V devices on the same data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
Operation CE# OE# WE# RESET# ACC
Addresses
(Note 2)
DQ0–
DQ7
Read L L H H XAIN DOUT
Write (Program/Erase) L H L H XAIN (Note 4)
Accelerated Program L H L H VHH AIN (Note 4)
Standby VCC ±
0.3 V XXVCC ±
0.3 V HX High-Z
Output Disable L H H H XX High-Z
Reset X X X L XX High-Z
Sector Group Protect (Note 2) L H L VID XSA, A6 = L,
A1 = H, A0 = L (Note 4)
Sector Group Unprotect
(Note 2) LHL V
ID XSA, A6 = H,
A1 = H, A0 = L (Note 4)
Temporary Sector Group
Unprotect XXX V
ID XAIN (Note 4)
12 Am29LV065D February 26, 2009
enabled for read access until the command register
contents are altered.
See “VersatileIOTM (VIO) Control” for more information.
Refer to the AC Read-Only Operations table for timing
specifications and to Figure 14 for the timing diagram.
ICC1 in the DC Characteristics table represents the ac-
tive current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Ta bl e 2 indicates the address
space that each sector occupies.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal op-
eration. Note that the ACC pin must not be at VHH for
operations other than accelerated programming, or
device damage may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
February 26, 2009 Am29LV065D 13
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The sys-
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 2. Sector Address Table
Sector A22 A21 A20 A19 A18 A17 A16
8-bit Address Range
(in hexadecimal)
SA0 0 0 0 0 0 0 0 000000–00FFFF
SA1 0 0 0 0 0 0 1 010000–01FFFF
SA2 0 0 0 0 0 1 0 020000–02FFFF
SA3 0 0 0 0 0 1 1 030000–03FFFF
SA4 0 0 0 0 1 0 0 040000–04FFFF
SA5 0 0 0 0 1 0 1 050000–05FFFF
SA6 0 0 0 0 1 1 0 060000–06FFFF
SA7 0 0 0 0 1 1 1 070000–07FFFF
SA8 0 0 0 1 0 0 0 080000–08FFFF
SA9 0 0 0 1 0 0 1 090000–09FFFF
SA10 0 0 0 1 0 1 0 0A0000–0AFFFF
SA11 0 0 0 1 0 1 1 0B0000–0BFFFF
SA12 0 0 0 1 1 0 0 0C0000–0CFFFF
SA13 0 0 0 1 1 0 1 0D0000–0DFFFF
SA14 0 0 0 1 1 1 0 0E0000–0EFFFF
SA15 0 0 0 1 1 1 1 0F0000–0FFFFF
SA16 0 0 1 0 0 0 0 100000–10FFFF
SA17 0 0 1 0 0 0 1 110000–11FFFF
SA18 0 0 1 0 0 1 0 120000–12FFFF
SA19 0 0 1 0 0 1 1 130000–13FFFF
SA20 0 0 1 0 1 0 0 140000–14FFFF
SA21 0 0 1 0 1 0 1 150000–15FFFF
SA22 0 0 1 0 1 1 0 160000–16FFFF
SA23 0 0 1 0 1 1 1 170000–17FFFF
SA24 0 0 1 1 0 0 0 180000–18FFFF
SA25 0 0 1 1 0 0 1 190000–19FFFF
SA26 0 0 1 1 0 1 0 1A0000–1AFFFF
14 Am29LV065D February 26, 2009
SA27 0 0 1 1 0 1 1 1B0000–1BFFFF
SA28 0 0 1 1 1 0 0 1C0000–1CFFFF
SA29 0 0 1 1 1 0 1 1D0000–1DFFFF
SA30 0 0 1 1 1 1 0 1E0000–1EFFFF
SA31 0 0 1 1 1 1 1 1F0000–1FFFFF
SA32 0 1 0 0 0 0 0 200000–20FFFF
SA33 0 1 0 0 0 0 1 210000–21FFFF
SA34 0 1 0 0 0 1 0 220000–22FFFF
SA35 0 1 0 0 0 1 1 230000–23FFFF
SA36 0 1 0 0 1 0 0 240000–24FFFF
SA37 0 1 0 0 1 0 1 250000–25FFFF
SA38 0 1 0 0 1 1 0 260000–26FFFF
SA39 0 1 0 0 1 1 1 270000–27FFFF
SA40 0 1 0 1 0 0 0 280000–28FFFF
SA41 0 1 0 1 0 0 1 290000–29FFFF
SA42 0 1 0 1 0 1 0 2A0000–2AFFFF
SA43 0 1 0 1 0 1 1 2B0000–2BFFFF
SA44 0 1 0 1 1 0 0 2C0000–2CFFFF
SA45 0 1 0 1 1 0 1 2D0000–2DFFFF
SA46 0 1 0 1 1 1 0 2E0000–2EFFFF
SA47 0 1 0 1 1 1 1 2F0000–2FFFFF
SA48 0 1 1 0 0 0 0 300000–30FFFF
SA49 0 1 1 0 0 0 1 310000–31FFFF
SA50 0 1 1 0 0 1 0 320000–32FFFF
SA51 0 1 1 0 0 1 1 330000–33FFFF
SA52 0 1 1 0 1 0 0 340000–34FFFF
SA53 0 1 1 0 1 0 1 350000–35FFFF
SA54 0 1 1 0 1 1 0 360000–36FFFF
SA55 0 1 1 0 1 1 1 370000–37FFFF
SA56 0 1 1 1 0 0 0 380000–38FFFF
SA57 0 1 1 1 0 0 1 390000–39FFFF
SA58 0 1 1 1 0 1 0 3A0000–3AFFFF
SA59 0 1 1 1 0 1 1 3B0000–3BFFFF
SA60 0 1 1 1 1 0 0 3C0000–3CFFFF
SA61 0 1 1 1 1 0 1 3D0000–3DFFFF
Table 2. Sector Address Table (Continued)
Sector A22 A21 A20 A19 A18 A17 A16
8-bit Address Range
(in hexadecimal)
February 26, 2009 Am29LV065D 15
SA62 0 1 1 1 1 1 0 3E0000–3EFFFF
SA63 0 1 1 1 1 1 1 3F0000–3FFFFF
SA64 1 0 0 0 0 0 0 400000–40FFFF
SA65 1 0 0 0 0 0 1 410000–41FFFF
SA66 1 0 0 0 0 1 0 420000–42FFFF
SA67 1 0 0 0 0 1 1 430000–43FFFF
SA68 1 0 0 0 1 0 0 440000–44FFFF
SA69 1 0 0 0 1 0 1 450000–45FFFF
SA70 1 0 0 0 1 1 0 460000–46FFFF
SA71 1 0 0 0 1 1 1 470000–47FFFF
SA72 1 0 0 1 0 0 0 480000–48FFFF
SA73 1 0 0 1 0 0 1 490000–49FFFF
SA74 1 0 0 1 0 1 0 4A0000–4AFFFF
SA75 1 0 0 1 0 1 1 4B0000–4BFFFF
SA76 1 0 0 1 1 0 0 4C0000–4CFFFF
SA77 1 0 0 1 1 0 1 4D0000–4DFFFF
SA78 1 0 0 1 1 1 0 4E0000–4EFFFF
SA79 1 0 0 1 1 1 1 4F0000–4FFFFF
SA80 1 0 1 0 0 0 0 500000–50FFFF
SA81 1 0 1 0 0 0 1 510000–51FFFF
SA82 1 0 1 0 0 1 0 520000–52FFFF
SA83 1 0 1 0 0 1 1 530000–53FFFF
SA84 1 0 1 0 1 0 0 540000–54FFFF
SA85 1 0 1 0 1 0 1 550000–55FFFF
SA86 1 0 1 0 1 1 0 560000–56FFFF
SA87 1 0 1 0 1 1 1 570000–57FFFF
SA88 1 0 1 1 0 0 0 580000–58FFFF
SA89 1 0 1 1 0 0 1 590000–59FFFF
SA90 1 0 1 1 0 1 0 5A0000–5AFFFF
SA91 1 0 1 1 0 1 1 5B0000–5BFFFF
SA92 1 0 1 1 1 0 0 5C0000–5CFFFF
SA93 1 0 1 1 1 0 1 5D0000–5DFFFF
SA94 1 0 1 1 1 1 0 5E0000–5EFFFF
SA95 1 0 1 1 1 1 1 5F0000–5FFFFF
SA96 1 1 0 0 0 0 0 600000–60FFFF
Table 2. Sector Address Table (Continued)
Sector A22 A21 A20 A19 A18 A17 A16
8-bit Address Range
(in hexadecimal)
16 Am29LV065D February 26, 2009
Note: All sectors are 64 Kbytes in size.
SA97 1 1 0 0 0 0 1 610000–61FFFF
SA98 1 1 0 0 0 1 0 620000–62FFFF
SA99 1 1 0 0 0 1 1 630000–63FFFF
SA100 1 1 0 0 1 0 0 640000–64FFFF
SA101 1 1 0 0 1 0 1 650000–65FFFF
SA102 1 1 0 0 1 1 0 660000–66FFFF
SA103 1 1 0 0 1 1 1 670000–67FFFF
SA104 1 1 0 1 0 0 0 680000–68FFFF
SA105 1 1 0 1 0 0 1 690000–69FFFF
SA106 1 1 0 1 0 1 0 6A0000–6AFFFF
SA107 1 1 0 1 0 1 1 6B0000–6BFFFF
SA108 1 1 0 1 1 0 0 6C0000–6CFFFF
SA109 1 1 0 1 1 0 1 6D0000–6DFFFF
SA110 1 1 0 1 1 1 0 6E0000–6EFFFF
SA111 1 1 0 1 1 1 1 6F0000–6FFFFF
SA112 1 1 1 0 0 0 0 700000–70FFFF
SA113 1 1 1 0 0 0 1 710000–71FFFF
SA114 1 1 1 0 0 1 0 720000–72FFFF
SA115 1 1 1 0 0 1 1 730000–73FFFF
SA116 1 1 1 0 1 0 0 740000–74FFFF
SA117 1 1 1 0 1 0 1 750000–75FFFF
SA118 1 1 1 0 1 1 0 760000–76FFFF
SA119 1 1 1 0 1 1 1 770000–77FFFF
SA120 1 1 1 1 0 0 0 780000–78FFFF
SA121 1 1 1 1 0 0 1 790000–79FFFF
SA122 1 1 1 1 0 1 0 7A0000–7AFFFF
SA123 1 1 1 1 0 1 1 7B0000–7BFFFF
SA124 1 1 1 1 1 0 0 7C0000–7CFFFF
SA125 1 1 1 1 1 0 1 7D0000–7DFFFF
SA126 1 1 1 1 1 1 0 7E0000–7EFFFF
SA127 1 1 1 1 1 1 1 7F0000–7FFFFF
Table 2. Sector Address Table (Continued)
Sector A22 A21 A20 A19 A18 A17 A16
8-bit Address Range
(in hexadecimal)
February 26, 2009 Am29LV065D 17
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect
mode requires VID (8.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in
Tabl e 3. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Table 2). Ta b l e 3
shows the remaining address bits that are don’t care.
When all necessary bits have been set as required,
the programming equipment may then read the corre-
sponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10 . This method
does not require VID. Refer to the Autoselect Com-
mand Sequence section for more information.
Table 3. Am29LV065D Autoselect Codes, (High Voltage Method)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Description CE# OE# WE#
A22
to
A16
A15
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0 DQ7 to DQ0
Manufacturer ID: AMD L L H X X VID XLXLL 01h
Device ID: Am29LV065D L L H X X VID XLXLH 93h
Sector Protection
Verification LLHSAXV
ID XLXHL 80h (protected),
00h (unprotected)
SecSi Sector Indicator Bit
(DQ7) LLH X XV
ID XLXHH 90h (factory locked),
10h (not factory locked)
18 Am29LV065D February 26, 2009
Sector Group Protection and
Unprotection
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Table 4 ). The hardware sector
group unprotection feature re-enables both program
and erase operations in previously protected sector
groups. Sector group protection/unprotection can be
implemented via two methods.
Sector protection and unprotection requires VID on the
RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 23 shows the timing
diagram. This method uses standard microprocessor
bus cycle timing. For sector group unprotect, all unpro-
tected sector groups must first be protected prior to
the first sector group unprotect write cycle.
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and pro-
tecting sector groups at its factory prior to shipping the
device through AMD’s ExpressFlash™ Service. Con-
tact an AMD representative for details.
It is possible to determine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.
Table 4. Sector Group Protection/Unprotection
Address Table
Note: All sector groups are 256 Kbytes in size.
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 4 )).
This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID (8.5 V – 12.5 V). During
this mode, formerly protected sector groups can be
programmed or erased by selecting the sector group
addresses. Once VID is removed from the RESET#
pin, all the previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
Figure 22 shows the timing diagrams, for this feature.
Sector Group A22–A18
SA0–SA3 00000
SA4–SA7 00001
SA8–SA11 00010
SA12–SA15 00011
SA16–SA19 00100
SA20–SA23 00101
SA24–SA27 00110
SA28–SA31 00111
SA32–SA35 01000
SA36–SA39 01001
SA40–SA43 01010
SA44–SA47 01011
SA48–SA51 01100
SA52–SA55 01101
SA56–SA59 01110
SA60–SA63 01111
SA64–SA67 10000
SA68–SA71 10001
SA72–SA75 10010
SA76–SA79 10011
SA80–SA83 10100
SA84–SA87 10101
SA88–SA91 10110
SA92–SA95 10111
SA96–SA99 11000
SA100–SA103 11001
SA104–SA107 11010
SA108–SA111 11011
SA112–SA115 11100
SA116–SA119 11101
SA120–SA123 11110
SA124–SA127 11111
February 26, 2009 Am29LV065D 19
Figure 1. Temporary Sector Group
Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect
Completed (Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
20 Am29LV065D February 26, 2009
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Sector Group Protect:
Write 60h to sector
group address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
group address
Wait 150 µs
Verify Sector Group
Protect: Write 40h
to sector group
address twith A6 = 0,
A1 = 1, A0 = 0
Read from
sector group address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
First Write
Cycle = 60h?
Data = 01h?
Remove V
ID
from RESET#
Write reset
command
Sector Group
Protect complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No
Sector Group
Unprotect:
Write 60h to sector
group address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
group address
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector group
address with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
Data = 00h?
Last sector
group
verified?
Remove V
ID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No All sector
groups
protected?
Yes
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
Set up
next sector group
address
No
Yes
No
Yes
No
No
Yes
No
Sector Group
Protect
Algorithm
Sector Group
Unprotect
Algorithm
First Write
Cycle = 60h?
Protect
another
sector group?
Reset
PLSCNT = 1
February 26, 2009 Am29LV065D 21
SecSi (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to utilize that
sector in any manner they choose. The customer-lock-
able version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indi-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
The SecSi sector address space in this device is allo-
cated as follows:
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. A factory locked
device has an 16-byte random ESN at addresses
000000h–00000Fh.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
vices are then shipped from AMD’s factory with the
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 256-byte SecSi sector. The
SecSi Sector is one-time programmable, may not be
erased, and can be locked only once. Note that the ac-
celerated programming (ACC) and unlock bypass
functions are not available when programming the
SecSi Sector.
The SecSi Sector area can be protected using one of
the following procedures:
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
■To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 3.
Once the SecSi Sector is locked and verified, the sys-
tem must write the Exit SecSi Sector Region com-
mand sequence to return to reading and writing the
remainder of the array.
The SecSi Sector protection must be used with cau-
tion since, once protected, there is no procedure avail-
able for unprotecting the SecSi Sector area and none
of the bits in the SecSi Sector memory space can be
modified in any way.
Table 5. SecSi Sector Contents
SecSi Sector
Address Range
Standard
Factory Locked
ExpressFlash
Factory Locked
Customer
Lockable
000000h–00000Fh ESN
ESN or
determined by
customer Determined by
customer
000010h–00007Fh,
000400h–00047Fh Unavailable Determined by
customer
22 Am29LV065D February 26, 2009
Figure 3. SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, any time the
device is ready to read array data (addresses are don’t
care). The system can read CFI information at the ad-
dresses given in Tables 6–9. To terminate reading CFI
data, the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi.html. Alter-
natively, contact an AMD representative for copies of
these documents.
Write 60h to
any address
Write 40h to SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
START
RESET# =
VIH or VID
Wait 1 μs
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove VIH or VID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete
February 26, 2009 Am29LV065D 23
Table 6. CFI Query Identification String
Table 7. System Interface String
Table 8. Device Geometry Definition
Addresses (x8) Data Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h Primary OEM Command Set
15h
16h
40h
00h Address for Primary Extended Table
17h
18h
00h
00h Alternate OEM Command Set (00h = none exists)
19h
1Ah
00h
00h Address for Alternate OEM Extended Table (00h = none exists)
Addresses (x8) Data Description
1Bh 27h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 36h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 00h VPP Min. voltage (00h = no VPP pin present)
1Eh 00h VPP Max. voltage (00h = no VPP pin present)
1Fh 04h Typical timeout per single byte write 2N µs
20h 00h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 0Ah Typical timeout per individual block erase 2N ms
22h 00h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 05h Max. timeout for byte write 2N times typical
24h 00h Max. timeout for buffer write 2N times typical
25h 04h Max. timeout per individual block erase 2N times typical
26h 00h Max. timeout for full chip erase 2N times typical (00h = not supported)
Addresses (x8) Data Description
27h 17h Device Size = 2N byte
28h
29h
00h
00h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
00h
00h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch 01h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
7Fh
00h
00h
01h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
24 Am29LV065D February 26, 2009
Table 9. Primary Vendor-Specific Extended Query
31h
32h
33h
34h
00h
00h
00h
00h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
00h
00h
00h
00h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
00h
00h
00h
00h
Erase Block Region 4 Information (refer to CFI publication 100)
Addresses (x8) Data Description
40h
41h
42h
50h
52h
49h
Query-unique ASCII string “PRI”
43h 31h Major version number, ASCII
44h 31h Minor version number, ASCII
45h 01h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
46h 02h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 04h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 01h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 04h Sector Protect/Unprotect scheme
04 = 29LV800 mode
4Ah 00h Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh 000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 00h Page Mode Type
00 = Not Supported
4Dh B5h ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh C5h ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 00h Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
February 26, 2009 Am29LV065D 25
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Ta b l e 1 0 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence may
place the device in an unknown state. A reset com-
mand is required to return the device to reading array
data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase op-
eration, or if the device is in the autoselect mode. See
the next section, Reset Command, for more informa-
tion.
See also “VersatileIOTM (VIO) Control” in the Device
Bus Operations section for more information. The
Read-Only Operations table provides the read param-
eters, and Figure 14 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to read several identifier codes at specific ad-
dresses:
Table 10 shows the address and data requirements.
The command sequence is an alternative to the high
voltage method shown in Tabl e 3 . The autoselect com-
mand sequence may be written to an address that is
either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 16-byte random Electronic Serial Num-
ber (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the de-
Identifier Code Address
Manufacturer ID 00h
Device ID 01h
SecSi Sector Factory Protect 03h
Sector Group Protect Verify (SA)02h
26 Am29LV065D February 26, 2009
vice to normal operation. Tabl e 10 shows the address
and data requirements for both command sequences.
See also “SecSi (Secured Silicon) Sector Flash
Memory Region” for further information.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 10 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Write Operation
Status section for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. The SecSi
sector, autoselect, and CFI functions are not available
when a program function is in progress. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 10 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
The device offers accelerated program operations
through the ACC pin. When the system asserts VHH on
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the
ACC pin must not be at VHH for operations other than
accelerated programming, or device damage may re-
sult.
Figure 4 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 16 for timing diagrams.
Figure 4. Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Table 10 for program command sequence.
February 26, 2009 Am29LV065D 27
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to the Write Operation Status section
for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. The SecSi
Sector, autoselect, and CFI functions are unavailable
when an erase operation is in progress. If that occurs,
the chip erase command sequence should be reiniti-
ated once the device has returned to reading array
data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must re-
write the command sequence and any additional ad-
dresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing sector. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing sector.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. The SecSi Sector,
autoselect, and CFI functions are unavailable when an
erase operation is in progress. All other commands
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the sector erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec-
tor erase operation, including the 50 µs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
28 Am29LV065D February 26, 2009
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard byte program operation.
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writ-
ing this command. Further writes of the Resume com-
mand are ignored. Another Erase Suspend command
can be written after the chip has resumed erasing. Figure 5. Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
February 26, 2009 Am29LV065D 29
Command Definitions
Table 10. Am29LV065D Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A22–A16 uniquely select any sector.
Notes:
1. See Ta bl e 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Unless otherwise noted, address bits A22–A12 are don’t cares.
5. No unlock or command cycles required when device is in read
mode.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
7. The fourth cycle of the autoselect command sequence is a read
cycle. See the Autoselect Command Sequence section for more
information.
8. The data is 80h for factory locked and 00h for not factory locked.
9. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
13. The Erase Resume command is valid only during the Erase
Suspend mode.
14. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect (Note 7)
Manufacturer ID 4 XXX AA XXX 55 XXX 90 X00 01
Device ID 4 XXX AA XXX 55 XXX 90 X01 93
SecSi Sector Factory
Protect (Note 8) 4 XXX AA XXX 55 XXX 90 X03 80/00
Sector Group Protect Verify
(Note 9) 4 XXX AA XXX 55 XXX 90 (SA)X02 00/01
Enter SecSi Sector Region 3 XXX AA XXX 55 XXX 88
Exit SecSi Sector Region 4 XXX AA XXX 55 XXX 90 XXX 00
Program 4 XXX AA XXX 55 XXX A0 PA PD
Unlock Bypass 3XXX AA XXX 55 XXX 20
Unlock Bypass Program (Note 10) 2XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2XXX 90 XXX 00
Chip Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 XXX 10
Sector Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 SA 30
Erase Suspend (Note 12) 1 XXX B0
Erase Resume (Note 13) 1 XXX 30
CFI Query (Note 14) 1 XX 98
30 Am29LV065D February 26, 2009
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Ta bl e 11 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is com-
plete or in progress. The device also provides a hard-
ware-based output signal, RY/BY#, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 6 shows the Data# Polling algorithm. Figure 19
in the AC Characteristics section shows the Data#
Polling timing diagram.
Figure 6. Data# Polling Algorithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
February 26, 2009 Am29LV065D 31
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or the device is in the erase-suspend-read
mode.
Ta b l e 1 1 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 7 shows the toggle bit algorithm. Figure 20 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 21 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
Figure 7. Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
32 Am29LV065D February 26, 2009
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare out-
puts for DQ2 and DQ6.
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if the device was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 11 shows the status of DQ3 relative to the other
status bits.
February 26, 2009 Am29LV065D 33
Table 11. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Status
DQ7
(Note 2) DQ6
DQ5
(Note 1) DQ3
DQ2
(Note 2) RY/BY#
Standard
Mode
Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
34 Am29LV065D February 26, 2009
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +5.5 V
A9, OE#, ACC, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 8. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 9.
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 8. Maximum DC input
voltage on pin A9, OE#, ACC, and RESET# is +12.5 V
which may overshoot to +14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0–3.6 V
VIO . . . . . . . . . . . . . . . . .either 1.8–2.9 V or 3.0–5.0 V
(see Ordering Information section)
Operating ranges define those limits between which the
functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 8. Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 9. Maximum Positive
Overshoot Waveform
February 26, 2009 Am29LV065D 35
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
5. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. If VIO > VCC,
maximum VIL for CE# and DQ VOS is 0.8 V; minimum VIH for CE# and DQ I/Os is 0.7 V10-. Maximum VIH for these connections is
VIO + 0.3 V.
6. Not 100% tested.
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max
±1.0 µA
ICC1
VCC Active Read Current
(Notes 1, 2) CE# = VIL, OE# = VIH
5 MHz 9 16 mA
1 MHz 2 4
ICC2 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 26 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA
VIL Input Low Voltage (Note 5) –0.5 0.8 V
VIH Input High Voltage (Note 5) 0.7 x VCC VCC + 0.3 V
VHH
Voltage for ACC Program
Acceleration VCC = 3.0 V ± 10% 11.5 12.5 V
VID
Voltage for Autoselect and Temporary
Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.8 VIO V
VOH2 IOH = –100 µA, VCC = VCC min V
IO–0.4 V
VLKO Low VCC Lock-Out Voltage (Note 6) 2.3 2.5 V
36 Am29LV065D February 26, 2009
DC CHARACTERISTICS
Zero-Power Flash
Note: Addresses are switching at 1 MHz
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
0
0 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
10
8
2
0
1 2345
Frequency in MHz
Supply Current in mA
Note: T = 25 °C
Figure 11. Typical ICC1 vs. Frequency
4
6
12
3.0 V
3.6 V
February 26, 2009 Am29LV065D 37
TEST CONDITIONS
Table 12. Test Specifications
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Te s t
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
Test Condition
90R,
101R
120R,
121R Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 30 100 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement
reference levels (See Note) 1.5 V
Output timing measurement
reference levels 0.5 VIO V
3.0 V
0.0 V
1.5 V 0.5 VIO V OutputMeasurement LevelInput
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 13. Input Waveforms and Measurement Levels
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
38 Am29LV065D February 26, 2009
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. All test setups assume VIO = VCC.
2. Not 100% tested.
3. See Figure 12 and Table 12 for test specifications.
Parameter
Description
Test Setup
(Note 1)
Speed Options
JEDEC Std. 90R 101R
120R,
121R Unit
tAVAV tRC Read Cycle Time (Note 2) Min 90 100 120 ns
tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 90 100 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 120 ns
tGLQV tOE Output Enable to Output Delay Max 35 35 50 ns
tEHQZ tDF Chip Enable to Output High Z (Note 2) Max 30 30 30 ns
tGHQZ tDF
Output Enable to Output High Z
(Note 2) Max 30 30 30 ns
tAXQX tOH
Output Hold Time From Addresses,
CE# or OE#, Whichever Occurs First Min 0 ns
tOEH
Output Enable
Hold Time (Note 2)
Read Min 0 ns
Toggle and
Data# Polling Min 10 ns
tOH
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
0 V
RY/BY#
RESET#
tDF
Figure 14. Read Operation Timings
February 26, 2009 Am29LV065D 39
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter
Description All Speed Options UnitJEDEC Std
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note) Max 20 µs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 15. Reset Timings
40 Am29LV065D February 26, 2009
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std. Description 90R 101R
120R,
121R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns
tWLAX tAH Address Hold Time Min 45 45 50 ns
tAHT
Address Hold Time From CE# or OE# high
during toggle bit polling Min 0 ns
tDVWH tDS Data Setup Time Min 45 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOEPH Output Enable High during toggle bit polling Min 20 ns
tGHWL tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 35 50 ns
tWHDL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 5 µs
tWHWH1 tWHWH1 Accelerated Byte Programming Operation (Note 2) Typ 4 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.9 sec
tVHH VHH Rise and Fall Time (Note 1) Min 250 ns
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Write Recovery Time from RY/BY# Min 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns
February 26, 2009 Am29LV065D 41
AC CHARACTERISTICS
OE#
WE#
CE#
VCC
Data
Addresses
tDS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
XXXh PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
tBUSY
t
CH
PA
N
ote: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 16. Program Operation Timings
ACC
tVHH
VHH
VIL or VIH VIL or VIH
tVHH
Figure 17. Accelerated Program Timing Diagram
42 Am29LV065D February 26, 2009
AC CHARACTERISTICS
OE#
CE#
Addresses
VCC
WE#
Data
XXXh SA
tAH
tWP
tWC tAS
tWPH
XXXh for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
tRB
tBUSY
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
Figure 18. Chip/Sector Erase Operation Timings
February 26, 2009 Am29LV065D 43
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0–DQ6
RY/BY#
t
BUSY
Complement True
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
t
ACC
t
RC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
44 Am29LV065D February 26, 2009
AC CHARACTERISTICS
OE#
CE#
WE#
Addresses
tOEH
tDH
tAHT
tASO
tOEPH
tOE
Valid Data
(first read) (second read) (stops toggling)
tCEPH
tAHT
tAS
DQ6/DQ2 Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 21. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
February 26, 2009 Am29LV065D 45
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
Parameter
All Speed OptionsJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
tRRB
RESET# Hold Time from RY/BY# High for
Temporary Sector Group Unprotect Min 4 µs
RESET#
tVIDR
VID
VSS, VIL,
or VIH
VID
VSS, VIL,
or VIH
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
tRRB
Figure 22. Temporary Sector Group Unprotect Timing Diagram
46 Am29LV065D February 26, 2009
AC CHARACTERISTICS
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Group Protect or Unprotect Verify
VID
VIH
* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Group Protect and Unprotect Timing Diagram
February 26, 2009 Am29LV065D 47
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std Description 90R 101R 120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 45 50 ns
tDVEH tDS Data Setup Time Min 45 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tGHEL tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 45 45 50 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 11 µs
tWHWH1 tWHWH1 Accelerated Byte Programming Operation (Note 2) Typ 7 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.9 sec
48 Am29LV065D February 26, 2009
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
XXX for program
XXX for erase
PA for program
SA for sector erase
XXX for chip erase
tBUSY
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings
February 26, 2009 Am29LV065D 49
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Ta bl e
10 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.9 15 sec Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 115 sec
Byte Program Time 5 150 µs
Excludes system level
overhead (Note 5)
Accelerated Byte Program Time 4 120 µs
Chip Program Time (Note 3) 42 126 sec
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Parameter Description Test Conditions Min Unit
Minimum Pattern Data Retention Time
150°C10Years
125°C20Years
50 Am29LV065D February 26, 2009
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP)
Dwg rev AA; 10/99
February 26, 2009 Am29LV065D 51
PHYSICAL DIMENSIONS
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
11 x 12 mm package
Dwg rev AF; 10/99
52 Am29LV065D February 26, 2009
REVISION SUMMARY
Revision A (July 27, 2000)
Initial release.
Revision A+1 (August 4, 2000)
Global
Deleted references to the 48-pin reverse TSOP.
Connection Diagrams
Corrected pin 36 on TSOP package to VIO.
Accelerated Program Operation, Unlock Bypass
Command Sequence
Modified caution note regarding ACC input.
Revision A+2 (August 14, 2000)
Ordering Information
Corrected 90 ns entry in VIO column for FBGA.
Revision A+3 (August 25, 2000)
Table 3, Am29LV065D Autoselect Codes,
(High Voltage Method)
Corrected the SecSI Sector Indicator Bit codes from
80h/00h to 90h/10h.
Revision A+4 (October 19, 2000)
Global
Changed data sheet status to “Preliminary.”
Revision A+5 (November 7, 2000)
Ordering Information
Deleted burn-in option.
Revision A+6 (November 27, 2000)
Pin Description, and Table 11, Write Operation
Status
Deleted references to RY/BY# being available only on
the FBGA package. RY/BY# is also available on the
TSOP package.
Revision A+7 (March 8, 2001)
Global
Deleted “Preliminary” status from document.
Table 4, Sector Group Protection/Unprotection
Address Table
Corrected the sector group address bits for sectors
64–127.
Revision B (January 10, 2002)
Global
Added TSR048 package. Clarified description of Ver-
satileIO (VIO) in the following sections: Distinctive
Characteristics; General Description; VersatileIO (VIO)
Control; Operating Ranges; DC Characteristics;
CMOS compatible.
Reduced typical sector erase time from 1.6 s to 0.9 s.
Table 3, Am29LV065D Autoselect Codes,
(High Voltage Method)
Corrected the autoselect code for sector protection
verification.
Sector Group Protection and Unprotection
Deleted reference to previous method of sector protec-
tion and unprotection.
Autoselect Command Sequence
Clarified description of function.
SecSi (Secured Silicon) Sector Flash
Memory Region
Clarified the customer lockable version of this device
can be programmed and protected only once. In Ta b l e
5, changed address range in second row.
DC Characteristics
Changed minimum VOH1 from 0.85VIO to 0.8VIO. De-
leted reference to Note 6 for both VOH1 and VOH2.
Erase and Program Operations table
Corrected to indicate tBUSY specification is a maximum
value.
Erase and Program Performance table
Changed typical sector erase time from 1.6 s to 0.9 s
and typical chip erase time from 205 s to 115 s.
Revision C (March 26, 2004)
SecSi (Secured Silicon) Sector Flash
Memory Region
Modified SecSi Sector protect verify section. Added
algorithm shown in Figure 3.
Common Flash Memory Interface
Modified website for CFI specifications and publica-
tions.
Command Definitions
Modified end of first paragraph to “Writing incorrect
address and data values or writing them in the im-
proper sequence may place the device in an unknown
state. A reset command is required to return the de-
vice to reading array data.”
February 26, 2009 Am29LV065D 53
Byte Program Command Sequence, Chip Erase
Command Sequence, Erase Suspend/Erase
Resume Commands
Added - The Secsi Sector, autoselect, and CFI func-
tions are not available when a program function is in
progress.
DC Characteristics - CMOS Compatible
Removed IACC . Added Note.
Trademarks
Updated.
Command Definitions
Modified Erase Suspend & Erase Resume to XXX.
See Table 10.
Revision C+1 (June 10, 2004)
Ordering Information
Added Pb-free package OPNs.
Revision C2 (February 16, 2006)
Global
Removed Reverse TSOP.
Revision C3 (February 26, 2009)
Global
Added obsolescence information.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2004-2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade-
marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are
for identification purposes only and may be trademarks of their respective companies.
Copyright © 2006–2009 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
ORNAND2™, HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
