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FM25CL64B
64-Kbit (8K × 8) Serial (SPI) F-RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-84477 Rev. *J Revised November 12, 2018
64-Kbit (8K × 8) Serial (SPI) F-RAM
Features
■64-Kbit ferroelectric random access memory (F-RAM) logically
organized as 8K × 8
❐High-endurance 100 trillion (1014) read/writes
❐151-year data retention (See Data Retention and Endurance
on page 12)
❐NoDelay™ writes
❐Advanced high-reliability ferroelectric process
■Very fast serial peripheral interface (SPI)
❐Up to 20 MHz frequency
❐Direct hardware replacement for serial flash and EEPROM
❐Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
■Sophisticated write protection scheme
❐Hardware protection using the Write Protect (WP) pin
❐Software protection using Write Disable instruction
❐Software block protection for 1/4, 1/2, or entire array
■Low power consumption
❐200 A active current at 1 MHz
❐3 A (typ) standby current
■Low-voltage operation: VDD = 2.7 V to 3.65 V
■Industrial temperature: –40 C to +85 C
■Packages
❐8-pin small outline integrated circuit (SOIC) package
❐8-pin thin dual flat no leads (DFN) package
■Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM25CL64B is a 64-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system level
reliability problems caused by serial flash, EEPROM, and other
nonvolatile memories.
Unlike serial flash and EEPROM, the FM25CL64B performs
write operations at bus speed. No write delays are incurred. Data
is written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endurance compared with other
nonvolatile memories. The FM25CL64B is capable of supporting
1014 read/write cycles, or 100 million times more write cycles
than EEPROM.
These capabilities make the FM25CL64B ideal for nonvolatile
memory applications requiring frequent or rapid writes.
Examples range from data collection, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
The FM25CL64B provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
FM25CL64B uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The device
specifications are guaranteed over an industrial temperature
range of –40 C to +85 C.
For a complete list of related documentation, click here.
Instruction Decoder
Clock Generator
Control Logic
Write Protect
Instruction Register
Address Register
Counter
8 K x 8
F-RAM Array
13
Data I/ O Register
8
Nonvolatile Status
Register
3
WP
CS
HOLD
SCK
SOSI
Logic Block Diagram
FM25CL64B
Document Number: 001-84477 Rev. *J Page 2 of 22
Contents
Pinouts ..............................................................................3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Memory Architecture ........................................................ 4
Serial Peripheral Interface – SPI Bus .............................. 4
SPI Overview ............................................................... 4
SPI Modes ................................................................... 5
Power Up to First Access ............................................ 6
Command Structure .................................................... 6
WREN - Set Write Enable Latch ................................. 6
WRDI - Reset Write Enable Latch ...............................6
Status Register and Write Protection ............................. 6
RDSR - Read Status Register ..................................... 7
WRSR - Write Status Register .................................... 7
Memory Operation ............................................................ 8
Write Operation ........................................................... 8
Read Operation ........................................................... 8
HOLD Pin Operation ................................................... 9
Endurance ................................................................. 10
Maximum Ratings ........................................................... 11
Operating Range ............................................................. 11
DC Electrical Characteristics ........................................ 11
Data Retention and Endurance ..................................... 12
Capacitance .................................................................... 12
Thermal Resistance ........................................................ 12
AC Test Conditions ........................................................ 12
AC Switching Characteristics ....................................... 13
Power Cycle Timing ....................................................... 15
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
FM25CL64B
Document Number: 001-84477 Rev. *J Page 3 of 22
Pinouts
Figure 1. 8-pin SOIC pinout
Figure 2. 8-pin DFN pinout
HOLD
SCK
1
2
3
4 5
CS 8
7
6
VDD
SI
SO
Top View
not to scale
V
SS
WP
SO
CS
V
SS
WP
SI
VDD
SCK
HOLD
1
2
45
6
7
8
3
O
PAD
EXPOSED
Top View
not to scale
Pin Definitions
Pin Name I/O Type Description
CS Input Chip Select. This active LOW input activates the device. When HIGH, the device enters
low-power standby mode, ignores other inputs, and tristates the output. When LOW, the device
internally activates the SCK signal. A falling edge on CS must occur before every opcode.
SCK Input Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising
edge and outputs occur on the falling edge. Because the device is synchronous, the clock
frequency may be any value between 0 and 20 MHz and may be interrupted at any time.
SI[1] Input Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of
SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD
specifications.
SO[1] Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all
other times including when HOLD is LOW. Data transitions are driven on the falling edge of the
serial clock.
WP Input Write Protect. This active LOW pin prevents write operation to the Status Register when WPEN
is set to ‘1’. This is critical because other write protection features are controlled through the
Status Register. A complete explanation of write protection is provided in Status Register and
Write Protection on page 7. This pin must be tied to VDD if not used.
HOLD Input HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for
another task. When HOLD is LOW, the current operation is suspended. The device ignores any
transition on SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin must
be tied to VDD if not used.
VSS Power supply Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
EXPOSED PAD No connect The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. The
EXPOSED PAD should not be soldered on the PCB.
Note
1. SI may be connected to SO for a single pin data interface.
FM25CL64B
Document Number: 001-84477 Rev. *J Page 4 of 22
Functional Overview
The FM25CL64B is a serial F-RAM memory. The memory array
is logically organized as 8,192 × 8 bits and is accessed using an
industry standard serial peripheral interface (SPI) bus. The
functional operation of the F-RAM is similar to serial flash and
serial EEPROMs. The major difference between the
FM25CL64B and a serial flash or EEPROM with the same pinout
is the F-RAM's superior write performance, high endurance, and
low power consumption.
Memory Architecture
When accessing the FM25CL64B, the user addresses 8K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the SPI
protocol, which includes a chip select (to permit multiple devices
on the bus), an opcode, and a two-byte address. The upper 3 bits
of the address range are ‘don’t care’ values. The complete
address of 13 bits specifies each byte address uniquely.
Most functions of the FM25CL64B are either controlled by the
SPI interface or handled by on-board circuitry. The access time
for the memory operation is essentially zero, beyond the time
needed for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike a serial flash or
EEPROM, it is not necessary to poll the device for a ready
condition because writes occur at bus speed. By the time a new
bus transaction can be shifted into the device, a write operation
is complete. This is explained in more detail in the interface
section.
Note The FM25CL64B contains no power management circuits
other than a simple internal power-on reset circuit. It is the user's
responsibility to ensure that VDD is within datasheet tolerances
to prevent incorrect operation. It is recommended that the part is
not powered down with chip enable active.
Serial Peripheral Interface – SPI Bus
The FM25CL64B is a SPI slave device and operates at speeds
up to 20 MHz. This high-speed serial bus provides
high-performance serial communication to a SPI master. Many
common microcontrollers have hardware SPI ports allowing a
direct interface. It is quite simple to emulate the port using
ordinary port pins for microcontrollers that do not. The
FM25CL64B operates in SPI Mode 0 and 3.
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
The SPI is a synchronous serial interface, which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on the SPI bus is activated using the CS
pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both of these modes, data is clocked into the F-RAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated, the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms in the SPI protocol are as follows:
SPI Master
The SPI master device controls the operations on a SPI bus. An
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
of the operations must be initiated by the master activating a
slave device by pulling the CS pin of the slave LOW. The master
also generates the SCK and all the data transmission on SI and
SO lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. An SPI slave never initiates a communication on the SPI
bus and acts only on the instruction from the master.
The FM25CL64B operates as an SPI slave and may share the
SPI bus with other SPI slave devices.
Chip Select (CS)
To select any slave device, the master needs to pull down the
corresponding CS pin. Any instruction can be issued to a slave
device only while the CS pin is LOW. When the device is not
selected, data through the SI pin is ignored and the serial output
pin (SO) remains in a high-impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Serial Clock (SCK)
The Serial Clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
The FM25CL64B enables SPI modes 0 and 3 for data
communication. In both of these modes, the inputs are latched
by the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of a SPI instruction on
the SI pin. Further, all data inputs and outputs are synchronized
with SCK.
Data Transmission (SI/SO)
The SPI data bus consists of two lines, SI and SO, for serial data
communication. SI is also referred to as Master Out Slave In
(MOSI) and SO is referred to as Master In Slave Out (MISO). The
master issues instructions to the slave through the SI pin, while
FM25CL64B
Document Number: 001-84477 Rev. *J Page 5 of 22
the slave responds through the SO pin. Multiple slave devices
may share the SI and SO lines as described earlier.
The FM25CL64B has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 3.
For a microcontroller that has no dedicated SPI bus, a
general-purpose port may be used. To reduce hardware
resources on the controller, it is possible to connect the two data
pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.
Figure 4 shows such a configuration, which uses only three pins.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 64-Kbit serial F-RAM requires a 2-byte address for any read
or write operation. Because the address is only 13 bits, the first
three bits which are fed in are ignored by the device. Although
these three bits are ‘don’t care’, Cypress recommends that these
bits be set to 0s to enable seamless transition to higher memory
densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
FM25CL64B uses the standard opcodes for memory accesses.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS, and the SO pin remains tristated.
Status Register
FM25CL64B has an 8-bit Status Register. The bits in the Status
Register are used to configure the device. These bits are
described in Table 3 on page 7.
SPI Modes
FM25CL64B may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■SPI Mode 0 (CPOL = 0, CPHA = 0)
■SPI Mode 3 (CPOL = 1, CPHA = 1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.
Figure 3. System Configuration with SPI port
CS1
CS2
HOLD1
HOLD2
FM25CL64B FM25CL64B
WP1
WP2
SCK SI SO SCK SI SO
CS HOLD WP CS HOLD WP
SCK
MOSI
MISO
SPI
Microcontroller
Figure 4. System Configuration without SPI port
FM25CL64B
Microcontroller
SCK SI SO
CS HOLD WP
P1.2
P1.1
P1.0
FM25CL64B
Document Number: 001-84477 Rev. *J Page 6 of 22
The two SPI modes are shown in Figure 5 and Figure 6. The
status of the clock when the bus master is not transferring data is:
■SCK remains at 0 for Mode 0
■SCK remains at 1 for Mode 3
The device detects the SPI mode from the status of the SCK pin
when the device is selected by bringing the CS pin LOW. If the
SCK pin is LOW when the device is selected, SPI Mode 0 is
assumed and if the SCK pin is HIGH, it works in SPI Mode 3.
Power Up to First Access
The FM25CL64B is not accessible for a tPU time after power up.
Users must comply with the timing parameter tPU, which is the
minimum time from VDD (min) to the first CS LOW.
Command Structure
There are six commands, called opcodes, that can be issued by
the bus master to the FM25CL64B. They are listed in Table 1.
These opcodes control the functions performed by the memory.
WREN - Set Write Enable Latch
The FM25CL64B will power up with writes disabled. The WREN
command must be issued before any write operation. Sending
the WREN opcode allows the user to issue subsequent opcodes
for write operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Sending the WREN opcode causes the internal Write Enable
Latch to be set. A flag bit in the Status Register, called WEL,
indicates the state of the latch. WEL = ‘1’ indicates that writes are
permitted. Attempting to write the WEL bit in the Status Register
has no effect on the state of this bit – only the WREN opcode can
set this bit. The WEL bit will be automatically cleared on the rising
edge of CS following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or the F-RAM
array without another WREN command. Figure 7 illustrates the
WREN command bus configuration.
WRDI - Reset Write Enable Latch
The WRDI command disables all write activity by clearing the
Write Enable Latch. The user can verify that writes are disabled
by reading the WEL bit in the Status Register and verifying that
WEL is equal to ‘0’. Figure 8 illustrates the WRDI command bus
configuration.
Figure 5. SPI Mode 0
Figure 6. SPI Mode 3
Table 1. Opcode commands
Name Description Opcode
WREN Set write enable latch 0000 0110b
WRDI Write disable 0000 0100b
RDSR Read Status Register 0000 0101b
WRSR Write Status Register 0000 0001b
READ Read memory data 0000 0011b
WRITE Write memory data 0000 0010b
LSB
MSB
76543210
CS
SCK
SI
012 3 4 567
Figure 7. WREN Bus Configuration
Figure 8. WRDI Bus Configuration
0 0 0
CS
SCK
SI
SO
HI-Z
0 1 2 3 4 5 6 7
00
001
FM25CL64B
Document Number: 001-84477 Rev. *J Page 7 of 22
Status Register and Write Protection
The write protection features of the FM25CL64B are multi-tiered
and are enabled through the status register. The Status Register
is organized as follows. (The default value shipped from the
factory for bits in the Status Register is ‘0’.)
Bits 0 and 4–6 are fixed at ‘0’; none of these bits can be modified.
Note that bit 0 (“Ready or Write in progress” bit in serial flash and
EEPROM) is unnecessary, as the F-RAM writes in real-time and
is never busy, so it reads out as a ‘0’. The BP1 and BP0 control
the software write-protection features and are nonvolatile bits.
The WEL flag indicates the state of the Write Enable Latch.
Attempting to directly write the WEL bit in the Status Register has
no effect on its state. This bit is internally set and cleared via the
WREN and WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits. They
specify portions of memory that are write-protected as shown in
Table 4.
The BP1 and BP0 bits and the Write Enable Latch are the only
mechanisms that protect the memory from writes. The remaining
write protection features protect inadvertent changes to the block
protect bits.
The write protect enable bit (WPEN) in the Status Register
controls the effect of the hardware write protect (WP) pin. When
the WPEN bit is set to ‘0’, the status of the WP pin is ignored.
When the WPEN bit is set to ‘1’, a LOW on the WP pin inhibits a
write to the Status Register. Thus the Status Register is
write-protected only when WPEN = ‘1’ and WP = ‘0’.
Table 5 summarizes the write protection conditions.
RDSR - Read Status Register
The RDSR command allows the bus master to verify the
contents of the Status Register. Reading the status register
provides information about the current state of the
write-protection features. Following the RDSR opcode, the
FM25CL64B will return one byte with the contents of the Status
Register.
WRSR - Write Status Register
The WRSR command allows the SPI bus master to write into the
Status Register and change the write protect configuration by
setting the WPEN, BP0 and BP1 bits as required. Before issuing
a WRSR command, the WP pin must be HIGH or inactive. Note
that on the FM25CL64B, WP only prevents writing to the Status
Register, not the memory array. Before sending the WRSR
command, the user must send a WREN command to enable
writes. Executing a WRSR command is a write operation and
therefore, clears the Write Enable Latch.
Table 2. Status Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN (0) X (0) X (0) X (0) BP1 (0) BP0 (0) WEL (0) X (0)
Table 3. Status Register Bit Definition
Bit Definition Description
Bit 0 Don’t care This bit is non-writable and always returns ‘0’ upon read.
Bit 1 (WEL) Write Enable Latch WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEL = ‘1’ --> Write enabled
WEL = ‘0’ --> Write disabled
Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details, see Ta b l e 4.
Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details, see Ta b l e 4.
Bit 4–6 Don’t care These bits are non-writable and always return ‘0’ upon read.
Bit 7 (WPEN) Write Protect Enable bit Used to enable the function of Write Protect Pin (WP). For details, see Tabl e 5 .
Table 4. Block Memory Write Protection
BP1 BP0 Protected Address Range
0 0 None
0 1 1800h to 1FFFh (upper 1/4)
1 0 1000h to 1FFFh (upper 1/2)
1 1 0000h to 1FFFh (all)
Table 5. Write Protection
WEL WPEN WP Protected
Blocks
Unprotected
Blocks
Status
Register
0 X X Protected Protected Protected
1 0 X Protected Unprotected Unprotected
1 1 0 Protected Unprotected Protected
1 1 1 Protected Unprotected Unprotected
FM25CL64B
Document Number: 001-84477 Rev. *J Page 8 of 22
Memory Operation
The SPI interface, which is capable of a high clock frequency,
highlights the fast write capability of the F-RAM technology.
Unlike serial flash and EEPROMs, the FM25CL64B can perform
sequential writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory begin with a WREN opcode. The WRITE
opcode is followed by a two-byte address containing the 13-bit
address (A12–A0) of the first data byte to be written into the
memory. The upper three bits of the two-byte address are
ignored. Subsequent bytes are data bytes, which are written
sequentially. Addresses are incremented internally as long as
the bus master continues to issue clocks and keeps CS LOW. If
the last address of 1FFFh is reached, the counter will roll over to
0000h. Data is written MSB first. The rising edge of CS
terminates a write operation. A write operation is shown in
Figure 11 on page 9.
Note When a burst write reaches a protected block address, the
automatic address increment stops and all the subsequent data
bytes received for write will be ignored by the device.
EEPROMs use page buffers to increase their write throughput.
This compensates for the technology’s inherently slow write
operations. F-RAM memories do not have page buffers because
each byte is written to the F-RAM array immediately after it is
clocked in (after the eighth clock). This allows any number of
bytes to be written without page buffer delays.
Note If the power is lost in the middle of the write operation, only
the last completed byte will be written.
Read Operation
After the falling edge of CS, the bus master can issue a READ
opcode. Following the READ command is a two-byte address
containing the 13-bit address (A12–A0) of the first byte of the
read operation. The upper three bits of the address are ignored.
After the opcode and address are issued, the device drives out
the read data on the next eight clocks. The SI input is ignored
during read data bytes. Subsequent bytes are data bytes, which
are read out sequentially. Addresses are incremented internally
as long as the bus master continues to issue clocks and CS is
LOW. If the last address of 1FFFh is reached, the counter will roll
over to 0000h. Data is read MSB first. The rising edge of CS
terminates a read operation and tristates the SO pin. A read
operation is shown in Figure 12 on page 9.
Figure 9. RDSR Bus Configuration
Figure 10. WRSR Bus Configuration (WREN not shown)
CS
SCK
SO
01234567
SI
000001 0 0
1
HI-Z
012345 67
LSB
D0D1D2D3D4D5D6
MSB
D7
Opcode
Data
CS
SCK
SO
01 23 4567
SI
00000001
MSB LSB
D2D3D7
HI-Z
012345 67
Opcode Data
XX
XX
X
FM25CL64B
Document Number: 001-84477 Rev. *J Page 9 of 22
HOLD Pin Operation
The HOLD pin can be used to interrupt a serial operation without
aborting it. If the bus master pulls the HOLD pin LOW while SCK
is LOW, the current operation will pause. Taking the HOLD pin
HIGH while SCK is LOW will resume an operation. The
transitions of HOLD must occur while SCK is LOW, but the SCK
and CS pin can toggle during a hold state.
Figure 11. Memory Write (WREN not shown)
Figure 12. Memory Read
~
~
CS
SCK
SO
01234 5 6 70 7654321 1213141501234567
MSB LSB
Data
D0D1D2D3D4D5D6D7
SI
~
~
Opcode
0000001
X X X A12 A11 A9
0
A10
A8 A3 A1A2 A0
13-bit Address
MSB LSB
HI-Z
~
~
CS
SCK
SO
01 23456 70 7654321 12131415012345 6 7
MSB LSB
Data
SI
~
~
Opcode
0000001
X X X A12 A11 A9
1
A10
A8 A3 A1A2 A0
13-bit Address
MSB LSB
D0D1D2D3D4D5D6D7
HI-Z
Figure 13. HOLD Operation[2]
CS
SCK
HOLD
SO
~
~
~
~
SI VALID IN VALID IN
~
~
~
~
~
~
Note
2. Figure shows HOLD operation for input mode and output mode.
FM25CL64B
Document Number: 001-84477 Rev. *J Page 10 of 22
Endurance
The FM25CL64B devices are capable of being accessed at least
1014 times, reads or writes. An F-RAM memory operates with a
read and restore mechanism. Therefore, an endurance cycle is
applied on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on an array of
rows and columns of 1K rows of 64-bits each. The entire row is
internally accessed once whether a single byte or all eight bytes
are read or written. Each byte in the row is counted only once in
an endurance calculation. Ta b l e 6 shows endurance calculations
for a 64-byte repeating loop, which includes an opcode, a starting
address, and a sequential 64-byte data stream. This causes
each byte to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually unlimited even at a
20 MHz clock rate.
Table 6. Time to Reach Endurance Limit for Repeating
64-byte Loop
SCK Freq
(MHz)
Endurance
Cycles/sec
Endurance
Cycles/year
Years to Reach
Limit
20 37,310 1.18 × 1012 85.1
10 18,660 5.88 × 1011 170.2
5 9,330 2.94 × 1011 340.3
FM25CL64B
Document Number: 001-84477 Rev. *J Page 11 of 22
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS .........–1.0 V to +5.0 V
Input voltage ............. –1.0 V to +5.0 V and VIN < VDD+1.0 V
DC voltage applied to outputs
in High Z state ....................................–0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns)
on any pin to ground potential ............ –2.0 V to VDD + 2.0 V
Package power dissipation capability
(TA = 25 °C) ................................................................. 1.0 W
Surface mount lead soldering temperature
(3 seconds) .............................................................. +260 C
DC output current
(1 output at a time, 1s duration) .................................. 15 mA
Electrostatic Discharge Voltage [3]
Human Body Model (AEC-Q100-002 Rev. E) ................... 2 kV
Charged Device Model (AEC-Q100-011 Rev. B) .............. 500 V
Latch-up current .................................................... > 140 mA
Operating Range
Range Ambient Temperature (TA) VDD
Industrial –40 C to +85 C 2.7 V to 3.65 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [4] Max Unit
VDD Power supply 2.7 3.3 3.65 V
IDD VDD supply current SCK toggling between
VDD – 0.3 V and VSS,
other inputs
VSS or VDD – 0.3 V.
SO = Open.
fSCK = 1 MHz – – 0.2 mA
fSCK = 20 MHz – – 3 mA
ISB VDD standby current CS = VDD. All other inputs VSS or VDD.–36A
ILI Input leakage current VSS < VIN < VDD ––±1A
ILO Output leakage current VSS < VOUT < VDD ––±1A
VIH Input HIGH voltage 0.7 × VDD –V
DD + 0.3 V
VIL Input LOW voltage – 0.3 – 0.3 × VDD V
VOH Output HIGH voltage IOH = –2 mA VDD – 0.8 – – V
VOL Output LOW voltage IOL = 2 mA – – 0.4 V
VHYS[5] Input Hysteresis (CS and SCK
pin)
0.05 × VDD ––V
Notes
3. Electrostatic Discharge voltages specified in the datasheet are the JEDEC standard limits used for qualifying the device. To know the maximum value device passes
for, please refer to the device qualification report available on the website.
4. Typical values are at 25 °C, VDD = VDD(typ). Not 100% tested.
5. This parameter is characterized and not 100% tested.
FM25CL64B
Document Number: 001-84477 Rev. *J Page 12 of 22
AC Test Conditions
Input pulse levels .................................10% and 90% of VDD
Input rise and fall times ...................................................5 ns
Input and output timing reference levels ................0.5 × VDD
Output load capacitance .............................................. 30 pF
Data Retention and Endurance
Parameter Description Test condition Min Max Unit
TDR Data retention TA = 85 C10–Years
TA = 75 C38–
TA = 65 C 151 –
NVCEndurance Over operating temperature 1014 – Cycles
Capacitance
Parameter [6] Description Test Conditions Max Unit
COOutput pin capacitance (SO) TA = 25 C, f = 1 MHz, VDD = VDD(typ) 8 pF
CIInput pin capacitance 6pF
Thermal Resistance
Parameter [6] Description Test Conditions 8-pin SOIC 8-pin DFN Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
148 19 C/W
JC Thermal resistance
(junction to case)
48 30 C/W
Note
6. This parameter is characterized and not 100% tested.
FM25CL64B
Document Number: 001-84477 Rev. *J Page 13 of 22
AC Switching Characteristics
Over the Operating Range
Parameters [7]
Description Min Max Unit
Cypress
Parameter Alt. Parameter
fSCK –SCK Clock frequency 020 MHz
tCH –Clock HIGH time 22 –ns
tCL –Clock LOW time 22 –ns
tCSU tCSS Chip select setup 10 –ns
tCSH tCSH Chip select hold 10 –ns
tOD[8, 9] tHZCS Output disable time –20 ns
tODV tCO Output data valid time –20 ns
tOH –Output hold time 0 – ns
tD–Deselect time 60 –ns
tR[10, 11] –Data in rise time –50 ns
tF[10, 11] –Data in fall time –50 ns
tSU tSD Data setup time 5 – ns
tHtHD Data hold time 5 – ns
tHS tSH HOLD setup time 10 –ns
tHH tHH HOLD hold time 10 –ns
tHZ[8, 9] tHHZ HOLD LOW to HI-Z –20 ns
tLZ[9] tHLZ HOLD HIGH to data active –20 ns
Notes
7. Test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of
the specified IOL/IOH and 30 pF load capacitance shown in AC Test Conditions on page 12.
8. tOD and tHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
9. This parameter is characterized and not 100% tested.
10. Rise and fall times measured between 10% and 90% of waveform.
11. These parameters are guaranteed by design and are not tested.
FM25CL64B
Document Number: 001-84477 Rev. *J Page 14 of 22
Figure 14. Synchronous Data Timing (Mode 0)
Figure 15. HOLD Timing
HI-Z
VALID IN
HI-Z
CS
SCK
SI
SO
tCL
tCH
tCSU
tSU tH
tODV tOH
t
D
tCSH
tOD
VALID IN VALID IN
CS
SCK
HOLD
SO
tHS
tHZ tLZ
tHH
tHS
tHH
~
~
~
~
SI
tSU
VALID IN VALID IN
~
~
~
~
~
~
FM25CL64B
Document Number: 001-84477 Rev. *J Page 15 of 22
Power Cycle Timing
Over the Operating Range
Parameter Description Min Max Unit
tPU Power-up VDD(min) to first access (CS LOW) 1 – ms
tPD Last access (CS HIGH) to power-down (VDD(min)) 0 – µs
tVR [12] VDD power-up ramp rate 30 –µs/V
tVF [12] VDD power-down ramp rate 30 –µs/V
Figure 16. Power Cycle Timing
CS
~
~
~
~
tPU
tVR tVF
VDD
VDD(min)
tPD
VDD(min)
Note
12. Slope measured at any point on VDD waveform.
FM25CL64B
Document Number: 001-84477 Rev. *J Page 16 of 22
Ordering Code Definitions
Ordering Information
Ordering Code Package
Diagram Package Type Operating
Range
FM25CL64B-G 51-85066 8-pin SOIC Industrial
FM25CL64B-GTR 51-85066 8-pin SOIC
FM25CL64B-DG 001-85260 8-pin DFN
FM25CL64B-DGTR 001-85260 8-pin DFN
All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Option: X = blank or TR
blank = Standard; TR = Tape and Reel
Package Type: X = G or DG
G = 8-pin SOIC; DG = 8-pin DFN
Die revision: B
Density: 64 = 64-Kbit
Voltage: CL = 2.7 V to 3.65 V
SPI F-RAM
Cypress
25FM CL 64 B XDG-
FM25CL64B
Document Number: 001-84477 Rev. *J Page 17 of 22
Package Diagrams
Figure 17. 8-pin SOIC (150 Mils) Package Outline, 51-85066
51-85066 *I
FM25CL64B
Document Number: 001-84477 Rev. *J Page 18 of 22
Figure 18. 8-pin DFN (4.0 × 4.5 × 0.8 mm) Package Outline, 001-85260
Package Diagrams (continued)
001-85260 *B
FM25CL64B
Document Number: 001-84477 Rev. *J Page 19 of 22
Acronyms Document Conventions
Units of Measure
Acronym Description
AEC Automotive Electronics Council
CPHA Clock Phase
CPOL Clock Polarity
EEPROM Electrically Erasable Programmable Read-Only
Memory
EIA Electronic Industries Alliance
I/O Input/Output
JEDEC Joint Electron Devices Engineering Council
JESD JEDEC Standards
LSB Least Significant Bit
MSB Most Significant Bit
F-RAM Ferroelectric Random Access Memory
RoHS Restriction of Hazardous Substances
SPI Serial Peripheral Interface
SOIC Small Outline Integrated Circuit
DFN Thin Dual Flat No-lead
Symbol Unit of Measure
°C degree Celsius
Hz hertz
kHz kilohertz
Kkilohm
Kbit kilobit
kV kilovolt
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
ms millisecond
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
FM25CL64B
Document Number: 001-84477 Rev. *J Page 20 of 22
Document History Page
Document Title: FM25CL64B, 64-Kbit (8K × 8) Serial (SPI) F-RAM
Document Number: 001-84477
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 3902952 GVCH 02/25/2013 New data sheet.
*A 3924523 GVCH 03/07/2013 Updated Power Cycle Timing:
Changed minimum value of tPU parameter from 10 ms to 1 ms.
*B 4014247 GVCH 05/29/2013 Updated SOIC package marking scheme.
Added Appendix A - Errata for FM25CL64B.
*C 4045438 GVCH 06/30/2013 All errata items are fixed and the errata is removed.
*D 4223057 GVCH 01/23/2014 Updated Pinouts:
Updated Figure 2 (Added EXPOSED PAD details).
Updated Pin Definitions:
Added EXPOSED PAD pin and its corresponding details.
Updated Maximum Ratings:
Added “Maximum Junction Temperature” and its corresponding details.
Added “DC voltage applied to outputs in High-Z state” and its corresponding
details.
Added “Transient voltage (< 20 ns) on any pin to ground potential” and its
corresponding details.
Added “Package power dissipation capability (TA = 25 °C)” and its
corresponding details.
Added “DC output current (1 output at a time, 1s duration)” and its
corresponding details.
Added “Latch-up Current” and its corresponding details.
Removed “Package Moisture Sensitivity Level” and its corresponding details.
Updated Data Retention and Endurance:
Removed details of TDR parameter corresponding to “TA = +80 °C”.
Added details of TDR parameter corresponding to “TA = 65 °C”.
Added NVC parameter and its details.
Added Thermal Resistance.
Updated Package Diagrams:
Removed Package Marking Scheme (top mark).
Removed “Ramtron Revision History”.
Updated to Cypress template.
Completing Sunset Review.
*E 4563141 GVCH 11/06/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*F 4782808 GVCH 06/05/2015 Replaced “TDFN” with “DFN” in all instances across the document.
Updated Pin Definitions:
Updated details in “Description” column of “EXPOSED PAD” pin.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *F to *G.
spec 001-85260 – Changed revision from *A to *B.
Updated to new template.
*G 4878788 ZSK / PSR 08/10/2015 Updated Maximum Ratings:
Removed “Maximum junction temperature” and its corresponding details.
Added “Maximum accumulated storage time” and its corresponding details.
Added “Ambient temperature with power applied” and its corresponding
details.
FM25CL64B
Document Number: 001-84477 Rev. *J Page 21 of 22
*H 5606837 GVCH 01/27/2017 Updated Maximum Ratings:
Updated Electrostatic Discharge Voltage (in compliance with AEC-Q100
standard):
Changed value of “Human Body Model” from 4 kV to 2 kV.
Changed value of “Charged Device Model” from 1.25 kV to 500 V.
Removed “Machine Model” related information.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *G to *H.
Updated to new template.
Completing Sunset Review.
*I 5703890 GVCH 04/20/2017 Updated Maximum Ratings:
Added Note 3 and referred the same note in “Electrostatic Discharge Voltage”.
Updated to new template.
*J 6237906 GVCH 11/12/2018 Updated Maximum Ratings:
Replaced “–55 °C to +125 °C” with “–65 °C to +125 °C” in ratings corresponding
to “Storage temperature”.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *H to *I.
Updated to new template.
Document History Page (continued)
Document Title: FM25CL64B, 64-Kbit (8K × 8) Serial (SPI) F-RAM
Document Number: 001-84477
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 001-84477 Rev. *J Revised November 12, 2018 Page 22 of 22
FM25CL64B
© Cypress Semiconductor Corporation, 2013–2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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