SN54ABT377, SN74ABT377A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156E – FEBRUAR Y 1991 – REVISED JANUAR Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
description
These 8-bit positive-edge-triggered D-type
flip-flops with a clock (CLK) input are particularly
suitable for implementing buffer and storage
registers, shift registers, and pattern generators.
Data (D) input information that meets the setup
time requirements is transferred to the Q outputs
on the positive-going edge of the clock pulse if the
common clock-enable (CLKEN) input is low.
Clock triggering occurs at a particular voltage
level and is not directly related to the transition
time of the positive-going pulse. When the
buffered clock (CLK) input is at either the high or
low level, the D-input signal has no effect at the
output. The circuits are designed to prevent false
clocking by transitions at CLKEN.
The SN54ABT377 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT377A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
CLKEN CLK DQ
H X X Q0
L↑HH
L↑LL
XH or L X Q0
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
SN54ABT377 ...J OR W PACKAGE
SN74ABT377A . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
SN54ABT377 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLKEN
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
1D
1Q
CLKEN
5Q
5D 8Q
4Q
GND
CLK VCC
8D
7D
7Q
6Q
6D
SN54ABT377, SN74ABT377A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156E – FEBRUAR Y 1991 – REVISED JANUAR Y 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
2D
3
1D 4
2D 7
3D
G1
1
1Q
2
2Q
5
3Q
6
8
4D 13
5D 14
6D
4Q
9
5Q
12
6Q
15
CLKEN
17
7D 18
8D
11
CLK
7Q
16
8Q
19
1C2
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1D
1Q
1D
C1
CLK
CLKEN
To Seven Other Channels
11
1
3
2
SN54ABT377, SN74ABT377A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156E – FEBRUAR Y 1991 – REVISED JANUAR Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT377 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT377A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT377 SN74ABT377A
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 5 5 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
SN54ABT377, SN74ABT377A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156E – FEBRUAR Y 1991 – REVISED JANUAR Y 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54ABT377 SN74ABT377A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VOH
VCC = 5 V, IOH = –3 mA 3 3 3
V
V
OH
VCC =45V
IOH = –24 mA 2 2
V
V
CC =
4
.
5
V
IOH = –32 mA 2* 2
VOL
VCC =45V
IOL = 48 mA 0.55 0.55
V
V
OL
V
CC =
4
.
5
V
IOL = 64 mA 0.55* 0.55
V
Vhys 100 mV
IIVCC = 5.5 V, VI = VCC or GND ±1±1±1µA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
IO‡VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
ICC
V
CC
= 5.5 V, I
O
= 0, Outputs high 1 250 250 250 µA
I
CC
CC ,O,
VI = VCC or GND Outputs low 24 30 30 30 mA
∆ICC§VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND 1.5 1.5 1.5 mA
CiVI = 2.5 V or 0.5 V 3.5 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†All typical values are at VCC = 5 V.
‡Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT377
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
fclock Clock frequency 0 150 0 150 MHz
twPulse duration CLK high or low 3.3 3.3 ns
tsu
Setu
p
time before CLK↑
Data high or low 2 2.5
ns
t
su
Setup
time
before
CLK↑
CLKEN high or low 3 3
ns
th
Hold time after CLK↑
Data high or low 1.81.8
ns
t
h
H
o
ld
ti
me a
ft
er
CLK↑
CLKEN high or low 1.81.8
ns
This data sheet limit may vary among suppliers.
SN54ABT377, SN74ABT377A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156E – FEBRUAR Y 1991 – REVISED JANUAR Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT377A
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
fclock Clock frequency 0 150 0 150 MHz
twPulse duration CLK high or low 3.3 3.3 ns
tsu
Setu
p
time before CLK↑
Data high or low 2 2.5
ns
t
su
Setup
time
before
CLK↑
CLKEN high or low 3 3
ns
th
Hold time after CLK↑
Data high or low 1.8†1.8†
ns
t
h
H
o
ld
ti
me a
ft
er
CLK↑
CLKEN high or low 1.2†1.2†
ns
†This data sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT377
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
fmax 150 150 MHz
tPLH
CLK
Q
2.2 4.5 6 2.2 7
ns
tPHL
CLK
Q
3.1 5.3 6.8 2 7.6
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT377A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
fmax 150 150 MHz
tPLH
CLK
Q
2.2 4.5 6 2.2 6.5
ns
tPHL
CLK
Q
2.6†5.3 6.8 2.6†7.3
ns
†This data sheet limit may vary among suppliers.
SN54ABT377, SN74ABT377A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCBS156E – FEBRUAR Y 1991 – REVISED JANUAR Y 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
Output
Control
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 . 5 n s, t f≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 21-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9314801Q2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 5962-
9314801Q2A
SNJ54ABT
377FK
5962-9314801QRA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9314801QR
A
SNJ54ABT377J
SN74ABT377ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AB377A
SN74ABT377ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT377A
SN74ABT377ADWE4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT377A
SN74ABT377ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT377A
SN74ABT377AN ACTIVE PDIP N 20 20 RoHS &
Non-Green NIPDAU N / A for Pkg Type -40 to 85 SN74ABT377AN
SN74ABT377ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT377A
SN74ABT377APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AB377A
SN74ABT377APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AB377A
SNJ54ABT377FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 5962-
9314801Q2A
SNJ54ABT
377FK
SNJ54ABT377J ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9314801QR
A
SNJ54ABT377J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 21-Jan-2021
Addendum-Page 2
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ABT377ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74ABT377ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74ABT377ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74ABT377APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ABT377ADBR SSOP DB 20 2000 853.0 449.0 35.0
SN74ABT377ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN74ABT377ANSR SO NS 20 2000 367.0 367.0 45.0
SN74ABT377APWR TSSOP PW 20 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.38
0.22
8.2
7.4 TYP
SEATING
PLANE
0.05 MIN
0.25
GAGE PLANE
0 -8
2 MAX
B5.6
5.0
NOTE 4
A
7.5
6.9
NOTE 3
0.95
0.55
(0.15) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
1
10 11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
A 15
DETAIL A
TYPICAL
SCALE 2.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
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