D1912HKIM 20121015-S00005 No.A2150-1/26
Semiconductor Components Industries, LLC, 2013
May, 2013 Ver.1.0
http://onsemi.com
LC87FC096A
Overview
The LC87FC096A is an 8-bit microcomputer, integrates a number of hardware features such as 98K-byte flash ROM,
4096-byte RAM, On-chip debugging function, 16-bit timers/cou nter, four 8-bit timers, a 16-bit timer, a base timer
serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block
transmission/reception capabilities), an asyn chronous/synchronous SIO port, two UART ports, a single master
I2C/synchronous SIO interface, an 11-channel A D converter, four PWM channels, a system clock frequency divider,
a infrared remote controller receiver function, and interrupt feature.
Features
Flash ROM
• 100352 × 8 bits
(Address: 00000H to 17FFFH, 1F800H to 1FFFFH)
• Capable of on-board-programing with 2.7 to 3.6V,
of voltage source.
• Block-erasable in 2K byte units
RAM
• 4096 × 9 bits (LC87FC096A)
Package Form
• QIP64E (14×14):
Lead-free and halogen-free type
Ordering number : ENA2150
Package Dimensions
unit : mm (typ)
3159A
SANYO : QIP64E(14X14)
14.0
17.2
14.0
17.2
0.15
0.35
0.8
(2.7)
3.0max
0.1
0.8
(1.0)
116
17
32
3348
49
64
Ordering number : ENA2150
CMOS IC
FROM 98K byte, RAM 4096 byte on-chip
8-bit 1-chip Microcontroller
* This product is licensed from Silico n Storag e Technology, Inc. (USA).
LC87FC096A
No.A2150-2/26
Minimum Bus Cycle
• 83.3ns (12MHz) VDD=2.7 to 3.6V
• 125ns (8MHz) VDD=2.5 to 3.6V
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time
• 250ns (12MHz) VDD=2.7V to 3.6V
• 375ns (8MHz) VDD=2.5V to 3.6V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 46 (P1n, P2n, P3n, P70 to P73, P80 to P86, PCn,
PWM2, PWM3, XT2)
Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
• Normal withstand voltage input port 1 (XT1)
• Dedicated oscillator ports 2 (CF1, CF2)
• Reset pins 1 (RES)
• Power pins 6(VSS1 to 3, VDD1 to 3)
Timers
• Timer 0:16-bit timer/counter with a capture register
Mode 0:8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 cha nnel s
Mode 1:8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2:16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3:16-bit counter (with a 16-bit capture register)
• Timer 1:16-bit timer/counter that supports PWM/toggle outputs
Mode 0:8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1:8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2:16-bi t t imer/counter wit h a n 8- bi t prescaler (wi t h t og gl e outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3:16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM)
• Timer 4:8-bit timer with a 6-bit prescaler
• Timer 5:8-bit timer with a 6-bit prescaler
• Timer 6:8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7:8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer A:16-bit timer
Mode 0:8-bit timer with an 8-bit prog rammab le prescaler × 2-channels
Mode 1:16-bit timer with an 8-bit programmable prescaler
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time sche mes
High-Speed C l ock C ount e r
• Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz)
• Can generate output real-time
LC87FC096A
No.A2150-3/26
SIO
• SIO0:8-bit Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1:8-bit asynchronous /synchronous serial interface
Mode 0:Synchronous 8-bit serial I/O (2- or 3-w ire configuration, 2 to 512 tCYC transfer clocks)
Mode 1:Asynchronous serial I/ O (half-duplex, 8 dat a bi t s, 1 sto p bit , 8 to 204 8 tC YC ba u drat es)
Mode 2:Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3:Bus mode 2 (start detect, 8 data bits, stop detect)
• SMIIC0:Single master I2C/8-bit synchronous SIO
Mode 0:Single-master mode communication
Mode 1:Synchronous 8-bit serial I/O (MSB first)
UART: 2 cha nnel s
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in co ntinuous data transmission)
• Built-in baudrate generator (with ba udrates of 16/3 to 8192/3 tCYC)
AD Converter: 12 bits × 11 channels
PWM: Multifrequency 12-bit PWM × 4-channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
• The noise filtering function is available for the INT3, T0IN, or T0HCP signa l at P73. When P73 is read with an
instruction, the signal leve l at that pin is read regardless of the availability of the noise filtering function.
Infrared Remote Controller Receiver Circuit
• Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is
selected as the reference clock source)
• Supports data encording systems such as PPM (Pulse Position Modulation) and Manchester encording
• X’tal HOLD mode release function
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Functio n
• Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
• Able to output oscillation clock of sub clock.
LC87FC096A
No.A2150-4/26
Interrupts
• 31 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No. Vector Address Level Interrupt Source
1 00003H X or L INT0
2 0000BH X or L INT1
3 00013H H or L INT2/T0L/INT4/TAL/Infrared remote control receiver
4 0001BH H or L INT3/INT5/base timer0/base timer1
5 00023H H or L T0H/INT6/TAH
6 0002BH H or L T1L/T1H/INT7/SMIIC0
7 00033H H or L SIO0/UART1 receive/ UART2 receive
8 0003BH H or L SIO1/UART1 transmit/ UART2 transmit
9 00043H H or L ADC/T6/T7
10 0004BH H or L Port 0/T4/T5/PWM2, PWM3/RMPWM
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 2048 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits (5 tCYC execution time)
• 24 bits × 16 bits (12 tCYC execution time)
• 16 bits ÷ 8 bits (8 tCYC execution time)
• 24 bits ÷ 16 bits (12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal): For system clock
• CF oscillation circuit: For system clock, with internal Rf
• Crystal oscillation circuit: For low-speed system clock
System Cl ock Divi der Function
• Can run on low current.
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and
64.0μs (at a main clock rate of 12MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
Continued on next page.
LC87FC096A
No.A2150-5/26
Continued from preceding page.
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base
timer and infrared remote controller receiver circuit.
1) The CF and RC oscillators automatically s top operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the infrared remote controller receiver circuit
On-chip Debugger Function
• Permits software debugging with the test device installed on the target board.
Development Tools
• On-chip debugger: TCB87-TypeC (3wir e v ersion) + LC87FC096A
Programming Boards
Package Programming boards
QIP64E W87F50256Q
Flash ROM Programmer
Maker Model Supported version Device
Our company SKK/SKK Type-B/SKK DBG Type-B
(SANYO FWS)
Application Version:
After 1.08
Chip Data Version:
After 2.42
LC87FC096
LC87FC096A
No.A2150-6/26
Pin Assignment
QIP64E (14×14) “Lead-free and halogen-free type”
LC87FC096A
Top view
P83/AN3
P84/AN4
P85/AN5
P86/AN6
PC0/SM0CK
PC1/SM0DA
PC2/SM0DO
PC3/RMPWM0
PC4/RMPWM1
PC5/DBGP0
PC6DBGP1
PC7/DBGP2
VDD3
VSS3
P30
P31
P32/UTX1
P33/URX1
P34/UTX2
P35/URX2
P36
P37
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN/INT7
P23INT4/T1IN
P22/INT4/T1IN
P21/INT4/T1IN
P20/INT4/T1IN/INT6
P07/T7O
P06/T6O
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/NKIN
P73/INT3/T0IN/RMIN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
PWM2
PWM3
VDD2
VSS2
P00
P01
P02
P03
P04
P05/CKO
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4
8
47 4
6
4
5
44 4
3
42 4
0
39
38
3
7
36
35
3
4
33
12 3 4 5 6 7 8 9 10 11 12 13 14 15 16
41
LC87FC096A
No.A2150-7/26
System Block Diagram
Interrupt control
Standby control
IR PLA
Bus interface
Port 0
Port 1
SIO0
SIO1
Timer 0
Timer 1
Timer 4
Timer 5
Port 2
Port 7
Port 8
ADC
ALU
Flash ROM
PC
ACC
B register
C register
PSW
RAR
RAM
Stack pointer
Watchdog timer
PWM2/3
UART1
Base timer
Timer 6 INT0 to INT7
Noise filter
Timer 7 Port 3
Port C
UART2 On-chip Debugger
CF
RC
X’tal
Clock
generator
SMIIC0
Timer A
Remote control
receiver circuit
RMPWM
LC87FC096A
No.A2150-8/26
Pin Description
Pin Name I/O Description Option
VSS1, VSS2, VSS3 - - Power supply pin No
VDD1, VDD2, VDD3 - + Power supply pin No
Port 0 I/O • 8-bit I/O port
• I/O specifiable in 4-bit units
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Shared Pins
P05 : Clock output (system clock / can selected from sub clock)
P06 : Timer 6 toggle output
P07 : Timer 7 toggle output
Yes
P00 to P07
Port 1 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10 : SIO0 data output
P11 : SIO0 data input/bus I/O
P12 : SIO0 clock I/O
P13 : SIO1 data output
P14 : SIO1 data input/bus I/O
P15 : SIO1 clock I/O
P16 : Timer 1 PWML output
P17 : Timer 1 PWMH output/beeper output
Yes
P10 to P17
Port 2 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Yes
P20 to P27
Rising Falling
Rising/
Falling H level L level
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Continued on next page.
LC87FC096A
No.A2150-9/26
Continued from preceding page.
Pin Name I/O Description Option
Port 7 I/O • 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Shared pins
P70 : INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71 : INT1 input/HOLD reset input/timer 0H capture input
P72 : INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73 : INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
remote control receiver input
AD converter input port: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
No
P70 to P73
Rising Falling
Rising/
Falling H level L level
INT0 enable enable disable enable enable
INT1 enable enable disable enable enable
INT2 enable enable enable disable disable
INT3 enable enable enable disable disable
Port 8 I/O • 7-bit I/O port
• I/O specifiable in 1-bit units
• Shared pins
AD converter input port : AN0 (P80) to AN6 (P86)
No
P80 to P86
PWM2
PWM3 I/O • PWM2 and PWM3 output ports
• General-purpose I/O available No
Port 3 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Yes
P30 to P37
Port C I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
PC0: SMIIC0 clock input/output
PC1: SMIIC0 bus input/output/data input
PC2: SMIIC0 data output (used in 3-wire SIO mode)
PC3: RMPWM0 output
PC4: RMPWM1 output
PC5: DBGP0
PC6: DBGP1
PC7: DBGP2
DBGP0 to DBGP2: On-chip Debugger
Yes
PC0 to PC7
RES Input Reset pin No
XT1 Input • 32.768kHz crystal oscillator input pin
• Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to VDD1 if not to be used.
No
XT2 I/O • 32.768kHz crystal oscillator output pin
• Shared pins
General-purpose I/O port
AD converter input port : AN11
Must be set for oscillation and kept open if not to be used.
No
CF1 Input Ceramic resonator input pin No
CF2 Output Ceramic resonator output pin No
LC87FC096A
No.A2150-10/26
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name Option Selected
in Units of Option Type Output Type Pull-up Resistor
P00 to P07 1 bit 1 CMOS Programmable (Note 1)
2 Nch-open drain No
P10 to P17 1 bit 1 CMOS Programmable
2 Nch-open drain Programmable
P20 to P27 1 bit 1 CMOS Programmable
2 Nch-open drain Programmable
P70 - No Nch-open drain Programmable
P71 to P73 - No CMOS Programmable
P80 to P86 - No Nch-open drain No
PWM2, PW M3 - No CMOS No
P30 to P37
1 bit 1 CMOS Programmable
2 Nch-open drain Programmable
PC0 to PC7 1 bit 1 CMOS Programmable
2 Nch-open drain Programmable
XT1 - No Input for 32.768kHz crystal oscillator (Input only) No
XT2 - No Output for 32.768kHz crystal oscillator
(Nch-open drain when in general-purpose output
mode)
No
Note 1:Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the bac ku p ti me.
Be sure to electrically short the VSS1, VSS2 and VSS3 pins.
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
LSI
Power
Supply
VSS1V
SS2VSS3
VDD3
VDD2
VDD1
Power
Supply
VDD3
VDD2
VDD1
LSI
VSS1V
SS2V
SS3
Back-up
capacitor
Back-up
capacitor
LC87FC096A
No.A2150-11/26
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter Symbol Pin/Remarks Conditions Specification
VDD [V] min typ max unit
Maximum supply
voltage VDD max VDD 1, VDD2, VDD3V
DD1=VDD2=VDD3 -0.3 +4.6
V
Input voltage VI(1) XT1, CF1 -0.3
VDD+0.3
Input/output voltage VIO(1) Ports 0, 1, 2
Ports 7, 8
Ports 3, C
PWM2, PWM3, XT2
-0.3
VDD+0.3
High level output current
Peak output
current IOPH(1) Ports 0, 1, 2
Ports 3, C CMOS output select
Per 1 applicable pin -7.5
mA
IOPH(2) PWM2, PWM3 Per 1 applicable pin -12.5
IOPH(3) P71 to P73 Per 1 applicable pin -4.5
Mean output
current
(Note 1-1)
IOMH(1) Ports 0, 1, 2
Ports 3, C CMOS output select
Per 1 applicable pin -5
IOMH(2) PWM2, PWM3 Per 1 applicable pin -10
IOMH(3) P71 to P73 Per 1 applicable pin -3
Total output
current
ΣIOAH(1) P71 to P73 Total of all applicable pins -10
ΣIOAH(2) Port 1
PWM2, PWM3 Total of all applicable pins -15
ΣIOAH(3) Ports 0, 2 Total of all applicable pins -15
ΣIOAH(4) Ports 0, 1, 2
PWM2, PWM3 Total of all applicable pins -30
ΣIOAH(5) Port 3 Total of all applicable pins -15
ΣIOAH(6) Port C Total of all applicable pins -15
ΣIOAH(7) Ports 3, C Total of all applicable pins -30
Low level output current
Peak output
current IOPL(1) P02 to P07
Ports 1, 2
Ports 3, C
PWM2, PWM3
Per 1 applicable pin
10
IOPL(2) P00, P01 Per 1 applicable pin 15
IOPL(3) Ports 7, 8, XT2 Per 1 applicable pin 7.5
Mean output
current
(Note 1-1)
IOML(1) P02 to P07
Ports 1, 2
Ports 3, C
PWM2, PWM3
Per 1 applicable pin
7.5
IOML(2) P00, P01 Per 1 applicable pin 10
IOML(3) Ports 7, 8, XT2 Per 1 applicable pin 5
Total output
current
ΣIOAL(1) Port 7
P83 to P86, XT2 Total of all applicable pins 15
ΣIOAL(2) P80 to P82 Total of all applicable pins 10
ΣIOAL(3) Ports 7, 8, XT2 Total of all applicable pins 25
ΣIOAL(4) Port 1
PWM2, PWM3 Total of all applicable pins 25
ΣIOAL(5) Ports 0, 2 Total of all applicable pins 25
ΣIOAL(6) Ports 0, 1, 2
PWM2, PWM3 Total of all applicable pins 50
ΣIOAL(7) Port 3 Total of all applicable pins 25
ΣIOAL(8) Port C Total of all applicable pins 25
ΣIOAL(9) Ports 3, C Total of all applicable pins 50
Maximum power
dissipation Pdmax QIP64E(14×14) Ta=-40 to +85°C 300 mW
Operating ambient
temperature Topr -40 85
°C
Storage ambient
temperature Tstg -55 125
Note 1-1: The mean output curren t is a mean value measured over 100ms.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Cond itions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
LC87FC096A
No.A2150-12/26
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter Symbol Pin/Remarks Conditions Specification
VDD[V] min typ max unit
Operating
supply voltage
(Note 2-1)
VDD (1) VDD1=VDD2=VDD3 0.245μs ≤ tCYC ≤ 200μs 2.7 3.6
V
0.367μs ≤ tCYC ≤ 200μs 2.5 3.6
Memory
sustaining
supply voltage
VHD V
DD1=VDD2=VDD3 RAM and register contents
sustained in HOLD mode. 2.0 3.6
High level input
voltage VIH(1) Ports 1, 2
P71 to P73
P70 port input
/interrupt side
2.5 to 3.6 0.3VDD
+0.7 V
DD
VIH(2) Ports 0, 8, 3, C
PWM2, PWM3 2.5 to 3.6 0.3VDD
+0.7 V
DD
VIH(3) Port 70 watchdog
timer side 2.5 to 3.6 0.9VDD V
DD
VIH(4) XT1, XT2, CF1,
RES 2.5 to 3.6 0.75VDD V
DD
Low level input
voltage VIL(1) Ports 1, 2
P71 to P73
P70 port input/
interrupt side
2.5 to 3.6 VSS
0.25VDD
VIL(2) Ports 0, 8, 3, C
PWM2, PWM3 2.5 to 3.6 VSS 0.2VDD
VIL(3) Port 70 watchdog
timer side 2.5 to 3.6 VSS
0.8VDD
-1.0
VIL(4)
XT1, XT2, CF1, RES 2.5 to 3.6 VSS
0.25VDD
Instruction cycle
time
(Note 2-2)
tCYC
2.7 to 3.6 0.245 200 μs
2.5 to 3.6 0.367 200
External system
clock frequency FEXCF(1) CF1 • CF2 pin open
• System clock frequency
division rate=1/1
• External system clock
duty=50±5%
2.7 to 3.6 0.1 12
MHz
2.5 to 3.6 0.1 8
• CF2 pin open
• System clock frequency
division rate=1/2
2.7 to 3.6 0.2 24
2.5 to 3.6 0.2 16
Oscillation
frequency range
(Note 2-3)
FmCF(1) CF1, CF2 12MHz ceramic oscillation
See Fig. 1. 2.7 to 3.6 12
MHz
FmCF(2) CF1, CF2 8MHz ceramic oscillation
See Fig. 1. 2.5 to 3.6 8
FmRC Internal RC oscillation 2.5 to 3.6 0.3 1.0 2.0
FsX’tal XT1, XT2 32.768kHz crystal oscillation
See Fig. 2. 2.5 to 2.6
32.768
kHz
Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
LC87FC096A
No.A2150-13/26
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter Symbol Pins Conditions Specification
VDD[V] min typ max unit
High level input
current IIH(1) Ports 0, 1, 2
Ports 7, 8
Ports 3, C
RES
PWM2, PWM3
Outp ut disabled
Pull-up resistor off
VIN=VDD
(Including output Tr's off leakage
current)
2.5 to 3.6 1
μA
IIH(2) XT1, XT2 For input port specification
VIN=VDD 2.5 to 3.6 1
IIH(3) CF1 VIN=VDD 2.5 to 3.6 15
Low level input
current IIL(1) P orts 0, 1, 2
Ports 7, 8
Ports 3, C
RES
PWM2, PWM3
Outp ut disabled
Pull-up resistor off
VIN=VSS
(Including output Tr's off leakage
current)
2.5 to 3.6 -1
IIL(2) XT1, XT2 For input port specification
VIN=VSS 2.5 to 3.6 -1
IIL(3) CF1 VIN=VSS 2.5 to 3.6 -15
High level output
voltage VOH(1) Ports 0, 1, 2
Ports 3, C IOH=-0.4mA 3.0 to 3.6 VDD-0.4
V
VOH(2) IOH=-0.2mA 2.5 to 3.6 VDD-0.4
VOH(3) P71 to P73 IOH=-0.4mA 3.0 to 3.6 VDD-0.4
VOH(4) IOH=-0.2mA 2.5 to 3.6 VDD-0.4
VOH(5) PWM2, PWM3 IOH=-1.6mA 3.0 to 3.6 VDD-0.4
VOH(6) IOH=-1mA 2.5 to 3.6 VDD-0.4
Low level output
voltage VOL(1) Ports 0, 1, 2
Ports 3, C
PWM2, PWM3
IOL=1.6mA 3.0 to 3.6 0.4
VOL(2) IOL=1mA 2.5 to 3.6 0.4
VOL(3) Ports 7, 8
XT2 IOL=1.6mA 3.0 to 3.6 0.4
VOL(4) IOL=1mA 2.5 to 3.6 0.4
VOL(5) P00, P01 IOL=5mA 3.0 to 5.5 0.4
VOL(6) IOL=2.5mA 2.2 to 5.5 0.4
Pull-up
resistance Rpu(1) Ports 0, 1, 2, 7
Ports 3, C VOH=0.9VDD 3.0 to 3.6 15 35 80 kΩ
Rpu(2) 2.5 to 3.6 15 35 100
Hysteresis
voltage VHYS RES
Ports 1, 2, 7 2.5 to 3.6 0.1
VDD V
Pin capacitance CP All pins For pins other than that under test:
VIN=VSS
f=1MHz
Ta=25°C
2.5 to 3.6 10 pF
LC87FC096A
No.A2150-14/26
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 =0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Symbol
Pin/
Remarks Conditions Specification
VDD [V] min typ max unit
Serial clock
Input clock
Frequency tSCK(1)
SCK0(P12) See Fig. 6.
2.5 to 3.6
2
tCYC
Low level
pulse width tSCKL(1) 1
High level
pulse width tSCKH(1)
1
tSCKHA(1) • Continuous data
transmission/reception mode
• See Fig. 6.
• (Note 4-1-2)
4
Output clock
Frequency tSCK(2)
SCK0(P12) • CMOS output se le cted
• See Fig. 6.
2.5 to 3.6
4/3
Low level
pulse width tSCKL(2)
1/2 tSCK
High level
pulse width tSCKH(2)
1/2
tSCKHA(2) • Continuous data
transmission/reception mode
• CMOS outpu t se lected
• See Fig. 6.
tSCKH(2)
+2tCYC
tSCKH(2)
+(10/3)
tCYC
tCYC
Serial input
Data setup time
tsDI(1)
SB0(P11),
SI0(P11)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6. 2.5 to 3.6 0.03
μs
Data hold time thDI(1)
2.5 to 3.6 0.03
Seria l output
Input clock
Output delay
time tdD0(1) SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
• (Note 4-1-3) 2.5 to 3.6
(1/3)tCYC
+0.05
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3) 2.5 to 3.6 1tCYC
+0.05
Output clock
tdD0(3)
(Note 4-1-3)
2.5 to 3.6
(1/3)tCYC
+0.15
Note 4-1-1: These specifi cati ons a re theo ret i cal values . Ad d m a rgin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans / rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
LC87FC096A
No.A2150-15/26
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Symbol Pin/Remarks Conditions Specification
VDD [V] min typ max unit
Serial clock
Input clock
Frequency tSCK(3)
SCK1(P15) See Fig. 6.
2.5 to 3.6
2
tCYC
Low level
pulse width tSCKL(3) 1
High level
pulse width tSCKH(3) 1
Output clock
Frequency tSCK(4)
SCK1(P15) • CMOS output selec ted
• See Fig. 6.
2.5 to 3.6
2
Low level
pulse width tSCKL(4) 1/2 tSCK
High level
pulse width tSCKH(4) 1/2
Serial input
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6. 2.5 to 3.6 0.03
μs
Data hold time thDI(2)
2.5 to 3.6 0.03
Seria l output
Output delay time tdD0(4) SO1(P13),
SB1(P14)
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as th e
time to the beginning of
output state change in
open drain output mode.
• See Fig. 6.
2.5 to 3.6
(1/3)tCYC
+0.05
Note 4-2-1: These specifi cati ons a re theo ret i cal values . Ad d m a rgin depending on its use.
LC87FC096A
No.A2150-16/26
3-1. SMIIC0 Simple SIO Mode Input/Output Char acteristics
Parameter Symbol
Applicable
Pin/Remarks Conditions Specification
VDD[V] min typ max unit
Serial clock
Input clock
Period tSCK (4)
SM0CK (PC0) See Fig. 6.
2.5 to 3.6
4/3
tCYC
Low level
pulse width tSCKL (4) 2/3
High level
pulse width tSCKH (4) 2/3
Output clock
Period tSCK (5)
SM0CK (PC0) • CMOS out pu t selected
• See Fig. 6.
2.5 to 3.6
4/3
Low level
pulse width tSCKL (5) 1/2 tSCK
High level
pulse width tSCKH (5) 1/2
Serial input
Data setup time
tsDI (3) SM0DA (PC1) • Specified with respect to
rising edge of SIOCLK
• See Fig. 6. 2.5 to 3.6 0.03
μs
Data hold time
thDI (3) 0.03
Seria l output
Output delay
time tdD0 (5) SM0DO (PC2),
SM0DA (PC1)
• Specified with respect to
falling edge of SIOCLK
• Specified as interval up to
time when output state
starts changing.
• See Fig. 6.
2.5 to 3.6 1/3tCYC
+0.05
Note 4-3-1: These specifi cati ons a re theo ret i cal values . Ad d m a rgin depending on its use.
LC87FC096A
No.A2150-17/26
3-2. SMIIC0 I2C Mode Input/Output Characteristics
Parameter Symbol
Applicable
Pin/Remarks Conditions Specification
VDD[V] Min typ max Unit
Clock
Input clock
Period tSCL
SM0CK (PC0) • See Fi g. 8.
2.5 to 3.6
5
Tfilt
Low level
pulse width tSCLL
2.5
High level
pulse width tSCLH
2
Output clock
Period tSCLx
SM0CK (PC0) • Specified as interval up to
time when output state
starts changing. 2.5 to 3.6
10
Low level
pulse width tSCLLx
1/2 tSCL
High level
pulse width tSCLHx
1/2
SM0CK and SM0DA
pins input spike
suppression time
tsp SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8. 2.5 to 3.6 1 Tfilt
Bus rel e ase time
between start
and stop
Input
tBUF SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
2.5 to 3.6
2.5 Tfilt
Output
tBUFx SM0CK (PC0)
SM0DA (PC1)
• Standard clock mode
• Specified as interval up to
time when output state
starts changing.
5.5
μs
• High-speed clock mode
• Specified as interval up to
time when output state
starts changing.
1.6
Start/restart
condition hold
time
Input
tHD;STA SM0CK (PC0)
SM0DA (PC1)
• When SMIIC register
control bit, SHDS=0
• See Fig. 8.
2.5 to 3.6
2.0
Tfilt
• When SMIIC register
control bit, SHDS=1
• See Fig. 8. 2.5
Output
tHD;STAx SM0CK (PC0)
SM0DA (PC1)
• Standard clock mode
• Specified as interval up to
time when output state
starts changing.
4.1
μs
• High-speed clock mode
• Specified as interval up to
time when output state
starts changing.
1.0
Restart
condition setup
time
Input
tSU;STA SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
2.5 to 3.6
1.0 Tfilt
Output
tSU;STAx SM0CK (PC0)
SM0DA (PC1)
• Standard clock mode
• Specified as interval up to
time when output state
starts changing.
5.5
μs
• High-speed clock mode
• Specified as interval up to
time when output state
starts changing.
1.6
Continued on next page.
LC87FC096A
No.A2150-18/26
Continued from preceding page.
Parameter Symbol
Applicable
Pin/Remarks Conditions Specification
VDD[V] Min typ max Unit
Stop condition
setup time
Input
tSU;STO SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
2.5 to 3.6
1.0 Tfilt
Output
tSU;STOx SM0CK (PC0)
SM0DA (PC1)
• Standard clock mode
• Specified as interval up to time
when output state starts
changing.
4.9
μs
• High-speed clock mode
• Specified as interval up to time
when output state starts
changing.
1.6
Data hold time
Input
tHD;DAT SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
2.5 to 3.6
0
Tfilt
Output
tHD;DATx SM0CK (PC0)
SM0DA (PC1)
• Specified as interval up to time
when output state starts
changing. 1 1.5
Data setup
time
Input
tSU;DAT SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
2.5 to 3.6
1
Tfilt
Output
tSU;DATx SM0CK (PC0)
SM0DA (PC1)
• Specified as interval up to time
when output state starts
changing.
1tSCL-
1.5Tfilt
Note 4-3-2: These specifi cati ons a re theo ret i cal values . Ad d m a rgin depending on its use.
Note 4-3-3: The value of Tfilt is determined by the values of the register SMIC0BRG, b its 7 and 6 (BRP1, BRP0) and
the system clock frequency.
BRP1 BRP0 Tfilt
0 0 (1/3)tCYC×1
0 1 (1/3)tCYC×2
1 0 (1/3)tCYC×3
1 1 (1/3)tCYC×4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250ns Tfilt > 140ns
Note 4-3-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400kHz
LC87FC096A
No.A2150-19/26
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD [V] min typ max unit
High/low level
pulse width tPIH(1)
tPIL(1) INT0(P70), INT1(P71),
INT2(P72), INT4(P20 to P23),
INT5(P24 to P27)
INT6(P20), INT7(P24)
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1
are enabled. 2.5 to 3.6 1
tCYC
tPIH(2)
tPIL(2) INT3(P73) when noise
filter time constant is 1/1
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled. 2.5 to 3.6 2
tPIH(3)
tPIL(3) INT3(P73) when noise
filter time cons tant is 1/32
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled. 2.5 to 3.6 64
tPIH(4)
tPIL(4) INT3(P73) when noise
filter time cons tant is 1/128
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled. 2.5 to 3.6 256
tPIL(5) RES Resetting is enabled. 2.5 to 3.6 200 μs
AD Converter Characteristics at VSS1 = VSS2 = VSS3 = 0V
<12bits AD Converter Mode at Ta = -40°C to +85°C >
Parameter Symbol Pin/Remarks Conditions Specification
VDD[V] min typ max unit
Resolution N AN0(P80) to
AN6(P86),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
2.5 to 3.6 12 bit
Absolute
accuracy ET (Note 6-1)
2.5 to 3.6 ±16 LSB
Conversion time TCAD See Conversion time calculation
formulas. (Note 6-2) 3.0 to 3.6 64 115
μs
2.7 to 3.6 128 230
2.5 to 3.6 256 460
Analog input
voltage range VAIN 2.5 to 3.6 VSS V
DD V
Analog port
input current IAINH(1) analog channel VAIN=VDD 2.5 to 3.6 1 μA
IAINL(1) VAIN=VSS 2.5 to 3.6 -1
<8bits AD Converter Mode at Ta = -40°C to +85°C >
Parameter Symbol Pin/Remarks Conditions Specification
VDD[V] min typ max unit
Resolution N AN0(P80) to
AN6(P86),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
2.5 to 3.6 8 bit
Absolute
accuracy ET (Note 6-1)
2.5 to 3.6 ±1.5 LSB
Conversion
time TCAD See Conversion time calculation
formulas. (Note 6-2) 3.0 to 3.6 39 71
μs
2.7 to 3.6 79 140
2.5 to 3.6 157 280
Analog input
voltage range VAIN 2.5 to 3.6 VSS V
DD V
Analog port
input current IAINH(1) analog channel VAIN=VDD 2.5 to 3.6 1 μA
IAINL(1) VAIN=VSS 2.5 to 3.6 -1
12bits AD Converter Mode: TCAD(Conversion time)= ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode: TCAD(Conversion time)=((32/(AD division ratio) )+2)×(1/3)×tCYC
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channe l.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mod e .
LC87FC096A
No.A2150-20/26
Consumption Current Charac teristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter Symbol
Pins/Rema
rks Conditions Specification
VDD[V] min Typ Max unit
Normal mode
consumption
current
(Note 7-1)
IDDOP(1) VDD1
=VDD2
=VDD3
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
2.7 to 3.6 3.6 9.5
mA
IDDOP(2) • FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
2.5 to 3.6 2.9 7.1
IDDOP(3) • FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
2.5 to 3.6 0.186 0.96
IDDOP(4) • FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
2.5 to 3.6 11.5 58 μA
HALT mode
consumption
current
(Note 7-1)
IDDHALT(1) VDD1
=VDD2
=VDD3
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
2.7 to 3.6 1.5 2.9
mA
IDDHALT(2) • HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
2.5 to 3.6 1 1.8
IDDHALT(3) • HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
2.5 to 3.6 0.067 0.28
Note 7-1: The consumption current value in cludes none of the currents that flow into the output Tr and internal pull-up
resistors Continued on next page.
LC87FC096A
No.A2150-21/26
Continued from preceding page.
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ Max unit
HALT mode
consumption
current
(Note 7-1)
IDDHALT(4) VDD1
=VDD2
=VDD3
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
2.5 to 3.6 7.4 49 μA
HOLD mode
consumption
current
IDDHOLD(1) VDD1 • HOLD mode
• CF1=VDD or open (External clock mode) 2.5 to 3.6 0.04 20
μA
Timer HOLD
mode
consumption
current
IDDHOLD(2) • Timer HOLD mode
• CF1=VDD or open (External clock mode)
• FmX'tal=32.768kHz by crystal oscillation
mode
2.5 to 3.6 5.9 35
Note 7-1: The consumption current value in cludes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] Min Typ Max unit
Onboard
programming
current
IDDFW(1) VDD1 • Without CPU curent 2.7 to 3.6 7 11 mA
Programming
time tFW(1) • 2k byte Erasing 2.7 to 3.6 12 15 ms
tFW(2) • 2 byte Programming 2.7 to 3.6 35 45 µs
LC87FC096A
No.A2150-22/26
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter Symbol Pin/Remarks Conditions Specification
VDD [V] min typ max unit
Transfer rate UBR P32(UTX1),
P33(URX1),
P34(UTX2),
P35(URX2)
2.5 to 3.6 16/3 8192/3 tCYC
Data length: 7, 8, and 9 bits (LSB first)
Stop bits: 1 bit (2-bit in con tinuous data transmission)
Parity bits: None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
VDD1, VSS1 Terminal Condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below.
• Place capacitors as close to VDD1 and VSS1 as po ssible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1µF.
• Use thicker pattern for VDD1 and VSS1.
End of
transmission
Transmit data (LSB first)
Start of
transmission
UBR
Start bit Stop bit
Stop bit
UBR
End of
reception
Receive data (LSB first)
Start of
reception
Start bit
VSS1
VDD1
L1’
L2’
L1
L2
C1 C2
LC87FC096A
No.A2150-23/26
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit cons tant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Frequency Vendor Name Oscillator Name Circuit Constant Operating
Voltage Range
[V]
Oscillation
Stabilization Time Remarks
C1
[pF] C2
[pF] Rf1
[Ω] Rd1
[Ω] typ
[ms] max
[ms]
12MHz
MURATA
CSTCE12M0G52-R0 (10) (10) Open 330 2.2 to 3.6 0.02 0.2 C1, C2
integrated type
8MHz CSTCE8M00G52-R0 (10) (10) Open 680 2.2 to 3.6 0.02 0.2 C1, C2
integrated type
CSTLS8M00G53-B0 (15) (15) Open 680 2.2 to 3.6 0.02 0.2 C1, C2
integrated type
4MHz CSTCR4M00G53-R0 (15) (15) Open 1.5K 2.2 to 3.6 0.02 0.2 C1, C2
integrated type
CSTLS4M00G53-B0 (15) (15) Open 1.5K 2.2 to 3.6 0.01 0.1 C1, C2
integrated type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltag e lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit th at are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit cons tant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Frequency Vendor
Name Oscillator Name Circuit Constant Operating
Voltage
Range
[V]
Oscillation
Stabilization Time Remarks
C3
[pF] C4
[pF] Rf2
[Ω] Rd2
[Ω] typ
[s] max
[s]
32.768kHz EPSON
TOYOCOM MC-306 9 9 OPEN 330K 2.2 to 3.6 1.0 3.0 CL=7pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit
Figure 3 AC Timing Measurement Point
0.5VDD
C3
Rd2
C4
X’tal
XT2 XT1
Rf
C1 C2
CF
CF2CF1
Rd1
Rf
LC87FC096A
No.A2150-24/26
Reset Time and Oscillation Stabilization Time
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
Power supply
RES
Internal RC oscillation
CF1, CF2
XT1, XT2
Operating
mode
Reset time
tmsCF
tmsX’tal
Unpredictable Reset Instruction execution
VDD
Operating VDD lower limit
0V
Internal RC oscillation
CF1, CF2
XT1, XT2
State
HOLD reset
signal HOLD reset signal
absent HOLD reset signal valid
tmsCF
tmsX’tal
HOLD HALT
LC87FC096A
No.A2150-25/26
Figure 5 Reset Circuit
Figure 6 Serial Input/Output Waveforms
Figure 7 Pulse Input Tim ing S i gnal Wav e f or m
tPIL
tPIH
CRES
VDD
RRES
RES
Note :
Determine the value of CRES and RRES so that the
reset signal is present for a period of 200μs after the
supply voltage goes beyond the lower limit of the IC’s
operating vol t age.
Data RAM
transfer period
(SIO0 only)
Data RAM
transfer period
(SIO0 only)
DI0 DI7DI2 DI3 DI4 DI5 DI6 DI8
DO0 DO7DO2 DO3 DO4 DO5 DO6 DO8
DI1
DO1
SIOCLK:
DATAIN:
DATAOUT:
DATAOUT:
DATAIN:
SIOCLK:
DATAOUT:
DATAIN:
SIOCLK:
tSCK
tSCKL tSCKH
thDItsDI
tdDO
tSCKL tSCKHA
thDItsDI
tdDO
LC87FC096A
No.A2150-26/26
t
B
U
F
tHD;STA
tLOW
tR
tHD;DAT
tHIGH
tF
tSU;DAT tSU;STA
tHD;STA
tsp
tSU;STO
P
S
Sr P
SDA
SCK
S: Start condition
P: Stop condition
Sir: Restart condition
Figure 8 I2C Timing
PS
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