2018 Microchip Technology Inc. DS20005856A-page 1
HV57009
Features
• 5V CMOS Logic
• Up to –85V Output Voltage
• Output Current Source Control
• 16 MHz Equivalent Data Rate
• Latched Data Outputs
• Forward and Reverse Shifting Options (DIR pin)
• Diode to VDD allows Efficient Power Recovery
Applications
• Plasma Panel Driver
• Display Driver
• Print Head Driver
• Relay Driver
• Microelectromechanical Systems Applications
General Description
The HV57009 is a low-voltage to high-voltage
serial-to-parallel converter with P-channel open drain
outputs. This device has been designed as a driver for
plasma panels.
The device has two parallel 32-bit Shift registers,
permitting data rates twice the speed of one in a single
clock cycle. There are also 64 latches and control logic
to perform the blanking of the outputs. HVOUT1 is
connected to the first stage of the first Shift register
through the blanking logic. Data is shifted through the
Shift registers on the logic low-to-high transition of the
clock. The DIR pin causes counter-clockwise shifting
when connected to VSS and clockwise shifting when
connected to VDD. A data output buffer is provided for
cascading devices. This output reflects the current
status of the last bit of the Shift register, HVOUT64. The
operation of the Shift register is not affected by the latch
enable (LE) and the blanking (BL) inputs. Data transfer
from the Shift registers to the latches occurs when the
LE input is high. The data in the latches is stored when
LE is low.
The HV57009 has 64 channels of output
constant-current sourcing capability. They are
adjustable from 0.1 mA to 2 mA through one external
resistor or a current source.
Package Type
See Table 2-1 for pin information.
80-lead PQFP
(Top view)
1
80
64-Channel Serial-to-Parallel Converter with P-Channel Open Drain
Controllable Output Current
HVOUT1
HVOUT2
HVOUT3
•
•
•
HVOUT32
HVOUT33
HVOUT34
HVOUT35
•
•
•
HVOUT64
Latch
Latch
Latch
Latch
VDD
VSS
BL
LE
CLK
DIR
VBP +IN -IN
DI/O2B
Note:
Each SR (shift register) provides 32 outputs. SR1 supplies outputs 1 to 32 and SR2 supplies outputs 33 to 64.
Programmable
Current
DI/O1B
SR2
I/O
DI/O2A DI/O1A
I/O
SR1
HV57009
DS20005856A-page 2 2018 Microchip Technology Inc.
Functional Block Diagram
2018 Microchip Technology Inc. DS20005856A-page 3
HV57009
Typical Application Circuit
HV57009
DS20005856A-page 4 2018 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage, VDD (Note 1) ................................................................................................................. –0.5V to +7.5V
Output Voltage, VNN (Note 1) .......................................................................................................... VDD +0.5V to –95V
Logic Input Levels (Note 1) ............................................................................................................ –0.3V to VDD +0.3V
Ground Current (Note 2) ......................................................................................................................................... 1.5A
Operating Ambient Temperature, TA .................................................................................................... –40°C to +85°C
Storage Temperature, TS .................................................................................................................... –65°C to +150°C
Continuous Total Power Dissipation:
80-lead PQFP (Note 3) ......................................................................................................................... 1200 mW
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: All voltages are referenced to VSS.
2: Duty cycle is limited by the total power dissipated in the package.
3: For operations above 25°C ambient, derate linearly to the maximum operating temperature at 20 mW/°C.
RECOMMENDED OPERATING CONDITIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
Logic Supply Voltage VDD 4.5 —5.5 V
High-Voltage Output Voltage HVOUT –85 — VDD V
High-Level Input Voltage VIH VDD–1.2V — VDD V
Low-Level Input Voltage VIL 0 — 1.2 V
Clock Frequency per Register fCLK DC — 8 MHz
—4.5 MHz
Operating Ambient Temperature TA–40 —+85 °C
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: All voltages are referenced to VSS, VSS = 0, and TA = 25°C. Current going out of the chip
is considered negative.
Parameter Sym. Min. Typ. Max. Unit Conditions
VDD Supply Current IDD — — 15 mA VDD = VDD maximum,
fCLK = 8 MHz
High-Voltage Supply Current INN — — –10 µA Outputs off, HVOUT = –85V
(total of all outputs)
Quiescent VDD Supply Current IDDQ — — 100 µA All inputs = VDD,
except +IN = VSS = GND
High-Level Output Data Out VOH
VDD–0.5V — — V IO= –100 µA
HVOUT +1 —VDD V IO = –2 mA
Low-Level Output Data Out VOL — — +0.5 V IO = 100 µA
High-Level Logic Input Current IIH — — 1µA VIH = VDD
Low-Level Logic Input Current IIL — — –1 µA VIL = 0V
High-Output Source Current ICS
— — –2 mA VREF = 2V, REXT = 1 k,
See Figure 3-3 and Figure 3-4.
–0.1 ——mA VREF = 0.1V, REXT = 1 k,
See Figure 3-3 and Figure 3-4.
High-Voltage Output Source Current
for IREF = 2 mA ICS — — 10 % VREF = 2V, REXT = 1 k,
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Logic signal inputs and data inputs have tr, tf 5 ns (10% and 90% points) for
measurements.
Parameter Sym. Min. Typ. Max. Unit Conditions
Clock Frequency fCLK DC — 8 MHz Per register
—4.5 MHz When cascading devices
Clock Width High or Low tWL, tWH 62 — — ns
Data Set-Up Time before Clock Rises tSU 20 — — ns
Data Hold Time after Clock Rises tH15 — — ns
Time from Latch Enable to HVOUT tON, tOFF ——500 ns CL = 15 pF
Latch Enable Pulse Width tWLE 25 — — ns
Delay Time Clock to Latch Enable Low to High tDLE 45 — — ns
Latch Enable Set-Up Time before Clock Rises tSLE 0— — ns
Delay Time Clock to Data Low to High tDLH — — 150 ns CL = 15 pF
Delay Time Clock to Data High to Low tDHL — — 150 ns CL = 15 pF
Maximum Allowable Clock Rise and Fall Time
(10% and 90% Points) tr, tf— — 100 ns
2018 Microchip Technology Inc. DS20005856A-page 5
HV57009
TEMPERATURE SPECIFICATIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
TEMPERATURE RANGE
Operating Ambient Temperature TA–40 —+85 °C
Storage Temperature TS–65 —+150 °C
PACKAGE THERMAL RESISTANCE
80-lead PQFP JA —37 —°C/W
HV57009
DS20005856A-page 6 2018 Microchip Technology Inc.
Timing Waveforms
LE
HVOUT
w/ Data Input
Low
Previous IO = IREF
Previous IO = 0
IO = 0
IO = IREF
Data Valid 50% 50%
DATA
INPUT
CLK
DATA
OUT
50% 50% 50%
tSU tH
tWL tWH
50%
tDLH
tDLH
50%
tWLE
tDLE tSLE
50% 50%
tON
10%
90%
90%
10%
tOFF
VDD
VSS
VDD
HVOUT(OFF)
10%
90% 90%
10% 50%
tf tr
HVOUT
w/ Data Input
High
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
HVOUT(OFF)
2018 Microchip Technology Inc. DS20005856A-page 7
HV57009
2.0 PIN DESCRIPTION
The details on the pins of HV57009 are listed on
Table 2-1. Refer to Package Type for the location of
pins.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number Pin Name Description
1HVOUT24 High-voltage output
2HVOUT23 High-voltage output
3HVOUT22 High-voltage output
4HVOUT21 High-voltage output
5HVOUT20 High-voltage output
6HVOUT19 High-voltage output
7HVOUT18 High-voltage output
8HVOUT17 High-voltage output
9HVOUT16 High-voltage output
10 HVOUT15 High-voltage output
11 HVOUT14 High-voltage output
12 HVOUT13 High-voltage output
13 HVOUT12 High-voltage output
14 HVOUT11 High-voltage output
15 HVOUT10 High-voltage output
16 HVOUT9 High-voltage output
17 HVOUT8 High-voltage output
18 HVOUT7 High-voltage output
19 HVOUT6 High-voltage output
20 HVOUT5 High-voltage output
21 HVOUT4 High-voltage output
22 HVOUT3 High-voltage output
23 HVOUT2 High-voltage output
24 HVOUT1 High-voltage output
25 DI/O1A Data Input/Output 1A pin
26 DI/O2A Data Input/Output 2A pin
27 NC No connection
28 NC No connection
29 LE Latch enable pin
30 CLK Clock pin
31 BL Blanking pin
32 VSS Reference voltage (usually ground)
33 DIR Direction pin (See Note 1.)
34 VDD Logic supply voltage (See Note 2.)
Note 1: Pin designation for DIR = VDD.
2: 0.1 µF capacitor is needed between VDD and VBP (pin 40) for better output current stability and to
prevent transient cross-coupling between outputs. See Figure 3-3 and Figure 3-4.
HV57009
DS20005856A-page 8 2018 Microchip Technology Inc.
35 –IN –IN input pin
36 DI/O2B Data Input/Output 2B pin
37 DI/O1B Data Input/Output 1B pin
38 NC No connection
39 +IN +IN input pin
40 VBP Bias control voltage (See Note 2.)
41 HVOUT64 High-voltage output
42 HVOUT63 High-voltage output
43 HVOUT62 High-voltage output
44 HVOUT61 High-voltage output
45 HVOUT60 High-voltage output
46 HVOUT59 High-voltage output
47 HVOUT58 High-voltage output
48 HVOUT57 High-voltage output
49 HVOUT56 High-voltage output
50 HVOUT55 High-voltage output
51 HVOUT54 High-voltage output
52 HVOUT53 High-voltage output
53 HVOUT52 High-voltage output
54 HVOUT51 High-voltage output
55 HVOUT50 High-voltage output
56 HVOUT49 High-voltage output
57 HVOUT48 High-voltage output
58 HVOUT47 High-voltage output
59 HVOUT46 High-voltage output
60 HVOUT45 High-voltage output
61 HVOUT44 High-voltage output
62 HVOUT43 High-voltage output
63 HVOUT42 High-voltage output
64 HVOUT41 High-voltage output
65 HVOUT40 High-voltage output
66 HVOUT39 High-voltage output
67 HVOUT38 High-voltage output
68 HVOUT37 High-voltage output
69 HVOUT36 High-voltage output
70 HVOUT35 High-voltage output
71 HVOUT34 High-voltage output
72 HVOUT33 High-voltage output
73 HVOUT32 High-voltage output
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Name Description
Note 1: Pin designation for DIR = VDD.
2: 0.1 µF capacitor is needed between VDD and VBP (pin 40) for better output current stability and to
prevent transient cross-coupling between outputs. See Figure 3-3 and Figure 3-4.
2018 Microchip Technology Inc. DS20005856A-page 9
HV57009
74 HVOUT31 High-voltage output
75 HVOUT30 High-voltage output
76 HVOUT29 High-voltage output
77 HVOUT28 High-voltage output
78 HVOUT27 High-voltage output
79 HVOUT26 High-voltage output
80 HVOUT25 High-voltage output
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Name Description
Note 1: Pin designation for DIR = VDD.
2: 0.1 µF capacitor is needed between VDD and VBP (pin 40) for better output current stability and to
prevent transient cross-coupling between outputs. See Figure 3-3 and Figure 3-4.
HV57009
DS20005856A-page 10 2018 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
Follow the steps in Ta ble 3-1 to power up and power
down the HV57009.
TABLE 3-1: POWER-UP AND POWER-DOWN SEQUENCE
Power-up Power-down
Step Description Step Description
1Connect ground. 1Remove VPP.
2Apply VDD. 2Remo ve all inputs.
3Set all inputs (Data, CLK, Enable, etc.) to a known state. 3Remove VDD.
4Apply VPP. 4Disconnect ground.
TABLE 3-2:
Function
Inputs Outputs
Data CLK LE BL DIR Shift Register High-voltage Output Data Out
All O/P High X X X L X *ON *
Data Falls Through
(Latches Transparent)
LH H X L...L ON L
HH H X H...H OFF H
Data Stored in Latches X X L H X *Inversion of stored data *
I/O Relation
DI/O1-2A H H H QNQN+1 New ON or OFF DI/O1-2B
DI/O1-2A L H H QNQN+1 Previous ON or OFF DI/O1-2B
DI/O1-2B L H L QNQN-1 Previous ON or OFF DI/O1-2A
DI/O1-2B H H L QNQN-1 New ON or OFF DI/O1-2A
Note: H = VDD (Logic)/VNN (HV Outputs)
L = VSS
= Low-to-high transition
* = Dependent on the previous stage’s state. See Figure 3-2 for DIN and DOUT pin designation for clockwise
and counter-clockwise shifts.
TRUTH FUNCTION TABLE
DATA
INPUT
VDD
Logic Inputs
DATA
OUTPUT
Logic Data Output
To Internal
Circuits
VSS
Analog Input
I
CS
HVOUT
High Voltage Output
VDD
VSS
VDD
VSS
VDD
PCNTRL
DATA
INPUT
2018 Microchip Technology Inc. DS20005856A-page 11
HV57009
FIGURE 3-1: Input and Output Equivalent Circuits.
25 26 36 37
HVOUT33
•
•
•
•
•
HVOUT63
HVOUT64
Pin
DIR = VDD
DIR = VSS
SR1
CW
DIR = VDD; CW (HVOUT1→HVOUT64)
DIR = VSS; CCW (HVOUT64→HVOUT1)
DI/O1A DI/O2A DI/O2B DI/O1B
DI/O2A DI/O1A DI/O1B DI/O2B
HVOUT32
•
•
•
•
•
HVOUT2
HVOUT1
CW
SR1
FIGURE 3-2: Shift Register Operation.
HV57009
DS20005856A-page 12 2018 Microchip Technology Inc.
3.1 Typical Current Programing Circuits
VREF
I
OUT
HVOUT
VDD
0.1μF
VBP
I
REF
R
EXT
+IN -IN
C
D
*390pF
HV57009
Logic
To other
outputs
-+
VSS
R
D
*10kΩ
*Required if REXT > 10 k or REXT is replaced by a constant current source.
FIGURE 3-3: Negative Control Circuit.
*Required if REXT > 10 k or REXT is replaced by a constant current source.
+IN -IN
R
D
*10kΩ
HV57009
Logic
To other
outputs
-+
VREF
IOUT
HVOUT
VDD
VBP
IREF
REXT
VSS
0.1μF
CD *390pF
FIGURE 3-4: Positive Control Circuit.
2018 Microchip Technology Inc. DS20005856A-page 13
HV57009
Figure 3-3 and Figure 3-4 show the programming
circuits to control the high-voltage output current limit.
A reference current IREF is set by the external resistor
REXT and reference voltage VREF
. The current mirror
formed by the matching transistors uses the reference
current to cap the maximum allowed current at the
high-voltage output. The relationship between IOUT and
IREF are shown in Equation 3-1 and Equation 3-2.
EQUATION 3-1:
IOUT IREF VREF REXT
==
EQUATION 3-2:
If IOUT = 2 mA and VREF = –5V → REXT = 2.5 kΩ
If IOUT = 1 mA and REXT = 1 kΩ → VREF = –1V
If REXT > 10 k, add series network RD and CD to
ground for stability as shown in Figure 3-3 and
Figure 3-4.
This control method behaves linearly as long as the
operational amplifier is not saturated. However, it
requires a negative power source and needs to provide
a current IREF = IOUT for each HV57009 chip being
controlled.
If HVOUT +1V, the HVOUT cascade may no longer
operate as a perfect current source, and the output
current will diminish. This effect depends on the
magnitude of the output current.
Given IOUT and VREF
, the REXT can be calculated using
Equation 3-3:
EQUATION 3-3:
REXT VREF IREF
VREF IOUT
==
The intersection of a set of IOUT and VREF values can
be located in Figure 3-5. The value picked for REXT
must always be in the shaded area for linear operation.
This control method has the advantage that VREF is
positive and draws leakage current only. If
REXT > 10 k, add series network RD and CD to ground
for stability as shown in Figure 3-3 and Figure 3-4.
4
3
2
1
00 1 2 3 4 5
V
REF
(V)
I
OUT
(mA)
0.1k 0.2k 0.5k 1.0k 2.0k 3.0k
5.0K
Note: Lower reference current, IREF
, results in
higher distortion, ICS, on the output.
FIGURE 3-5: IOUT vs. IREF
.
HV57009
DS20005856A-page 14 2018 Microchip Technology Inc.
4.0 PACKAGE MARKING INFORMATION
4.1 Packaging Information
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
YYWWNNN
XXXXXXXXX 1822568
HV57009PG
e3
80-lead PQFP Example
e3
80-Lead PQFP Package Outline (PG)
20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint
Symbol A A1 A2 b D D1 E E1 e L L1 L2 șș
Dimen-
sion
(mm)
MIN 2.80* 0.25 2.55 0.30 23.65* 19.80* 17.65* 13.80*
0.80
BSC
0.73
1.95
REF
0.25
BSC
0
O
5
O
NOM - - 2.80 - 23.90 20.00 17.90 14.00 0.88 3.5
O
-
MAX 3.40 0.50* 3.05 0.45 24.15* 20.20* 18.15* 14.20* 1.03 7
O
16
O
JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
Drawings not to scale.
SD#DSPD 80PQFPPG V i C041309
1
80
Seating
Plane
Gauge
Plane
ș
L
L1
L2
View B
View B
ș
b
e
Side View
A2
A
A1
E
E1
D
D1
Seating
Plane
Top View
Note 1
(Index Area
D1/4 x E1/4)
Note:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2018 Microchip Technology Inc. DS20005856A-page 15
HV57009
HV57009
DS20005856A-page 16 2018 Microchip Technology Inc.
NOTES:
2018 Microchip Technology Inc. DS20005856A-page 17
HV57009
APPENDIX A: REVISION HISTORY
Revision A (April 2018)
• Converted Supertex Doc # DSFP-HV57009 to
Microchip DS20005856A
• Removed “HVCMOS® Technology” in the
Features section
• Changed the package marking format
• Made minor changes throughout the document
HV57009
DS20005856A-page 18 2018 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
2018 Microchip Technology Inc. DS20005856A-page 19
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
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Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
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GestIC is a registered trademark of Microchip Technology
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All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2951-7
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005856A-page 20 2018 Microchip Technology Inc.
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Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
ASIA/PACIFIC
Australia - Sydney
Tel: 61-2-9868-6733
China - Beijing
Tel: 86-10-8569-7000
China - Chengdu
Tel: 86-28-8665-5511
China - Chongqing
Tel: 86-23-8980-9588
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
China - Hong Kong SAR
Tel: 852-2943-5100
China - Nanjing
Tel: 86-25-8473-2460
China - Qingdao
Tel: 86-532-8502-7355
China - Shanghai
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
China - Suzhou
Tel: 86-186-6233-1526
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Tel: 86-29-8833-7252
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
India - New Delhi
Tel: 91-11-4160-8631
India - Pune
Tel: 91-20-4121-0141
Japan - Osaka
Tel: 81-6-6152-7160
Japan - Tokyo
Tel: 81-3-6880- 3770
Korea - Daegu
Tel: 82-53-744-4301
Korea - Seoul
Tel: 82-2-554-7200
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Malaysia - Penang
Tel: 60-4-227-8870
Philippines - Manila
Tel: 63-2-634-9065
Singapore
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7289-7561
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
10/25/17