DATA SHEET MOS INTEGRATED CIRCUIT PD4264405, 42S65405, 4265405 64 M-BIT DYNAMIC RAM 16 M-WORD BY 4-BIT, EDO Description The PD4264405, 42S65405, 4265405 are 16,777,216 words by 4 bits CMOS dynamic RAMs with optional EDO. EDO is a kind of the page mode and is useful for the read operation. Besides, the PD42S65405 can execute CAS before RAS self refresh. These are packaged in 32-pin plastic TSOP (II) and 32-pin plastic SOJ. Features * EDO (Hyper page mode) * 16,777,216 words by 4 bits organization * Single +3.3 V 0.3 V power supply * Fast access and cycle time Power consumption Active (MAX.) Part number PD4264405-A50 360 mW PD42S65405-A50, 4265405-A50 468 mW PD4264405-A60 324 mW PD42S65405-A60, 4265405-A60 396 mW Access time (MAX.) R/W cycle time (MIN.) EDO (Hyper page mode) cycle time (MIN.) 50 ns 84 ns 20 ns 60 ns 104 ns 25 ns * The PD42S65405 can execute CAS before RAS self refresh. Part number PD42S65405 PD4264405 PD4265405 Refrech cycle 4,096 cycles/128 ms 8,192 cycles/64 ms Refresh RAS only refresh, Normal read/write, CAS before RAS self refresh, CAS before RAS refresh, Hidden refresh RAS only refresh, Normal read/write 4,096 cycles/64 ms CAS before RAS refresh, Hidden refresh 4,096 cycles/64 ms RAS only refresh, Normal read/write, CAS before RAS refresh, Hidden refresh Power consumption at standby (MAX.) 0.72 mW (CMOS level input) 1.8 mW (CMOS level input) The information in this document is subject to change without notice. Document No. M10856EJ6V0DS00 (6th edition) Date Published September 1997 N Printed in Japan The mark shows major revised points. (c) 1995 PD4264405, 42S65405, 4265405 Ordering Information Access time (MAX.) Package 50 ns 32-pin plastic TSOP (II) PD42S65405G5-A60-7JD 60 ns (400 mil) PD42S65405LE-A50 50 ns 32-pin plastic SOJ PD42S65405LE-A60 60 ns (400 mil) PD4264405G5-A50-7JD 50 ns 32-pin plastic TSOP (II) PD4264405G5-A60-7JD 60 ns (400 mil) Part number PD42S65405G5-A50-7JD 2 Refresh CAS before RAS self refresh CAS before RAS refresh RAS only refresh Hidden refresh CAS before RAS refresh RAS only refresh Hidden refresh PD4265405G5-A50-7JD 50 ns PD4265405G5-A60-7JD 60 ns PD4264405LE-A50 50 ns 32-pin plastic SOJ PD4264405LE-A60 60 ns (400 mil) PD4265405LE-A50 50 ns PD4265405LE-A60 60 ns PD4264405, 42S65405, 4265405 Pin Configurations (Marking Side) 32-pin Plastic TSOP (II) (400 mil) 32-pin Plastic SOJ (400 mil) PD4264405G5-7JD PD4264405LE PD42S65405G5-7JD PD42S65405LE PD4265405G5-7JD PD4265405LE VCC 1 32 GND VCC 1 32 GND I/O1 2 31 I/O4 I/O1 2 31 I/O4 I/O2 3 30 I/O3 I/O2 3 30 I/O3 NC 4 29 NC NC 4 29 NC NC 5 28 NC NC 5 28 NC NC 6 27 NC NC 6 27 NC NC 7 26 CAS NC 7 26 CAS WE 8 25 OE WE 8 25 OE RAS 9 24 A12/NC RAS Note Note 9 24 A12/NC A0 10 23 A11 A0 10 23 A11 A1 11 22 A10 A1 11 22 A10 A2 12 21 A9 A2 12 21 A9 A3 13 20 A8 A3 13 20 A8 A4 14 19 A7 A4 14 19 A7 A5 15 18 A6 A5 15 18 A6 VCC 16 17 GND VCC 16 17 GND Note A12 ... PD4264405 NC ... PD42S65405, 4265405 A0 to A12 : Address Inputs I/O1 to I/O4 : Data Inputs/Outputs RAS : Row Address Strobe CAS : Column Address Strobe WE : Write Enable OE : Output Enable V CC : Power Supply GND : Ground NC : No Connection 3 PD4264405, 42S65405, 4265405 Block Diagram RAS OE Clock Generator CAS WE Data Output Buffer VCC CAS before RAS Counter Row Decoder GND Memory Cell Array I/O1 to I/O4 Bit organizationNote2 Row Address Buffer Sense Amplifier AddressNote 1 Column Address Buffer Column Decoder Notes 1. Part number Row address Column address PD4264405 A0 - A12 A0 - A10 PD42S65405, 4265405 A0 - A11 A0 - A11 2. 4,096 x 4,096 x 4 4 x4 Data Input Buffer PD4264405, 42S65405, 4265405 Input/Output Pin Functions The PD4264405, 42S65405, 4265405 have input pins RAS, CAS, WE, OE, AddressNote and input/output pins I/O1 to I/O4. Input/Output Pin name Function RAS (Row address strobe) Input RAS activates the sense amplifier by latching a row address and selecting a corresponding word line. It refreshes memory cell array of one line selected by the row address. It also selects the following function. * CAS before RAS self refresh, CAS before RAS refresh CAS (Column address strobe) Input CAS activates data input/output circuit by latching column address and selecting a digit line connected with the sense amplifier. A0 to AxNote (Address inputs) Input Address bus. Input total 24-bit of address signal, upper bits and lower bitsNote in sequence (address multiplex method). Therefore, one word is selected from 16,777,216-word by 4-bit memory cell array. In actual operation, latch row address by specifying row address and activating RAS. Then, switch the address bus to column address and activate CAS. Each address is taken into the device when RAS and CAS are activated. Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH) are specified for the activation of RAS and CAS. WE (Write enable) Input Write control signal. Write operation is executed by activating RAS, CAS and WE. OE (Output enable) Input Read control signal. Read operation can be executed by activating RAS, CAS and OE. If WE is activated during read operation, OE is to be ineffective in the device. Therefore, read operation cannot be executed. I/O1 to I/O4 (Data inputs/outputs) Input/Output 4-bit data bus. I/O1 to I/O4 are used to input/output data. Note Part number Address inputs Upper bits Lower bits PD4264405 A0 - A12 13 11 PD42S65405, 4265405 A0 - A11 12 12 5 PD4264405, 42S65405, 4265405 Hyper Page Mode (EDO) The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the hyper page mode (EDO) are as follows. 1. Data output time is extended. In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. 2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode. In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that in the fast page mode is 40 ns. In the hyper page mode (EDO) , read (data out) and write (data in) cycles can be executed repeatedly during one RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle. The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described in the next page. Hyper Page Mode (EDO) Read Cycle RAS VIH - VIL - tOFR tHPC CAS VIH - VIL - tOFC Address VIH - VIL - Row Col.A Col.B tRAC tAA tCAC WE tRCH tAA tAA tCAC tCAC tWPZ tRRH VIH - VIL - tOCH tCHO tOCH tOEP tOEP tOEA OE Col.C tOEA tWEZ tCHO VIH - VIL - tOLZ tDHC tCLZ I/O 6 VOH - VOL - Hi - Z Data out A tOEZ Data out B tCLZ tOEZ Data out C tOEZ Data out C Hi - Z PD4264405, 42S65405, 4265405 Cautions when using the hyper page mode (EDO) 1. CAS access should be used to operate tHPC at the MIN. value. 2. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective specification depends on the state of each signal. (1) Both RAS and CAS are inactive (at the end of read cycle) WE: inactive, OE: active t OFC is effective when RAS is inactivated before CAS is inactivated. t OFR is effective when CAS is inactivated before RAS is inactivated. The slower of tOFC and tOFR becomes effective. (2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle) WE, OE: inactive ***** t OEZ is effective. Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle) WE, OE: active and either t RRH or t RCH must be met ***** t WEZ and t WPZ are effective. The faster of t OEZ and t WEZ becomes effective. The faster of (1) and (2) becomes effective. 3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output with the OE signal. (1) CAS: inactive, OE: active ***** tCHO is effective. (2) CAS, OE: active ***** tOCH is effective. 7 PD4264405, 42S65405, 4265405 Electrical Specifications * All voltages are referenced to GND. * After power up (VCC VCC(MIN.)), wait more than 100 s (RAS, CAS inactive) and then, execute eight CAS before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit. Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Voltage on any pin relative to GND VT -0.5 to +4.6 V Supply voltage VCC -0.5 to +4.6 V Output current IO 50 mA Power dissipation PD 1 W Operating ambient temperature TA 0 to +70 C Storage temperature Tstg -55 to +125 C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 3.3 3.6 V Supply voltage VCC 3.0 High level input voltage VIH 2.0 VCC + 0.3 V Low level input voltage VIL -0.3 +0.8 V Operating ambient temperature TA 0 70 C MAX. Unit pF Capacitance (TA = 25 C, f = 1 MHZ) Parameter Input capacitance Data input/output capacitance 8 Symbol Test condition MIN. TYP. CI1 Address 5 CI2 RAS, CAS, WE, OE 7 CI/O I/O 7 pF PD4264405, 42S65405, 4265405 DC Characteristics (Recommended operating conditions unless otherwise noted) [PD4264405] Parameter Operating current Standby current RAS only refresh current Operating current Symbol ICC1 ICC2 ICC3 ICC4 (Hyper page mode (EDO)) CAS before RAS ICC5 refresh current Test condition MIN. MAX. Unit Notes mA 1, 2, 3 RAS, CAS cycling tRAC = 50 ns 100 tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 90 RAS, CAS VIH (MIN.), IO = 0 mA 1.0 RAS, CAS VCC - 0.2 V, IO = 0 mA 0.5 RAS cycling, CAS VIH (MIN.) tRAC = 50 ns 100 tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 90 RAS VIL (MAX.), CAS cycling tRAC = 50 ns 100 tHPC = tHPC (MIN.), IO = 0 mA tRAC = 60 ns 90 RAS cycling tRAC = 50 ns 130 tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 110 mA mA 1, 2, 3 ,4 mA 1, 2, 5 mA 1, 2 Input leakage current II (L) VI = 0 to 3.6 V All other pins not under test = 0 V -5 +5 A Output leakage current IO (L) VO = 0 to 3.6 V Output is disabled (Hi-Z) -5 +5 A High level output voltage VOH IO = -2.0 mA 2.4 Low level output voltage VOL IO = +2.0 mA V 0.4 V 9 PD4264405, 42S65405, 4265405 [PD42S65405, 4265405] Parameter Operating current PD42S65405 Standby current Symbol ICC1 ICC2 PD4265405 RAS only refresh current Operating current ICC3 ICC4 (Hyper page mode (EDO)) CAS before RAS ICC5 refresh current CAS before RAS long refresh current (4,096 cycles/128 ms, only for the PD42S65405) ICC6 Test condition MIN. MAX. Unit Notes mA 1, 2, 3 RAS, CAS cycling tRAC = 50 ns 130 tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 110 RAS, CAS VIH (MIN.), IO = 0 mA 1.0 RAS, CAS VCC - 0.2 V, IO = 0 mA 0.2 RAS, CAS VIH (MIN.), IO = 0 mA 1.0 RAS, CAS VCC - 0.2 V, IO = 0 mA 0.5 RAS cycling, CAS VIH (MIN.) tRAC = 50 ns 130 tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 110 RAS VIL (MAX.), CAS cycling tRAC = 50 ns 100 tHPC = tHPC (MIN.), IO = 0 mA tRAC = 60 ns 90 RAS cycling tRAC = 50 ns 130 tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 110 CAS before RAS refresh: tRAS 300 ns tRC = 31.3 s RAS, CAS: VCC - 0.2 V VIH VIH (MAX.) 0 V VIL 0.2 V Standby: RAS, CAS VCC - 0.2 V Address: VIH or VIL WE, OE: VIH IO = 0 mA tRAS 1 s mA mA 1, 2, 3 ,4 mA 1, 2, 5 mA 1, 2 500 A 1, 2 600 A 1, 2 400 A 2 CAS before RAS self refresh current (only for the PD42S65405) ICC7 RAS, CAS: tRASS = 5 ms VCC - 0.2 V VIH VIH (MAX.) 0 V VIL 0.2 V IO = 0 mA Input leakage current II (L) VI = 0 to 3.6 V All other pins not under test = 0 V -5 +5 A Output leakage current IO (L) VO = 0 to 3.6 V Output is disabled (Hi-Z) -5 +5 A High level output voltage VOH IO = -2.0 mA 2.4 Low level output voltage VOL IO = +2.0 mA V 0.4 V Notes 1. ICC1, ICC3, ICC4, ICC5 and ICC6 depend on cycle rates (tRC and tHPC). 2. Specified values are obtained with outputs unloaded. 3. ICC1 and ICC3 are measured assuming that address can be changed once or less during RAS VIL (MAX.) and CAS VIH (MIN.). 4. ICC3 is measured assuming that all column address inputs are held at either high or low. 5. ICC4 is measured assuming that all column address inputs are switched only once during each hyper page (EDO) cycle. 10 PD4264405, 42S65405, 4265405 AC Characteristics (Recommended Operating Conditions unless otherwise noted) AC Characteristics Test Conditions (1) Input timing specification (2) Output timing specification VIH (MIN.) = 2.0 V VOH (MIN.) = 2.0 V VIL (MAX.) = 0.8 V VOL tT = 2 ns (MAX.) = 0.8 V tT = 2 ns (3) Output load condition VCC 1,180 I/O 870 100 pF CL Common to Read, Write, Read Modify Write Cycle tRAC = 50 ns tRAC = 60 ns MIN. MAX. MIN. MAX. tRC 84 - 104 - ns RAS precharge time tRP 30 - 40 - ns CAS precharge time tCPN 7 - 10 - ns RAS pulse width tRAS 50 10,000 60 10,000 ns Parameter Read / Write cycle time Symbol Unit Notes 1 CAS pulse width tCAS 8 10,000 10 10,000 ns RAS hold time tRSH 13 - 15 - ns CAS hold time tCSH 38 - 40 - ns RAS to CAS delay time tRCD 11 37 14 45 ns 2 RAS to column address delay time tRAD 9 25 12 30 ns 2 CAS to RAS precharge time tCRP 5 - 5 - ns 3 Row address setup time tASR 0 - 0 - ns Row address hold time tRAH 7 - 10 - ns Column address setup time tASC 0 - 0 - ns Column address hold time tCAH 7 - 10 - ns OE lead time referenced to RAS tOES 0 - 0 - ns CAS to data setup time tCLZ 0 - 0 - ns OE to data setup time tOLZ 0 - 0 - ns OE to data delay time tOED 10 - 13 - ns tT 1 50 1 50 ns tREF - 128 - 128 ms - 64 - 64 ms Transition time (rise and fall) Refresh time PD42S65405 PD4264405, 4265405 4 11 PD4264405, 42S65405, 4265405 Notes 1. In CAS before RAS refresh cycles, tRAS(MAX) is 100 s. If 10 s < tRAS < 100 s, RAS precharge time for CAS before RAS self refresh (tRPS) is applied. 2. For read cycles, access time is defined as follows: Input conditions Access time Access time from RAS tRAD tRAD (MAX.) and tRCD tRCD (MAX.) tRAC (MAX.) tRAC (MAX.) tRAD > tRAD (MAX.) and tRCD tRCD (MAX.) tAA (MAX.) tRAD + tAA (MAX.) tRCD > tRCD (MAX.) tCAC (MAX.) tRCD + tCAC (MAX.) tRAD (MAX.) and tRCD (MAX.) are specified as reference points only ; they are not restrictive operating parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output data will be available. Therefore, the input conditions tRAD tRAD (MAX.) and tRCD tRCD (MAX.) will not cause any operation problems. 3. tCRP (MIN.) requirement is applied to RAS, CAS cycles. 4. This specification is applied only to the PD42S65405. Read Cycle Parameter tRAC = 50 ns tRAC = 60 ns MIN. MAX. MIN. MAX. Symbol Unit Notes Access time from RAS tRAC - 50 - 60 ns 1 Access time from CAS tCAC - 13 - 15 ns 1 Access time from column address tAA - 25 - 30 ns 1 Access time from OE tOEA - 13 - 15 ns Column address lead time referenced to RAS tRAL 25 - 30 - ns Read command setup time tRCS 0 - 0 - ns Read command hold time referenced to RAS tRRH 0 - 0 - ns 2 Read command hold time referenced to CAS tRCH 0 - 0 - ns 2 Output buffer turn-off delay time from OE tOEZ 0 10 0 13 ns 3 CAS hold time to OE tCHO 5 - 5 - ns 4 Notes 1. For read cycles, access time is defined as follows: Input conditions Access time Access time from RAS tRAD tRAD (MAX.) and tRCD tRCD (MAX.) tRAC (MAX.) tRAC (MAX.) tRAD > tRAD (MAX.) and tRCD tRCD (MAX.) tAA (MAX.) tRAD + tAA (MAX.) tRCD > tRCD (MAX.) tCAC (MAX.) tRCD + tCAC (MAX.) tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output data will be available. Therefore, the input conditions tRAD tRAD (MAX.) and tRCD tRCD (MAX.) will not cause any operation problems. 2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles. 3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or VOL. 4. WE: inactive (in read cycle) CAS: inactive, OE: active *** tCHO is effective. CAS, OE: active *** tOCH is effective. 12 PD4264405, 42S65405, 4265405 Write Cycle Parameter tRAC = 50 ns tRAC = 60 ns MIN. MAX. MIN. MAX. Symbol Unit Notes WE hold time referenced to CAS tWCH 7 - 10 - ns 1 WE pulse width tWP 7 - 10 - ns 1 WE lead time referenced to RAS tRWL 13 - 15 - ns WE lead time referenced to CAS tCWL 7 - 10 - ns WE setup time tWCS 0 - 0 - ns OE hold time tOEH 0 - 0 - ns Data-in setup time tDS 0 - 0 - ns 3 Data-in hold time tDH 7 - 10 - ns 3 2 Notes 1. tWP (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should be met. 2. If tWCS tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle. 3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and read modify write cycles, they are referenced to the WE falling edge. Read Modify Write Cycle Parameter tRAC = 50 ns tRAC = 60 ns MIN. MAX. MIN. MAX. Symbol Unit Note Read modify write cycle time tRWC 107 - 133 - ns RAS to WE delay time tRWD 64 - 77 - ns 1 CAS to WE delay time tCWD 27 - 32 - ns 1 Column address to WE delay time tAWD 39 - 47 - ns 1 Note 1. If tWCS tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle. If tRWD tRWD (MIN.), tCWD tCWD (MIN.), tAWD tAWD (MIN.) and tCPWD tCPWD (MIN.), the cycle is a read modify write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is met, the state of the data out is indeterminate. 13 PD4264405, 42S65405, 4265405 Hyper Page Mode (EDO) Parameter tRAC = 50 ns tRAC = 60 ns MIN. MAX. MIN. MAX. Symbol Unit Notes Read / Write cycle time tHPC 20 - 25 - ns 1 RAS pulse width tRASP 50 125,000 60 125,000 ns CAS pulse width tHCAS 8 10,000 10 10,000 ns CAS precharge time tCP 7 - 10 - ns Access time from CAS precharge tACP - 30 - 35 ns CAS precharge to WE delay time tCPWD 41 - 52 - ns RAS hold time from CAS precharge tRHCP 30 - 35 - ns Read modify write cycle time tHPRWC 52 - 66 - ns Data output hold time tDHC 5 - 5 - ns OE to CAS hold time tOCH 5 - 5 - ns OE precharge time tOEP 5 - 5 - ns Output buffer turn-off delay from WE tWEZ 0 10 0 13 ns 4,5 WE pulse width tWPZ 7 - 10 - ns 5 Output buffer turn-off delay from RAS tOFR 0 10 0 13 ns 4,5 Output buffer turn-off delay from CAS tOFC 0 10 0 13 ns 4,5 2 3 Notes 1. tHPC (MIN.) is applied to CAS access. 2. If tWCS tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle. If tRWD tRWD (MIN.), tCWD tCWD (MIN.), tAWD tAWD (MIN.) and tCPWD tCPWD (MIN.), the cycle is a read modify write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is met, the state of the data out is indeterminate. 3. WE: inactive (in read cycle) CAS: inactive, OE: active ****** tCHO is effective. CAS, OE: active ****** tOCH is effective. 4. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is not referenced to VOH or VOL. 5. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective specification depends on state of each signal. (1) Both RAS and CAS are inactive (at the end of the read cycle) WE: inactive, OE: active tOFC is effective when RAS is inactivated before CAS is inactivated. tOFR is effective when CAS is inactivated before RAS is inactivated. The slower of tOFC and tOFR becomes effective. (2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle) WE, OE: inactive ****** tOEZ is effective. Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle) WE, OE: active and either tRRH or tRCH must be met ****** tWEZ and tWPZ are effective. The faster of tOEZ and tWEZ becomes effective. The faster of (1) and (2) becomes effective. 14 PD4264405, 42S65405, 4265405 Refresh Cycle Parameter tRAC = 50 ns tRAC = 60 ns MIN. MAX. MIN. MAX. Unit Symbol Note CAS setup time tCSR 5 - 5 - ns CAS hold time (CAS before RAS refresh) tCHR 10 - 10 - ns RAS precharge CAS hold time tRPC 5 - 5 - ns RAS pulse width (CAS befoe RAS self refresh) tRASS 100 - 100 - s 1 RAS precharge time (CAS before RAS self refresh) tRPS 90 - 110 - ns 1 CAS hold time (CAS before RAS self refresh) tCHS -50 - -50 - ns 1 WE setup time tWSR 10 - 10 - ns WE hold time tWHR 15 - 15 - ns Note 1. This specification is applied only to the PD42S65405. 15 PD4264405, 42S65405, 4265405 Read Cycle tRC tRAS RAS tRP VIH - VIL - tCSH tCRP CAS tRCD tRSH tCAS VIH - VIL - tRAD tASR Address tCPN VIH - VIL - tRAH tRAL tCAH tASC Row Col. tRCH tRCS WE tRRH VIH - VIL - tWPZ tOCH tOES tCHO tWEZ tOEA OE VIH - VIL - tRAC tAA tCAC tOLZ tCLZ I/O 16 VOH - VOL - Hi - Z tOFC tOEZ tOFR Data out Hi - Z PD4264405, 42S65405, 4265405 Early Write Cycle tRC tRP tRAS RAS VIH- VIL- tCSH tCRP CAS tRSH tRCD tCPN tCAS VIH- VIL- tRAD tASR Address WE I/O VIH- VIL- tRAH tASC Row tCAH Col. tWCS tWCH tDS tDH VIH- VIL- VIH- VIL- Data in Remark OE: Don't care 17 PD4264405, 42S65405, 4265405 Late Write Cycle t RC t RAS RAS t RP VIH- VIL- t CSH t CRP CAS t RCD t RSH t CPN t CAS VIH- VIL- t RAD t ASR Address VIH- VIL- t RAH t ASC Row t CAH Col. t CWL t RWL t RCS WE t WP VIH- VIL- t OEH OE VIH- VIL- t OED I/O 18 VIH- VIL- Hi-Z t DS t DH Data in PD4264405, 42S65405, 4265405 Read Modify Write Cycle t RWC t RAS RAS t RP VIH- VIL- t CSH t CRP CAS t RCD t RSH t CPN t CAS VIH- VIL- t RAD t ASR Address VIH- VIL- t RAH t ASC Row t CAH Col. t RWD t AWD t CWD t RCS WE t CWL t RWL t WP VIH- VIL- t OEA OE VIH- VIL- t RAC t AA t CAC I/O t OEH t OED VIH- VIL- t DS t DH Data in t OLZ t CLZ I/O VOH- VOL- Hi-Z t OEZ Data out Hi-Z 19 PD4264405, 42S65405, 4265405 Hyper Page Mode (EDO) Read Cycle tRASP RAS VIH - VIL - tCSH tCRP CAS tRCD tRSH tHCAS tHPC tHCAS tCP tHCAS tCP VIH - VIL - tRAD tRAH tASC Row tCAH tASC Col. tCAH Col. tRAL tCAH tASC tOFR tOFC Col. tRCH tRRH tRCS WE tCPN VIH - VIL - tASR Address tRP tRHCP tWPZ VIH - VIL - tWEZ OE tOCH tOEA VIH - VIL - tOLZ tRAC tAA tCAC tCLZ I/O VOH - VOL - tACP tAA tCAC Hi - Z tDHC Data out tACP tAA tCAC tDHC Data out tCHO tOEZ Data out Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 20 PD4264405, 42S65405, 4265405 Hyper Page Mode (EDO) Read Cycle (WE Control) t RASP RAS t RP t RHCP VIH - VIL - t RSH t HCAS t CSH t CRP CAS t HCAS t HCAS t CPN VIH - VIL - t ASR Address t RCD VIH - VIL - t RAD t RAH t ASC Row Col. t RAL t ASC tCAH t ASC t CAH Col. tCAH Col. t RCH t WPZ t RCS WE t RCS t RCH t RCH t WPZ t RRH t RCS t WPZ VIH - VIL - t OCH tCHO t OEA tWEZ t OLZ OE VIH - VIL - t RAC t AA t CAC t CLZ I/O VOH - VOL - Hi - Z t OFR t AA t CAC t CLZ t WEZ Data out t OFC t AA Hi - Z t WEZ t CAC t OEZ t CLZ Data out Hi - Z Data out Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 21 PD4264405, 42S65405, 4265405 Hyper Page Mode (EDO) Read Cycle (OE Control) tRASP RAS tRHCP VIH - VIL - tCSH tCRP CAS tRP tRSH tHPC tRCD tHCAS tCP tHCAS tCP tHCAS VIH - VIL - tRAD tASR Address VIH - VIL - tRAH Row tASC tCAH tASC tASC tCAH Col.B tRAC tAA tCAC VIH - VIL - Col.C tRCH tOES tCHO tOEA tOFR tCAH tAA tCAC tRRH tCAC tAA tOCH tOCH OE tOFC tRAL Col.A tRCS WE tCPN tCHO tACP tACP tOEP tOEP tOEP tOCH tCHO VIH - VIL - tCLZ VOH - I/O VOL - Hi - Z tOEA tOLZ tOEA tOLZ tOLZ tOEZ Data out A tCLZ tOEZ Data out B tOEZ Data out B tOEZ Data out C Hi - Z Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 22 PD4264405, 42S65405, 4265405 Hyper Page Mode (EDO) Early Write Cycle tRASP RAS tRP VIH- VIL- tRHCP tCSH tCRP CAS tHPC tRCD tHCAS tCP tHCAS tRSH tCP tHCAS VIH- VIL- tRAL tRAD tASR Address VIH- VIL- WE VIH- VIL- I/O tCPN tRAH tASC Row tCAH tASC Col. tASC Col. tWCS tWCH tDS tDH VIH- VIL- tCAH Data in tWCS tDS tCAH Col. tWCH tWCS tWCH tDH tDS tDH Data in Data in Remarks 1. OE: Don't care 2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 23 PD4264405, 42S65405, 4265405 Hyper Page Mode (EDO) Late Write Cycle t RASP RAS VIH- VIL- t CSH t CRP CAS t RP t RHCP t RCD t HCAS t HPC t HCAS t CP t RSH t HCAS t CP VIH- VIL- t RAD t ASR t RAH Address VIH- VIL- t RAL t ASC Row t CAH t ASC Col. t RCS Col. t WP Col. t RCS t WP t CWL t RWL t RCS t WP VIH- VIL- t OEH t OEH VIH- VIL- t OED I/O t CAH t CWL t OEH OE t ASC t CAH t CWL WE t CPN VIH- VIL- Hi-Z t DS t DH Data in t OED Hi-Z t DS t DH Data in t OED Hi-Z t DS t DH Data in Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 24 PD4264405, 42S65405, 4265405 Hyper Page Mode (EDO) Read Modify Write Cycle t RASP RAS VIH- VIL- t CRP CAS t RP t HPRWC t HCAS t RCD t CP t HCAS t CP t HCAS VIH- VIL- t RAD t ASR t RAH Address VIH- VIL- t RAL t ASC Row t CAH t ASC t ACP t RWD t AWD t CWD t CWL t WP t RCS t CAH Col. t ACP t CPWD t AWD t CWD t CWL t WP t RCS t CWL t RWL t WP t CPWD t AWD t CWD VIH- VIL- t AA t CAC t OEH t OEA t AA t CAC t OEH t OEH t CAC t OEA t OEA VIH- VIL- t CLZ t OLZ VOH- I/O VOL- Hi-Z t CLZ t OED t OEZ t OLZ Hi-Z out t DS I/O t ASC Col. t RAC t AA OE t CAH Col. t RCS WE t CPN VIH- VIL- t OED t CLZ t OEZ t OLZ Hi-Z out t DH in t DS t DH in t OED t OEZ Hi-Z out t DS t DH in Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 25 PD4264405, 42S65405, 4265405 Hyper Page Mode (EDO) Read and Write Cycle tRASP RAS tRP tRHCP VIH - VIL - tCSH tCRP CAS tHCAS tHCAS tCP VIH - VIL - tRAD tRAH tASC Row tCAH Col. tASC Col. Col. tRCH VIH - VIL - tOLZ VOH - VOL - Hi - Z tOEZ tDHC Data out tWEZ Hi - Z Data out tDS I/O tWCH tCHO tACP tAA tCAC tRAC tAA tCAC tCLZ I/O tWCS VIH - VIL - tOCH tOEA OE tCPN tRAL tCAH tASC tCAH tRCS WE tCP VIH - VIL - tASR Address tRSH tHCAS tHPC tRCD VIH - VIL - tDH Data in Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle. 26 PD4264405, 42S65405, 4265405 CAS Before RAS Self Refresh Cycle (Only for the PD42S65405) tRASS RAS tRPS VIH_ VIL_ tCRP tRPC tCHS tCPN tCSR CAS VIH_ VIL_ tWSR tWHR WE VIH_ VIL_ Remark Address, OE: Don't care I/O: Hi-Z Cautions on Use of CAS Before RAS Self Refresh CAS before RAS self refresh can be used independently when used in combination with distributed CAS before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with long RAS only refresh (both distributed and burst), the following cautions must be observed. (1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please perform CAS before RAS refresh 4,096 times within a 64 ms interval just before and after setting CAS before RAS self refresh. (2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only refresh 4,096 times within a 64 ms interval just before and after setting CAS before RAS self refresh. (3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 s), CAS before RAS refresh cycles will be executed one time. If 10 s < tRAS < 100 s, RAS precharge time for CAS before RAS self refresh (tRPS) is applied. And refresh cycles (4,096/128 ms) should be met. For details, please refer to How to use DRAM User's Manual. 27 PD4264405, 42S65405, 4265405 CAS Before RAS Refresh Cycle tRC tRC tRAS RAS tRP tCRP tCHR tRPC tCSR tCHR tWSR tWHR tRPC tCPN VIH- VIL- tWSR WE tRAS VIH- VIL- tCSR CAS tRP tWHR VIH- VIL- Remark Address, OE: Don't care I/O: Hi-Z RAS Only Refresh Cycle tRC tRAS RAS tRC tRP tRAS tRP VIH- VIL- tCRP tRPC tCRP CAS VIH- VIL- tASR Address VIH- VIL- tRAH Row Remark WE, OE: Don't care 28 tASR tRAH Row I/O: Hi-Z tCPN PD4264405, 42S65405, 4265405 Hidden Refresh Cycle (Read) tRC tRC tRAS tRP tRAS tRP VIH - RAS VIL - tCRP CAS tCHR tRSH tCPN VIH - VIL - tASR Address tRCD VIH - VIL - tRAD tRAH tRAL tCAH tASC Row Col. tRCH tRCS WE tWPZ tWHR VIH - VIL - tWEZ tOES tOEA OE tCHO VIH - VIL - tRAC tAA tCAC tOLZ tCLZ I/O VOH - VOL - Hi - Z tOFR tOFC tOEZ Data out Hi - Z 29 PD4264405, 42S65405, 4265405 Hidden Refresh Cycle (Write) tRC tRC tRAS RAS tRAS tRSH tRCD tCHR VIH- VIL- tRAD tASR Address VIH- VIL- tRAH tASC Row tCAH Col. tWCS WE tWCH VIH- VIL- tDS I/O VIH- VIL- Remark OE: Don't care 30 tRP VIH- VIL- tCRP CAS tRP tDH Data in tWSR tWHR tCPN PD4264405, 42S65405, 4265405 Package Drawings 32PIN PLASTIC TSOP(II) (400 mil) 32 17 1 P E F detail of lead end 16 A H J K G I N C D M B L M NOTE Each lead centerline is located within 0.21 mm (0.009 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 21.17 MAX. 0.834 MAX. B 1.075 MAX. 0.043 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.42 +0.08 -0.07 0.0170.003 E 0.10.05 0.0040.002 F 1.2 MAX. 0.048 MAX. G 0.97 0.038 H 11.760.2 0.4630.008 I 10.160.1 0.4000.004 J 0.80.2 0.031 +0.009 -0.008 K 0.145 +0.025 -0.015 0.0060.001 L 0.50.1 0.020 +0.004 -0.005 M 0.21 0.009 N 0.10 0.004 P 3 +7 -3 3 +7 -3 S32G5-50-7JD2 31 PD4264405, 42S65405, 4265405 32 PIN PLASTIC SOJ (400 mil) 17 1 16 C 32 D B E H G U J F I T K Q M P N M P32LE-400A NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maxi- mum material condition. 32 ITEM MILLIMETERS INCHES B 21.06 0.2 0.829 0.008 C 10.16 0.400 D 11.18 0.2 0.440 0.008 E 1.005 0.1 0.040 -0.005 F 0.74 0.029 G 3.5 0.2 0.138 0.008 H 2.545 0.2 0.100 0.008 I 0.8 MIN. 0.031 MIN. J 2.6 0.102 K 1.27 (T.P.) 0.050 (T.P.) M 0.40 0.10 0.016 +0.004 -0.005 N 0.12 0.005 P 9.4 0.20 0.370 0.008 Q 0.1 0.004 T R 0.85 R 0.033 U +0.10 0.20 -0.05 0.008+0.004 -0.002 +0.004 PD4264405, 42S65405, 4265405 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD4264405, 42S65405, 4265405. Types of Surface Mount Device PD4264405G5-7JD, 42S65405G5-7JD, 4265405G5-7JD: 32-pin plastic TSOP (II) (400 mil) PD4264405LE, 42S65405LE, 4265405LE: 32-pin plastic SOJ (400 mil) 33 PD4264405, 42S65405, 4265405 [MEMO] 34 PD4264405, 42S65405, 4265405 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 35 PD4264405, 42S65405, 4265405 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2