©
1995
DATA SHEET
MOS INTEGRATED CIRCUIT
64 M-BIT DYNAMIC RAM
16 M-WORD BY 4-BIT, EDO
Description
The
µ
PD4264405, 42S65405, 4265405 are 16,777,216 words by 4 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the
µ
PD42S65405 can execute CAS before RAS self refresh.
These are packaged in 32-pin plastic TSOP (II) and 32-pin plastic SOJ.
Features
• EDO (Hyper page mode)
• 16,777,216 words by 4 bits organization
• Single +3.3 V ± 0.3 V power supply
• Fast access and cycle time
The information in this document is subject to change without notice.
Document No. M10856EJ6V0DS00 (6th edition)
Date Published September 1997 N
Printed in Japan
µ
PD4264405, 42S65405, 4265405
Part number Power consumption Access time R/W cycle time EDO (Hyper page mode)
Active (MAX.) (MAX.) (MIN.) cycle time (MIN.)
µ
PD4264405-A50 360 mW 50 ns 84 ns 20 ns
µ
PD42S65405-A50, 4265405-A50 468 mW
µ
PD4264405-A60 324 mW 60 ns 104 ns 25 ns
µ
PD42S65405-A60, 4265405-A60 396 mW
• The
µ
PD42S65405 can execute CAS before RAS self refresh.
Part number Refrech cycle Refresh Power consumption
at standby (MAX.)
µ
PD42S65405 4,096 cycles/128 ms RAS only refresh, Normal read/write,
CAS before RAS self refresh,
CAS before RAS refresh, Hidden refresh
µ
PD4264405 8,192 cycles/64 ms RAS only refresh, Normal read/write 1.8 mW
4,096 cycles/64 ms CAS before RAS refresh, Hidden refresh (CMOS level input)
µ
PD4265405 4,096 cycles/64 ms RAS only refresh, Normal read/write,
CAS before RAS refresh, Hidden refresh
The mark shows major revised points.
0.72 mW
(CMOS level input)
µ
PD4264405, 42S65405, 4265405
2
Ordering Information
Part number Access time Package Refresh
(MAX.)
µ
PD42S65405G5-A50-7JD 50 ns 32-pin plastic TSOP (II) CAS before RAS self refresh
µ
PD42S65405G5-A60-7JD 60 ns (400 mil) CAS before RAS refresh
µ
PD42S65405LE-A50 50 ns 32-pin plastic SOJ RAS only refresh
µ
PD42S65405LE-A60 60 ns (400 mil) Hidden refresh
µ
PD4264405G5-A50-7JD 50 ns 32-pin plastic TSOP (II) CAS before RAS refresh
µ
PD4264405G5-A60-7JD 60 ns (400 mil) RAS only refresh
µ
PD4265405G5-A50-7JD 50 ns Hidden refresh
µ
PD4265405G5-A60-7JD 60 ns
µ
PD4264405LE-A50 50 ns 32-pin plastic SOJ
µ
PD4264405LE-A60 60 ns (400 mil)
µ
PD4265405LE-A50 50 ns
µ
PD4265405LE-A60 60 ns
µ
PD4264405, 42S65405, 4265405
3
Pin Configurations (Marking Side)
32-pin Plastic TSOP (II) (400 mil) 32-pin Plastic SOJ (400 mil)
µ
PD4264405G5-7JD
µ
PD4264405LE
µ
PD42S65405G5-7JD
µ
PD42S65405LE
µ
PD4265405G5-7JD
µ
PD4265405LE
V
CC
I/O1
I/O2
NC
NC
NC
NC
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
I/O4
I/O3
NC
NC
NC
CAS
OE
A12/NC
Note
A11
A10
A9
A8
A7
A6
GND
V
CC
I/O1
I/O2
NC
NC
NC
NC
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
I/O4
I/O3
NC
NC
NC
CAS
OE
A12/NC
Note
A11
A10
A9
A8
A7
A6
GND
Note A12 ...
µ
PD4264405
NC ...
µ
PD42S65405, 4265405
A0 to A12 : Address Inputs
I/O1 to I/O4 : Data Inputs/Outputs
RAS : Row Address Strobe
CAS : Column Address Strobe
WE : Write Enable
OE : Output Enable
VCC : Power Supply
GND : Ground
NC : No Connection
µ
PD4264405, 42S65405, 4265405
4
Block Diagram
Notes 1. Part number Row address Column address
µ
PD4264405 A0 - A12 A0 - A10
µ
PD42S65405, 4265405 A0 - A11 A0 - A11
2. 4,096 × 4,096 × 4
Clock
Generator
CAS before
RAS Counter
RAS
CAS
WE
V
CC
GND
Address
Note 1
Row Decoder
Row
Address
Buffer
Column
Address
Buffer
Memory
Cell
Array
Bit organization
Note2
Sense Amplifier
Column Decoder
Data
Output
Buffer
Data
Input
Buffer
× 4
OE
I/O1
to
I/O4
µ
PD4264405, 42S65405, 4265405
5
Input/Output Function
Input RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS self refresh, CAS before RAS refresh
Input CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.
Input Address bus.
Input total 24-bit of address signal, upper bits and lower bitsNote in sequence
(address multiplex method).
Therefore, one word is selected from 16,777,216-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.
Input Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Input Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
Input/Output 4-bit data bus.
I/O1 to I/O4 are used to input/output data.
Pin name
RAS
(Row address strobe)
CAS
(Column address strobe)
A0 to A×Note
(Address inputs)
WE
(Write enable)
OE
(Output enable)
I/O1 to I/O4
(Data inputs/outputs)
Input/Output Pin Functions
The
µ
PD4264405, 42S65405, 4265405 have input pins RAS, CAS, WE, OE, AddressNote and input/output
pins I/O1 to I/O4.
Note Part number Address inputs Upper bits Lower bits
µ
PD4264405 A0 - A12 13 11
µ
PD42S65405, 4265405 A0 - A11 12 12
µ
PD4264405, 42S65405, 4265405
6
Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.
1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle’s falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.
2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO) , read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.
Hyper Page Mode (EDO) Read Cycle
t
HPC
t
OEA
t
OEZ
t
AA
Hi - Z
Hi - Z
Row Col.A Col.B Col.C
t
OEA
t
OLZ
RAS V
IH
–
V
IL
–
CAS V
IH
–
V
IL
–
Address V
IH
–
V
IL
–
V
IH
–
V
IL
–
OE V
IH
–
V
IL
–
I/O V
OH
–
V
OL
–Data out A Data out B Data out C Data out C
t
OEZ
t
AA
t
CAC
t
OEZ
t
OEP
t
OEP
t
OCH
t
CHO
t
CHO
WE
t
RAC
t
AA
t
CAC
t
CLZ
t
CAC
t
CLZ
t
WPZ
t
DHC
t
OFC
t
OFR
t
WEZ
t
OCH
t
RRH
t
RCH
µ
PD4264405, 42S65405, 4265405
7
Cautions when using the hyper page mode (EDO)
1. CAS access should be used to operate tHPC at the MIN. value.
2. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
The slower of tOFC and tOFR becomes effective.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ····· tOEZ is effective.
Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ····· tWEZ and tWPZ are effective.
The faster of tOEZ and tWEZ becomes effective.
The faster of (1) and (2) becomes effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ····· tCHO is effective.
(2) CAS, OE: active ····· tOCH is effective.
µ
PD4264405, 42S65405, 4265405
8
Electrical Specifications
• All voltages are referenced to GND.
• After power up (VCC ≥ VCC(MIN.)), wait more than 100
µ
s (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on any pin relative to GND VT–0.5 to +4.6 V
Supply voltage VCC –0.5 to +4.6 V
Output current IO50 mA
Power dissipation PD1W
Operating ambient temperature TA0 to +70 ˚ C
Storage temperature Tstg –55 to +125 ˚ C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VCC 3.0 3.3 3.6 V
High level input voltage VIH 2.0 VCC + 0.3 V
Low level input voltage VIL –0.3 +0.8 V
Operating ambient temperature TA070˚C
Capacitance (TA = 25 ˚C, f = 1 MHZ)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance CI1 Address 5 pF
CI2 RAS, CAS, WE, OE 7
Data input/output capacitance CI/O I/O 7 pF
µ
PD4264405, 42S65405, 4265405
9
DC Characteristics (Recommended operating conditions unless otherwise noted)
[
µ
PD4264405]
Parameter Symbol Test condition MIN. MAX. Unit Notes
Operating current ICC1 RAS, CAS cycling tRAC = 50 ns 100 mA
1, 2, 3
tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 90
Standby current ICC2 RAS, CAS ≥ VIH (MIN.), IO = 0 mA 1.0 mA
RAS, CAS ≥ VCC – 0.2 V, IO = 0 mA 0.5
RAS only refresh current ICC3 RAS cycling, CAS ≥ VIH (MIN.) tRAC = 50 ns 100 mA
1, 2, 3 ,4
tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 90
Operating current ICC4 RAS ≤ VIL (MAX.), CAS cycling tRAC = 50 ns 100 mA 1, 2, 5
(Hyper page mode (EDO)) tHPC = tHPC (MIN.), IO = 0 mA tRAC = 60 ns 90
CAS before RAS ICC5 RAS cycling tRAC = 50 ns 130 mA 1, 2
refresh current tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 110
Input leakage current II (L) VI = 0 to 3.6 V –5 +5
µ
A
All other pins not under test = 0 V
Output leakage current IO (L) VO = 0 to 3.6 V –5 +5
µ
A
Output is disabled (Hi-Z)
High level output voltage VOH IO = –2.0 mA 2.4 V
Low level output voltage VOL IO = +2.0 mA 0.4 V
µ
PD4264405, 42S65405, 4265405
10
[
µ
PD42S65405, 4265405]
Parameter Symbol Test condition MIN. MAX. Unit Notes
Operating current ICC1 RAS, CAS cycling tRAC = 50 ns 130 mA
1, 2, 3
tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 110
Standby
µ
PD42S65405 ICC2 RAS, CAS ≥ VIH (MIN.), IO = 0 mA 1.0 mA
current RAS, CAS ≥ VCC – 0.2 V, IO = 0 mA 0.2
µ
PD4265405 RAS, CAS ≥ VIH (MIN.), IO = 0 mA 1.0
RAS, CAS ≥ VCC – 0.2 V, IO = 0 mA 0.5
RAS only refresh current ICC3 RAS cycling, CAS ≥ VIH (MIN.) tRAC = 50 ns 130 mA
1, 2, 3 ,4
tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 110
Operating current ICC4 RAS ≤ VIL (MAX.), CAS cycling tRAC = 50 ns 100 mA 1, 2, 5
(Hyper page mode (EDO)) tHPC = tHPC (MIN.), IO = 0 mA tRAC = 60 ns 90
CAS before RAS ICC5 RAS cycling tRAC = 50 ns 130 mA 1, 2
refresh current tRC = tRC (MIN.), IO = 0 mA tRAC = 60 ns 110
CAS before RAS ICC6 CAS before RAS refresh: tRAS ≤ 300 ns 500
µ
A 1, 2
long refresh current tRC = 31.3
µ
s
(4,096 cycles/128 ms, RAS, CAS:
only for the
µ
PD42S65405) VCC – 0.2 V ≤ VIH ≤ VIH (MAX.)
0 V ≤ VIL ≤ 0.2 V
Standby: tRAS ≤ 1
µ
s 600
µ
A 1, 2
RAS, CAS ≥ VCC – 0.2 V
Address: VIH or VIL
WE, OE: VIH
IO = 0 mA
CAS before RAS ICC7 RAS, CAS: 400
µ
A2
self refresh current tRASS = 5 ms
(only for the
µ
PD42S65405) VCC – 0.2 V ≤ VIH ≤ VIH (MAX.)
0 V ≤ VIL ≤ 0.2 V
IO = 0 mA
Input leakage current II (L) VI = 0 to 3.6 V –5 +5
µ
A
All other pins not under test = 0 V
Output leakage current IO (L) VO = 0 to 3.6 V –5 +5
µ
A
Output is disabled (Hi-Z)
High level output voltage VOH IO = –2.0 mA 2.4 V
Low level output voltage VOL IO = +2.0 mA 0.4 V
Notes 1. ICC1, ICC3, ICC4, ICC5 and ICC6 depend on cycle rates (tRC and tHPC).
2. Specified values are obtained with outputs unloaded.
3. ICC1 and ICC3 are measured assuming that address can be changed once or less during RAS ≤ VIL (MAX.)
and CAS ≥ VIH (MIN.).
4. ICC3 is measured assuming that all column address inputs are held at either high or low.
5. ICC4 is measured assuming that all column address inputs are switched only once during each hyper page
(EDO) cycle.
µ
PD4264405, 42S65405, 4265405
11
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification (2) Output timing specification
(3) Output load condition
V
CC
1,180 Ω
870 Ω
100 pF
I/O
C
L
Common to Read, Write, Read Modify Write Cycle
Parameter Symbol tRAC = 50 ns tRAC = 60 ns Unit
Notes
MIN. MAX. MIN. MAX.
Read / Write cycle time tRC 84 – 104 – ns
RAS precharge time tRP 30 – 40 – ns
CAS precharge time tCPN 7–10–ns
RAS pulse width tRAS 50 10,000 60 10,000 ns 1
CAS pulse width tCAS 8 10,000 10 10,000 ns
RAS hold time tRSH 13 – 15 – ns
CAS hold time tCSH 38 – 40 – ns
RAS to CAS delay time tRCD 11 37 14 45 ns 2
RAS
to column address delay time
tRAD 9 251230ns2
CAS to RAS precharge time tCRP 5–5–ns3
Row address setup time tASR 0–0–ns
Row address hold time tRAH 7–10–ns
Column address setup time tASC 0–0–ns
Column address hold time tCAH 7–10–ns
OE lead time referenced to RAS tOES 0–0–ns
CAS to data setup time tCLZ 0–0–ns
OE to data setup time tOLZ 0–0–ns
OE to data delay time tOED 10 – 13 – ns
Transition time (rise and fall) tT1 50 1 50 ns
Refresh time
µ
PD42S65405 tREF – 128 – 128 ms 4
µ
PD4264405, 4265405 – 64 – 64 ms
V
IH (MIN.)
= 2.0 V
V
IL (MAX.)
= 0.8 V
V
OH (MIN.)
= 2.0 V
V
OL (MAX.)
= 0.8 V
t
T
= 2 ns t
T
= 2 ns
µ
PD4264405, 42S65405, 4265405
12
Notes 1. In CAS before RAS refresh cycles, tRAS(MAX) is 100
µ
s.
If 10
µ
s < tRAS < 100
µ
s, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions Access time Access time from RAS
tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tRAC (MAX.) tRAC (MAX.)
tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tAA (MAX.) tRAD + tAA (MAX.)
tRCD > tRCD (MAX.) tCAC (MAX.) tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only ; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ≥ tRAD (MAX.) and tRCD ≥ tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the
µ
PD42S65405.
Read Cycle
Parameter Symbol tRAC = 50 ns tRAC = 60 ns Unit
Notes
MIN. MAX. MIN. MAX.
Access time from RAS tRAC – 50 – 60 ns 1
Access time from CAS tCAC – 13 – 15 ns 1
Access time from column address
tAA – 25 – 30 ns 1
Access time from OE
tOEA – 13 – 15 ns
Column address lead time referenced to RAS tRAL 25 – 30 – ns
Read command setup time tRCS 0–0–ns
Read command hold time referenced to RAS tRRH 0–0–ns2
Read command hold time referenced to CAS tRCH 0–0–ns2
Output buffer turn-off delay time from OE tOEZ 0 10 0 13 ns 3
CAS hold time to OE tCHO 5–5–ns4
Notes 1. For read cycles, access time is defined as follows:
Input conditions Access time Access time from RAS
tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tRAC (MAX.) tRAC (MAX.)
tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tAA (MAX.) tRAD + tAA (MAX.)
tRCD > tRCD (MAX.) tCAC (MAX.) tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ≥ tRAD (MAX.) and tRCD ≥ tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.
4. WE: inactive (in read cycle)
CAS: inactive, OE: active ··· tCHO is effective.
CAS, OE: active ··· tOCH is effective.
µ
PD4264405, 42S65405, 4265405
13
Write Cycle
Parameter Symbol tRAC = 50 ns tRAC = 60 ns Unit
Notes
MIN. MAX. MIN. MAX.
WE hold time referenced to CAS tWCH 7–10–ns1
WE pulse width tWP 7–10–ns1
WE lead time referenced to RAS tRWL 13 – 15 – ns
WE lead time referenced to CAS tCWL 7–10–ns
WE setup time tWCS 0–0–ns2
OE hold time tOEH 0–0–ns
Data-in setup time tDS 0–0–ns3
Data-in hold time tDH 7–10–ns3
Notes 1. tWP (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter Symbol tRAC = 50 ns tRAC = 60 ns Unit
Note
MIN. MAX. MIN. MAX.
Read modify write cycle time tRWC 107 – 133 – ns
RAS to WE delay time tRWD 64 – 77 – ns 1
CAS to WE delay time tCWD 27 – 32 – ns 1
Column address to WE delay time
tAWD 39 – 47 – ns 1
Note 1. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ≥ tRWD (MIN.), tCWD ≥ tCWD (MIN.), tAWD ≥ tAWD (MIN.) and tCPWD ≥ tCPWD (MIN.) , the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
µ
PD4264405, 42S65405, 4265405
14
Hyper Page Mode (EDO)
Parameter Symbol tRAC = 50 ns tRAC = 60 ns Unit
Notes
MIN. MAX. MIN. MAX.
Read / Write cycle time tHPC 20 – 25 – ns 1
RAS pulse width tRASP 50
125,000
60
125,000
ns
CAS pulse width tHCAS 8 10,000 10 10,000 ns
CAS precharge time tCP 7–10–ns
Access time from CAS precharge tACP – 30 – 35 ns
CAS precharge to WE delay time tCPWD 41 – 52 – ns 2
RAS hold time from CAS precharge tRHCP 30 – 35 – ns
Read modify write cycle time tHPRWC 52 – 66 – ns
Data output hold time tDHC 5–5–ns
OE to CAS hold time tOCH 5–5–ns3
OE precharge time tOEP 5–5–ns
Output buffer turn-off delay from WE tWEZ 0 10 0 13 ns 4,5
WE pulse width tWPZ 7–10–ns5
Output buffer turn-off delay from RAS tOFR 0 10 0 13 ns 4,5
Output buffer turn-off delay from CAS tOFC 0 10 0 13 ns 4,5
Notes 1. tHPC (MIN.) is applied to CAS access.
2. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If tRWD ≥ tRWD (MIN.), tCWD ≥ tCWD (MIN.), tAWD ≥ tAWD (MIN.) and tCPWD ≥ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. WE: inactive (in read cycle)
CAS: inactive, OE: active ······ tCHO is effective.
CAS, OE: active ······ tOCH is effective.
4. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
5. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1) Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
The slower of tOFC and tOFR becomes effective.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ······ tOEZ is effective.
Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ······ tWEZ and tWPZ are effective.
The faster of tOEZ and tWEZ becomes effective.
The faster of (1) and (2) becomes effective.
µ
PD4264405, 42S65405, 4265405
15
Refresh Cycle
Parameter Symbol tRAC = 50 ns tRAC = 60 ns Unit
Note
MIN. MAX. MIN. MAX.
CAS setup time tCSR 5–5–ns
CAS hold time (CAS before RAS refresh) tCHR 10 – 10 – ns
RAS precharge CAS hold time tRPC 5–5–ns
RAS pulse width (CAS befoe RAS self refresh) tRASS 100 – 100 –
µ
s1
RAS precharge time (CAS before RAS self refresh) tRPS 90 – 110 – ns 1
CAS hold time (CAS before RAS self refresh) tCHS –50 – –50 – ns 1
WE setup time
tWSR 10 – 10 – ns
WE hold time tWHR 15 – 15 – ns
Note 1. This specification is applied only to the
µ
PD42S65405.
µ
PD4264405, 42S65405, 4265405
16
Read Cycle
t
RC
t
RAS
t
RP
V
IH
–
V
IL
–
RAS
t
OFR
Hi - Z
t
CSH
Data out
V
IH
–
V
IL
–
CAS
V
IH
–
V
IL
–
Address
V
IH
–
V
IL
–
WE
V
IH
–
V
IL
–
OE
V
OH
–
V
OL
–
I/O Hi - Z
t
OFC
t
OEZ
t
CLZ
t
OLZ
t
CAC
t
AA
t
RAC
t
OEA
t
WEZ
t
WPZ
t
RRH
t
RCS
Row Col.
t
CAH
t
ASC
t
RAH
t
ASR
t
RAD
t
CRP
t
RCD
t
RSH
t
CAS
t
CPN
t
RAL
t
RCH
t
CHO
t
OES
t
OCH
µ
PD4264405, 42S65405, 4265405
17
Early Write Cycle
RAS
tRAS
tRC
tRP
tCSH
tRSH
tRCD
tCAS
tCPN
tCRP
tRAD
tASR tRAH tASC tCAH
Row Col.
tWCS
VIH–
VIL–
CAS VIH–
VIL–
Address VIH–
VIL–
WE VIH–
VIL–
Data in
I/O VIH–
VIL–
tDS
tWCH
tDH
Remark OE: Don’t care
µ
PD4264405, 42S65405, 4265405
18
Late Write Cycle
I/O
RAS VIH–
VIL–
WE VIH–
VIL–
tRAS tRP
tRC
CAS VIH–
VIL–
tCSH
tRCDtCRP tRSH
tCAS
tCPN
Address VIH–
VIL–
tASR tRAH tASC tCAH
tRAD
Row Col.
tRCS
OE VIH–
VIL–
VIH–
VIL–
tCWL
tOED
Data in
Hi-Z
tRWL
tWP
tOEH
tDS tDH
µ
PD4264405, 42S65405, 4265405
19
Read Modify Write Cycle
I/O
RAS V
IH–
V
IL–
WE V
IH–
V
IL–
t
RAS
t
RP
t
RWC
CAS V
IH–
V
IL–
t
CSH
t
RCD
t
CRP
t
RSH
t
CAS
t
CPN
Address V
IH–
V
IL–
t
ASR
t
RAH
t
ASC
t
CAH
t
RAD
Row Col.
t
RCS
OE V
IH–
V
IL–
V
IH–
V
IL–
t
RWD
t
CAC
Data in
t
AWD
t
CWD
t
DS
t
DH
t
WP
t
RWL
t
CWL
t
AA
t
RAC
t
OED
t
OEA
t
OEH
I/O V
OH–
V
OL–
Data out Hi-ZHi-Z
t
OEZ
t
CLZ
t
OLZ
µ
PD4264405, 42S65405, 4265405
20
Hyper Page Mode (EDO) Read Cycle
RAS
CAS
Address
WE
OE
I/O
t
RASP
t
RP
t
CRP
t
RCD
t
HCAS
t
CSH
t
CP
t
RHCP
t
RSH
t
HCAS
t
CPN
t
HCAS
t
HPC
t
CP
t
ASR
t
RAH
t
ASC
t
RAD
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WPZ
t
WEZ
t
OEZ
t
ACP
t
AA
t
CAC
t
ACP
t
AA
t
CAC
t
DHC
t
DHC
t
OEA
t
OLZ
t
RAC
t
AA
t
CAC
t
CLZ
Row Col. Col. Col.
Data out Data out Data out
Hi - Z
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
OH
–
V
OL
–
t
OFR
t
OFC
t
CHO
t
OCH
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
µ
PD4264405, 42S65405, 4265405
21
Hyper Page Mode (EDO) Read Cycle (WE Control)
RAS
CAS
Address
WE
OE
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
OH
–
V
OL
–
t
RASP
t
RP
t
CRP
t
RCD
t
HCAS
t
CSH
t
RHCP
t
RSH
t
HCAS
t
CPN
t
HCAS
t
ASR
t
RAH
t
ASC
t
RAD
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RRH
t
WPZ
t
OFR
t
OFC
t
OEZ
t
AA
t
AA
t
CLZ
t
CAC
t
CAC
t
CLZ
t
WEZ
t
WEZ
t
OEA
t
OLZ
t
RAC
t
AA
t
CAC
t
CLZ
Row Col. Col. Col.
Data out Data out Data out
Hi - Z
I/O
t
RCH
t
WPZ
t
RCS
t
RCH
t
WPZ
t
RCS
t
RCH
Hi - Z Hi - Z
t
WEZ
t
CHO
t
OCH
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
µ
PD4264405, 42S65405, 4265405
22
Hyper Page Mode (EDO) Read Cycle (OE Control)
t
RASP
t
RHCP
t
RP
t
CSH
t
HPC
t
RSH
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RCS
t
RCH
t
RRH
t
OEA
t
OEZ
t
AA
Hi - Z
Hi - Z
Row Col.A Col.B Col.C
t
OEA
t
ACP
t
OES
t
OLZ
t
CRP
t
RCD
t
HCAS
t
CP
t
HCAS
t
CP
t
HCAS
t
CPN
RAS
CAS
Address
OE
I/O
Data out A Data out B Data out B Data out C
t
OFC
t
OEZ
t
OFR
t
OEA
t
ACP
t
OCH
t
OLZ
t
AA
t
CAC
t
OEZ
t
OEZ
t
OEP
t
OEP
t
OEP
t
OCH
t
OCH
t
CHO
t
CHO
t
CHO
WE
t
RAC
t
AA
t
CAC
t
CLZ
t
CAC
t
CLZ
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
OH
–
V
OL
–
t
OLZ
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
µ
PD4264405, 42S65405, 4265405
23
Hyper Page Mode (EDO) Early Write Cycle
RAS
t
RASP
V
IH–
V
IL–
CAS V
IH–
V
IL–
Address V
IH–
V
IL–
WE V
IH–
V
IL–
I/O V
IH–
V
IL–
t
RP
t
RHCP
t
RSH
t
HPC
t
CPN
t
CSH
t
HCAS
t
CP
t
HCAS
t
HCAS
t
CP
t
RAL
t
CAH
t
CAH
t
ASC
t
CAH
Col. Col.Row
t
ASR
t
RAH
t
WCS
t
WCS
t
RCD
t
RAD
t
ASC
Col.
t
WCH
t
WCH
t
WCH
Data in Data inData in
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
WCS
t
ASC
t
CRP
Remarks 1. OE: Don’t care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
µ
PD4264405, 42S65405, 4265405
24
Hyper Page Mode (EDO) Late Write Cycle
CAS V
IH–
V
IL–
t
CPN
t
CP
t
CP
t
CSH
t
HCAS
t
RCD
RAS V
IH–
V
IL–
t
RASP
t
RP
t
CRP
t
HPC
t
RSH
t
RHCP
t
HCAS
t
HCAS
Row Col.
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
ASC
Col.
t
CAH
t
ASC
Col.
t
CAH
t
RAL
Address V
IH–
V
IL–
WE V
IH–
V
IL–
t
RCS
t
CWL
t
WP
t
RCS
t
CWL
t
WP
t
RCS
t
CWL
t
WP
t
RWL
OE V
IH–
V
IL–
t
OEH
t
OEH
t
OEH
I/O V
IH–
V
IL–
t
OED
t
DS
t
DH
Hi-Z Data in
t
OED
t
DS
t
DH
Data in
Hi-Z
t
OED
t
DS
t
DH
Data in
Hi-Z
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
µ
PD4264405, 42S65405, 4265405
25
Hyper Page Mode (EDO) Read Modify Write Cycle
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
t
RCS
CAS V
IH–
V
IL–
t
CPN
t
CP
t
HCAS
t
HCAS
t
CP
t
HPRWC
t
HCAS
t
RCD
RAS V
IH–
V
IL–
t
RASP
t
RP
t
CRP
Address V
IH–
V
IL–
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
ASC
t
CAH
t
CAH
t
ASC
Row Col. Col. Col.
t
RAL
WE V
IH–
V
IL–
t
RWD
t
OLZ
I/O V
IH–
V
IL–
t
DH
t
DS
t
AWD
t
CWD
t
WP
t
RCS
t
CWL
t
ACP
t
CPWD
t
AWD
t
CWD
tWP
t
CWL
t
ACP
t
CPWD
t
AWD
t
CWD
tRCS
tCWL
tRWL
tWP
OE V
IH–
V
IL–
I/O V
OH–
V
OL–
out
t
OEZ
t
CLZ
t
OED
t
OEA
t
CAC
t
AA
t
RAC
in
t
OEA
t
OEH
t
CAC
t
AA
t
OLZ
t
DH
t
DS
out
t
OEZ
t
CLZ
t
OED
in
t
OLZ
t
DH
t
DS
out
t
OEZ
t
CLZ
t
OED
in
t
OEH
t
AA
t
CAC
t
OEA
t
OEH
Hi-Z Hi-Z Hi-Z Hi-Z
µ
PD4264405, 42S65405, 4265405
26
Hyper Page Mode (EDO) Read and Write Cycle
V
IH
–
V
IL
–
RAS
V
IH
–
V
IL
–
CAS
V
IH
–
V
IL
–
Address
V
IH
–
V
IL
–
WE
V
IH
–
V
IL
–
OE
V
OH
–
V
OL
–
I/O
t
RASP
t
RP
t
CRP
t
RCD
t
HCAS
t
CSH
t
CP
t
RHCP
t
RSH
t
HCAS
t
CPN
t
HCAS
t
HPC
t
CP
t
ASR
t
RAH
t
ASC
t
RAD
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
ACP
t
AA
t
CAC
t
WEZ
t
DHC
t
OEA
t
RAC
t
AA
t
CAC
t
CLZ
Row Col. Col. Col.
Data out Data out
Hi - Z
t
OEZ
t
WCS
t
WCH
Hi - Z
t
DH
t
DS
Data in
I/O V
IH
–
V
IL
–
t
CHO
t
OLZ
t
OCH
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
µ
PD4264405, 42S65405, 4265405
27
CAS Before RAS Self Refresh Cycle (Only for the
µ
PD42S65405)
Remark Address, OE: Don’t care I/O: Hi-Z
RAS
CAS
WE
V
IH_
V
IL_
V
IH_
V
IL_
V
IH_
V
IL_
t
CSR
t
WSR
t
WHR
t
RASS
t
RPS
t
CRP
t
RPC
t
CHS
t
CPN
Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 4,096 times within a 64 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 4,096 times within a 64 ms interval just before and after setting CAS before RAS self refresh.
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100
µ
s), CAS before
RAS refresh cycles will be executed one time.
If 10
µ
s < tRAS < 100
µ
s, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (4,096/128 ms) should be met.
For details, please refer to How to use DRAM User’s Manual.
µ
PD4264405, 42S65405, 4265405
28
CAS Before RAS Refresh Cycle
RAS
tRC
VIH–
VIL–
CAS VIH–
VIL–
VIH–
VIL–
tWHR
tCSR tCHR tRPC tCSR tCHR tRPC tCPN
tCRP
tRAS tRP tRPtRAS
tWSR
WE
tRC
tWSR tWHR
Remark Address, OE: Don’t care I/O: Hi-Z
RAS Only Refresh Cycle
RAS
t
RC
V
IH–
V
IL–
CAS V
IH–
V
IL–
t
ASR
t
CRP
t
RPC
t
CPN
t
CRP
t
RAS
t
RP
t
RP
t
RAS
t
ASR
t
RC
Row
Address V
IH–
V
IL–
t
RAH
t
RAH
Row
Remark WE, OE: Don’t care I/O: Hi-Z
µ
PD4264405, 42S65405, 4265405
29
Hidden Refresh Cycle (Read)
t
RC
t
RC
t
RAS
t
RP
t
RAD
t
RAL
t
ASR
t
RAH
Row Col.
Data out Hi - Z
Hi - Z
t
ASC
t
RCS
t
WHR
t
OES
t
OEA
t
RAC
t
AA
t
CAC
t
OLZ
t
CLZ
t
OFC
t
OEZ
t
CAH
t
RP
t
RAS
t
CRP
t
RCD
t
RSH
t
CPN
t
CHR
RAS V
IH
–
V
IL
–
CAS V
IH
–
V
IL
–
WE V
IH
–
V
IL
–
OE V
IH
–
V
IL
–
I/O V
OH
–
V
OL
–
Address V
IH
–
V
IL
–
t
WEZ
t
CHO
t
OFR
t
WPZ
t
RCH
µ
PD4264405, 42S65405, 4265405
30
Hidden Refresh Cycle (Write)
RAS
t
RAS
t
RC
t
RAS
t
CHR
t
RCD
t
CPN
t
CRP
t
RAD
t
ASC
t
CAH
Row Col.
V
IH–
V
IL–
CAS V
IH–
V
IL–
Address V
IH–
V
IL–
WE V
IH–
V
IL–
I/O
t
RP
t
RC
t
RP
t
RSH
t
ASR
t
RAH
t
DS
t
DH
t
WCS
t
WCH
Data in
V
IH–
V
IL–
t
WSR
t
WHR
Remark OE: Don’t care
µ
PD4264405, 42S65405, 4265405
31
Package Drawings
32PIN PLASTIC TSOP(II) (400 mil)
ITEM MILLIMETERS INCHES
A
B
C
E
F
G
I
1.27 (T.P.)
1.2 MAX.
0.97
M
N 0.10
10.16±0.1
0.21
0.1±0.05 0.004±0.002
0.048 MAX.
0.038
0.400±0.004
0.009
0.004
0.050 (T.P.)
H 11.76±0.2 0.463±0.008
D 0.42 0.017±0.003
J 0.8±0.2 0.031+0.009
–0.008
K 0.145 0.006±0.001
L 0.5±0.1 0.020+0.004
–0.005
S32G5-50-7JD2
P3°
+7°
–3°
+0.025
–0.015
+0.08
–0.07
3°+7°
–3°
detail of lead end
DM
M
F
A
L
K
I
H
J
E
P
NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.
CNB
G
32 17
116
21.17 MAX.
1.075 MAX. 0.834 MAX.
0.043 MAX.
µ
PD4264405, 42S65405, 4265405
32
M
N
K
M
I
H
Q
17
16
32
1
F
J
G
E
T
P
U
P32LE-400A
ITEM MILLIMETERS INCHES
B
C
D
E
F
G
H
I
J
K
21.06±0.2
11.18±0.2
1.005±0.1
0.74
3.5±0.2
2.545±0.2
0.8 MIN.
10.16
0.829±0.008
0.440±0.008
0.029
0.138±0.008
0.031 MIN.
0.102
0.400
NOTE
P
Q 0.1
9.4±0.20
0.12
0.40±0.10
1.27 (T.P.)
2.6
0.040
+0.004
–0.005
0.050 (T.P.)
0.100±0.008
0.370±0.008
0.004
0.005
0.016
Each lead centerline is located within 0.12 mm
(0.005 inch) of its true position (T.P.) at maxi–
mum material condition.
+0.004
–0.005
M
N
T
U 0.20
R 0.85 R 0.033
0.008
+0.10
–0.05 +0.004
–0.002
32 PIN PLASTIC SOJ (400 mil)
C
D
B
µ
PD4264405, 42S65405, 4265405
33
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD4264405, 42S65405, 4265405.
Types of Surface Mount Device
µ
PD4264405G5-7JD, 42S65405G5-7JD, 4265405G5-7JD: 32-pin plastic TSOP (II) (400 mil)
µ
PD4264405LE, 42S65405LE, 4265405LE: 32-pin plastic SOJ (400 mil)
µ
PD4264405, 42S65405, 4265405
34
[MEMO]
µ
PD4264405, 42S65405, 4265405
35
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
µ
PD4264405, 42S65405, 4265405
2
[MEMO]
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consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
