PD - 94646A IRF7413Z HEXFET(R) Power MOSFET Applications l Control FET for Notebook Processor Power l Control and Synchronous Rectifier MOSFET for Graphics Cards and POL Converters in Computing, Networking and Telecommunication Systems Benefits l Ultra-Low Gate Impedance l Very Low RDS(on) l Fully Characterized Avalanche Voltage and Current l 100% Tested for RG VDSS RDS(on) max ID 30V 10m:@VGS = 10V 13A A A D S 1 8 S 2 7 D S 3 6 D G 4 5 D SO-8 Top View Absolute Maximum Ratings Max. Units VDS Drain-to-Source Voltage Parameter 30 V VGS Gate-to-Source Voltage 20 ID @ TA = 25C Continuous Drain Current, VGS @ 10V 13 ID @ TA = 70C Continuous Drain Current, VGS @ 10V 10 IDM Pulsed Drain Current 100 PD @TA = 25C Power Dissipation PD @TA = 70C Power Dissipation TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range c A 2.5 W 1.6 0.02 -55 to + 150 W/C C Thermal Resistance Parameter RJL RJA Junction-to-Drain Lead Junction-to-Ambient f Typ. Max. Units --- 20 C/W --- 50 Notes through are on page 10 www.irf.com 1 6/30/05 IRF7413Z Static @ TJ = 25C (unless otherwise specified) Parameter Min. Typ. Max. Units BVDSS Drain-to-Source Breakdown Voltage VDSS/TJ RDS(on) Conditions 30 --- --- V VGS = 0V, ID = 250A Breakdown Voltage Temp. Coefficient --- 0.025 --- V/C Reference to 25C, ID = 1mA Static Drain-to-Source On-Resistance --- 8.0 10 m VGS = 10V, ID = 13A --- 10.5 13 VGS(th) Gate Threshold Voltage 1.35 1.80 2.25 V VGS(th)/TJ Gate Threshold Voltage Coefficient --- -5.0 --- mV/C IDSS Drain-to-Source Leakage Current --- --- 1.0 A VDS = 24V, VGS = 0V --- --- 150 IGSS Gate-to-Source Forward Leakage --- --- 100 nA VGS = 20V Gate-to-Source Reverse Leakage --- --- -100 gfs Forward Transconductance 62 --- --- Qg VGS = 4.5V, ID e = 10A e VDS = VGS, ID = 250A VDS = 24V, VGS = 0V, TJ = 125C VGS = -20V S VDS = 15V, ID = 10A Total Gate Charge --- 9.5 14 Qgs1 Pre-Vth Gate-to-Source Charge --- 3.0 --- Qgs2 Post-Vth Gate-to-Source Charge --- 1.0 --- Qgd Gate-to-Drain Charge --- 3.0 --- ID = 10A Qgodr See Fig. 16 VDS = 15V nC VGS = 4.5V Gate Charge Overdrive --- 2.5 --- Qsw Switch Charge (Qgs2 + Qgd) --- 4.0 --- Qoss Output Charge --- 5.6 --- nC RG Gate Resistance --- 2.3 4.5 td(on) Turn-On Delay Time --- 8.7 --- VDD = 16V, VGS = 4.5V tr Rise Time --- 6.3 --- ID = 10A td(off) Turn-Off Delay Time --- 11 --- tf Fall Time --- 3.8 --- Ciss Input Capacitance --- 1210 --- Coss Output Capacitance --- 270 --- Crss Reverse Transfer Capacitance --- 140 --- ns VDS = 15V, VGS = 0V Clamped Inductive Load VGS = 0V pF VDS = 15V = 1.0MHz Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current c d Typ. Max. Units --- 32 mJ --- 10 A Diode Characteristics Parameter IS Continuous Source Current Min. Typ. Max. Units --- --- 3.1 (Body Diode) ISM A Pulsed Source Current (Body Diode) c --- --- 100 Conditions MOSFET symbol showing the integral reverse VSD Diode Forward Voltage --- --- 1.0 V p-n junction diode. TJ = 25C, IS = 10A, VGS = 0V trr Reverse Recovery Time --- 24 36 ns TJ = 25C, IF = 10A, VDD = 15V Qrr Reverse Recovery Charge --- 16 24 nC di/dt = 100A/s ton Forward Turn-On Time 2 e e Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) www.irf.com IRF7413Z 1000 1000 100 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 10V 8.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V 10 2.5V 1 100 BOTTOM VGS 10V 8.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V 10 2.5V 20s PULSE WIDTH Tj = 150C 20s PULSE WIDTH Tj = 25C 1 0.1 0.1 1 0.1 10 10 Fig 2. Typical Output Characteristics Fig 1. Typical Output Characteristics 1000 2.0 100 T J = 150C 10 T J = 25C VDS = 10V 20s PULSE WIDTH 1 ID = 13A VGS = 10V 1.5 (Normalized) RDS(on) , Drain-to-Source On Resistance ID, Drain-to-Source Current () 1 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) 1.0 0.5 2 3 4 5 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 6 -60 -40 -20 0 20 40 60 80 100 120 140 160 T J , Junction Temperature (C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRF7413Z 10000 12.0 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd VGS , Gate-to-Source Voltage (V) ID= 10A C, Capacitance(pF) C oss = C ds + C gd Ciss 1000 Coss Crss VDS= 24V VDS= 15V 10.0 8.0 6.0 4.0 2.0 0.0 100 1 10 100 0 1000.00 12 16 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 8 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 100.00 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 T J = 150C 10.00 T J = 25C 1.00 VGS = 0V 0.10 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 4 Q G Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) 1.4 10 100sec 1msec 1 T A = 25C Tj = 150C Single Pulse 10msec 0.1 0 1 10 100 1000 VDS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF7413Z 14 2.5 VGS(th) Gate threshold Voltage (V) ID, Drain Current (A) 12 10 8 6 4 2 2.0 ID = 250A 1.5 1.0 0.5 0 25 50 75 100 125 -75 150 -50 -25 0 25 50 75 100 125 150 T J , Temperature ( C ) T A , Ambient Temperature (C) Fig 9. Maximum Drain Current vs. Ambient Temperature Fig 10. Threshold Voltage vs. Temperature 100 Thermal Response ( Z thJA ) D = 0.50 10 0.20 0.10 0.05 1 0.02 0.01 J 0.1 R1 R1 J 1 R2 R2 2 1 R3 R3 C 3 2 3 4 4 Ci= i/Ri Ci i/Ri 0.000337 2.4927 0.012752 25.570 0.691000 20.340 21.90000 t1 t2 Notes: 1. Duty factor D = t 1/ t 2 2. Peak T J = P DM x Z thJA 0.001 1E-006 1E-005 0.0001 i (sec) 1.8556 P DM SINGLE PULSE ( THERMAL RESPONSE ) 0.01 Ri (C/W) R4 R4 0.001 0.01 0.1 1 +T A 10 100 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 5 IRF7413Z D.U.T RG VGS 20V DRIVER L VDS + V - DD IAS A 0.01 tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS , Single Pulse Avalanche Energy (mJ) 140 15V ID TOP 120 BOTTOM 3.1A 3.9A 10A 100 80 60 40 20 0 25 50 75 100 125 150 Starting T J , Junction Temperature (C) Fig 12c. Maximum Avalanche Energy vs. Drain Current LD I AS VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1s Duty Factor < 0.1% 50K 12V .2F Fig 14a. Switching Time Test Circuit .3F D.U.T. + V - DS VDS 90% VGS 3mA 10% IG ID VGS Current Sampling Resistors td(on) Fig 13. Gate Charge Test Circuit 6 tr td(off) tf Fig 14b. Switching Time Waveforms www.irf.com IRF7413Z D.U.T Driver Gate Drive + - - D.U.T. ISD Waveform Reverse Recovery Current + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period * * * * * D= VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer RG Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRF7413Z Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms x Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg x Vg x f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput Q + oss x Vin x f + (Qrr x Vin x f ) 2 This can be expanded and approximated by; Ploss = (Irms x Rds(on ) ) 2 Qgs 2 Qgd +I x x Vin x f + I x x Vin x f ig ig + (Qg x Vg x f ) + Qoss x Vin x f 2 This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. 8 *dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic www.irf.com IRF7413Z SO-8 Package Details D DIM B 5 A 8 6 7 6 H E 1 2 3 0.25 [.010] 4 A MIN .0532 .0688 1.35 1.75 A1 .0040 e e1 0.25 .0098 0.10 .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 E .1497 .1574 3.80 4.00 e .050 BAS IC 1.27 BAS IC .025 BAS IC 0.635 BAS IC H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0 8 0 8 K x 45 C A1 8X b 0.25 [.010] A MAX b e1 6X MILLIMETERS MAX A 5 INCHES MIN y 0.10 [.004] 8X L 8X c 7 C A B FOOTPRINT NOT ES : 1. DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994. 8X 0.72 [.028] 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. 4. OUT LINE CONFORMS T O JEDEC OUT LINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS . MOLD PROTRUS IONS NOT T O EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS . MOLD PROTRUS IONS NOT T O EXCEED 0.25 [.010]. 6.46 [.255] 7 DIMENS ION IS THE LENGT H OF LEAD FOR S OLDERING TO A S UBS T RAT E. 3X 1.27 [.050] 8X 1.78 [.070] SO-8 Part Marking EXAMPLE: T HIS IS AN IRF7101 (MOS FET ) INT ERNAT IONAL RECT IFIER LOGO XXXX F7101 DAT E CODE (YWW) P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) Y = LAS T DIGIT OF T HE YEAR WW = WEEK A = ASS EMBLY S IT E CODE LOT CODE PART NUMBER www.irf.com 9 IRF7413Z SO-8 Tape and Reel Dimensions are shown in millimeters (inches) TERMINAL NUMBER 1 12.3 ( .484 ) 11.7 ( .461 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 330.00 (12.992) MAX. 14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 0.62mH, RG = 25, IAS = 10A. Pulse width 400s; duty cycle 2%. When mounted on 1 inch square copper board. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 06/05 10 www.irf.com