PCF2116 family LCD controller / drivers Rev. 05.01 -- 20 July 2007 Product data sheet 1. General description The PCF2116 is a low-power CMOS LCD controller and driver, designed to drive a split screen dot matrix LCD display of 1 or 2 lines by 24 characters or 2 or 4 lines by 12 characters with 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system power consumption. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The PCF2116 interfaces to most microcontrollers using a 4 or 8-bit bus or via the 2-wire I2C-bus. To allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connection to VDD. The `x' in `PCF2116x' represents a specific letter code for a character set in the character generator ROM (CGROM). The different character sets currently available are specified by the letters A, C, and G (see Figure 5, Figure 6 and Figure 7). Other character sets are available on request. Remark: The notation for hexadecimal numbers used in this datasheet is consistent with NXP house style and uses a suffix `h' following the number e.g. 00h. 2. Features Single chip LCD controller/driver 1 or 2-line display of up to 24 characters per line, or 2 or 4 lines of up to 12 characters per line 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese syllabary) and user defined symbols On chip: generation of LCD supply voltage (external supply also possible) generation of intermediate LCD bias voltages oscillator requires no external components (external clock also possible) Display data RAM: 80 characters Character generator ROM: 240 characters Character generator RAM: 16 characters 4 or 8-bit parallel bus or 2-wire I2C-bus interface CMOS/TTL compatible 32 row, 60 column outputs MUX rates 1:32 and 1:16 Uses common 11 code instruction set Logic supply voltage range, VDD - VSS: 2.5 to 6 V Display supply voltage range, VDD - VLCD: 3.5 to 9 V PCF2116 family NXP Semiconductors LCD controller / drivers Low power consumption I2C-bus address: 011101 SA0. 3. Applications Telecom equipment. Portable instruments. Point-of-sale terminals. 4. Ordering information Table 1. Ordering information Type number PCF2116xU Package Name Description Version - chip in tray - PCF2116xU/2 - chip with gold bumps in tray - PCF2116xU/10 - wafer sawn and delivered on film frame carrier (FFC) - PCF2116xU/12 - wafer sawn with gold bumps and delivered on film frame carrier (FFC) - [1] The letter `x' in the type number represents the letter of the required built-in character set: A, C or G. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 2 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 5. Block diagram C1 to C60 R1 to R32 60 BIAS VOLTAGE GENERATOR 32 COLUMN DRIVERS ROW DRIVERS 60 6 32 SHIFT REGISTER 32-BIT DATA LATCHES VLCD 60 V LCD SHIFT REGISTER 5 x 12-BIT GENERATOR 5 PCF2116 CURSOR + DATA CONTROL V0 5 VDD CHARACTER GENERATOR RAM (CGRAM) 16 CHARACTERS VSS CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS OSCILLATOR OSC T1 TIMING GENERATOR 8 DISPLAY DATA RAM (DDRAM) 80 CHARACTERS 7 7 ADDRESS COUNTER (AC) DISPLAY ADDRESS COUNTER 7 POWER-ON RESET INSTRUCTION DECODER 8 8 DATA REGISTER (DR) BUSY FLAG 8 INSTRUCTION REGISTER (IR) 7 8 I/O BUFFER 4 4 coa057 DB0 to DB3 DB4 to DB7 E R/W RS SCL SDA SA0 Fig 1. Block diagram of the pcf2116 family PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 3 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 6. Pinning information C28 C29 C26 C27 C24 C25 C22 C23 C21 C19 C20 C17 C18 C16 y C14 C15 C12 C13 C10 C11 C8 C9 C7 C5 C6 C3 C4 C2 6.1 Pinning C30 C1 C31 R24 R23 C32 C33 R22 R21 C34 C35 R20 R19 C36 C37 R18 R17 C38 C39 R8 R7 C40 C41 R6 R5 C42 C43 R4 C44 R3 R2 C45 R1 6.99 mm 0 x 0 DB7 SCL C46 C47 DB6 C48 C49 SDA C50 C51 DB5 V0 PCF2116 VLCD1 C52 C53 DB4 VLCD2 C54 C55 DB3 C56 C57 VLCD3 C58 C59 DB2 C60 5.64 mm R31 R30 R29 R27 R28 R26 R25 R15 R16 R14 R13 R9 R10 R11 R12 RS T1 VSS2 R/W VSS1 E SA0 DB0 VDD1 VDD2 DB1 OSC R32 coa058 (1) Pad area 0.0121 mm2 (2) Bonding pad dimensions: 110 x 110 A Fig 2. Bonding pad location for PCF2116x PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 4 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers Table 2. Pad allocation table Symbol Pad Symbol Pad OSC 1 C29 to C1 60 to 88 DB1 2 R24 to R17 89 to 96 VDD2 3 R8 to R1 97 to 104 DB0 4 DB7 105 VDD1 5 SCL 106 SA0 6 DB6 107 E 7 SDA 108 VSS1 8 DB5 109 R/W 9 V0 110 T1 10 VLCD1 111 VSS2 11 DB4 112 RS 12 VLCD2 113 R9 to R16 13 to 20 DB3 114 R25 to R32 21 to 28 VLCD3 115 C60 to C30 29 to 59 DB2 116 6.2 Pin description Table 3. Bonding pad description All x/y coordinates represent the position of the centre of each pad with respect to the centre (x/y = 0) of the chip (see Figure 2). Symbol Pad X (m) Y (m) Description OSC 1 -2445 -3300 oscillator/external clock input DB1 2 -2211 -3300 1 bit of 8 bit bi-directional data bus VDD2 3 -2034 -3300 supply voltage 2 DB0 4 -1806 -3300 1 bit of 8 bit bi-directional data bus VDD1 5 -1627 -3300 supply voltage 1 SA0 6 -1437 -3300 I2C-bus address pin E 7 -1245 -3300 data bus clock input (parallel control) VSS1 8 -1056 -3300 logic ground 1 R/W 9 -867 -3300 read/write input (parallel control) T1 10 -672 -3300 test pad (connect to VSS) VSS2 11 -486 -3300 logic ground 2 RS 12 -297 -3300 register select input (parallel control) R9 13 77 -3300 LCD row driver output 9 R10 14 247 -3300 LCD row driver output 10 R11 15 417 -3300 LCD row driver output 11 R12 16 587 -3300 LCD row driver output 12 R13 17 757 -3300 LCD row driver output 13 R14 18 927 -3300 LCD row driver output 14 R15 19 1097 -3300 LCD row driver output 15 R16 20 1267 -3300 LCD row driver output 16 PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 5 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers Table 3. Bonding pad description ...continued All x/y coordinates represent the position of the centre of each pad with respect to the centre (x/y = 0) of the chip (see Figure 2). Symbol Pad X (m) Y (m) Description R25 21 1436 -3300 LCD row driver output 25 R26 22 1606 -3300 LCD row driver output 26 R27 23 1776 -3300 LCD row driver output 27 R28 24 1976 -3300 LCD row driver output 28 R29 25 2116 -3300 LCD row driver output 29 R30 26 2286 -3300 LCD row driver output 30 R31 27 2456 -3300 LCD row driver output 31 R32 28 2626 -3013 LCD row driver output 32 C60 29 2626 -2760 LCD column driver output 60 C59 30 2626 -2590 LCD column driver output 59 C58 31 2626 -2420 LCD column driver output 58 C57 32 2626 -2250 LCD column driver output 57 C56 33 2626 -2080 LCD column driver output 56 C55 34 2626 -1910 LCD column driver output 55 C54 35 2626 -1740 LCD column driver output 54 C53 36 2626 -1570 LCD column driver output 53 C52 37 2626 -1400 LCD column driver output 52 C51 38 2626 -1230 LCD column driver output 51 C50 39 2626 -1060 LCD column driver output 50 C49 40 2626 -890 LCD column driver output 49 C48 41 2626 -720 LCD column driver output 48 C47 42 2626 -550 LCD column driver output 47 C46 43 2626 -380 LCD column driver output 46 C45 44 2626 582 LCD column driver output 45 C44 45 2626 752 LCD column driver output 44 C43 46 2626 922 LCD column driver output 43 C42 47 2626 1092 LCD column driver output 42 C41 48 2626 1262 LCD column driver output 41 C40 49 2626 1432 LCD column driver output 40 C39 50 2626 1602 LCD column driver output 39 C38 51 2626 1772 LCD column driver output 38 C37 52 2626 1942 LCD column driver output 37 C36 53 2626 2112 LCD column driver output 36 C35 54 2626 2282 LCD column driver output 35 C34 55 2626 2452 LCD column driver output 34 C33 56 2626 2622 LCD column driver output 33 C32 57 2626 2792 LCD column driver output 32 C31 58 2626 2962 LCD column driver output 31 C30 59 2626 3132 LCD column driver output 30 PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 6 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers Table 3. Bonding pad description ...continued All x/y coordinates represent the position of the centre of each pad with respect to the centre (x/y = 0) of the chip (see Figure 2). Symbol Pad X (m) Y (m) Description C29 60 2339 3302 LCD column driver output 29 C28 61 2169 3302 LCD column driver output 28 C27 62 1999 3302 LCD column driver output 27 C26 63 1829 3302 LCD column driver output 26 C25 64 1659 3302 LCD column driver output 25 C24 65 1489 3302 LCD column driver output 24 C23 66 1319 3302 LCD column driver output 23 C22 67 1149 3302 LCD column driver output 22 C21 68 979 3302 LCD column driver output 21 C20 69 809 3302 LCD column driver output 20 C19 70 639 3302 LCD column driver output 19 C18 71 469 3302 LCD column driver output 18 C17 72 299 3302 LCD column driver output 17 C16 73 129 3302 LCD column driver output 16 C15 74 -245 3302 LCD column driver output 15 C14 75 -415 3302 LCD column driver output 14 C13 76 -585 3302 LCD column driver output 13 C12 77 -755 3302 LCD column driver output 12 C11 78 -925 3302 LCD column driver output 11 C10 79 -1095 3302 LCD column driver output 10 C9 80 -1265 3302 LCD column driver output 9 C8 81 -1435 3302 LCD column driver output 8 C7 82 -1605 3302 LCD column driver output 7 C6 83 -1775 3302 LCD column driver output 6 C5 84 -1945 3302 LCD column driver output 5 C4 85 -2115 3302 LCD column driver output 4 C3 86 -2285 3302 LCD column driver output 3 C2 87 -2455 3302 LCD column driver output 2 C1 88 -2625 3015 LCD column driver output 1 R24 89 -2625 2846 LCD row driver output 24 R23 90 -2625 2676 LCD row driver output 23 R22 91 -2625 2506 LCD row driver output 22 R21 92 -2625 2336 LCD row driver output 21 R20 93 -2625 2166 LCD row driver output 20 R19 94 -2625 1996 LCD row driver output 19 R18 95 -2625 1826 LCD row driver output 18 R17 96 -2625 1656 LCD row driver output 17 R8 97 -2625 1487 LCD row driver output 8 R7 98 -2625 1317 LCD row driver output 7 PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 7 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers Table 3. Bonding pad description ...continued All x/y coordinates represent the position of the centre of each pad with respect to the centre (x/y = 0) of the chip (see Figure 2). Symbol Pad X (m) Y (m) Description R6 99 -2625 1147 LCD row driver output 6 R5 100 -2625 977 LCD row driver output 5 R4 101 -2625 807 LCD row driver output 4 R3 102 -2625 637 LCD row driver output 3 R2 103 -2625 467 LCD row driver output 2 R1 104 -2625 297 LCD row driver output 1 DB7 105 -2625 -290 1 bit of 8 bit bi-directional data bus SCL 106 -2625 -479 I2C-bus serial clock input DB6 107 -2625 -716 1 bit of 8 bit bi-directional data bus SDA 108 -2625 -976 I2C-bus serial data input/output DB5 109 -2625 -1202 1 bit of 8 bit bi-directional data bus V0 110 -2625 -1388 control input for VLCD VLCD1 111 -2625 -1580 LCD supply voltage input/output 1 DB4 112 -2625 -1808 1 bit of 8 bit bi-directional data bus VLCD2 113 -2625 -1985 LCD supply voltage input/output 2 DB3 114 -2625 -2213 1 bit of 8 bit bi-directional data bus VLCD3 115 -2625 -2390 LCD supply voltage input/output 3 DB2 116 -2625 -2621 1 bit of 8 bit bi-directional data bus 7. Pin functions 7.1 RS: register select (parallel control) RS selects the register to be accessed for read and write when the device is controlled by the parallel interface. RS = logic `0' selects the instruction register for write and the Busy Flag and Address Counter for read. RS = logic `1' selects the data register for both read and write. There is an internal pull-up on pin RS. 7.2 R/W: read/write (parallel control) R/W selects either the read (R/W = logic `1') or write (R/W = logic `0') operation when control is by the parallel interface. There is an internal pull-up on this pin. 7.3 E: data bus clock The E pin is set HIGH to signal the start of a read or write operation when the device is controlled by the parallel interface. Data is clocked in or out of the chip on the negative edge of the clock. Note that this pin must be connected to logic `0' (VSS) when the I2C-bus control is used. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 8 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 7.4 DB0 to DB7: data bus The bidirectional, 3-state data bus transfers data between the system controller and the PCF2116. DB7 may be used as the Busy Flag signalling that internal operations are not yet complet. In 4-bit operations the 4 higher order lines DB4 to DB7 are used; DB0 to DB3 must be left open circuit. There is an internal pull-up on each of the data lines. Note that these pins must be left open circuit when the I2C-bus control is used. 7.5 C1 to C60: column driver outputs These pins output the data for pairs of columns.This arrangement permits an optimized chip-on-glass (COG) design for 4-line, 12 character layouts. 7.6 R1 to R32: row driver outputs These pins output the row select waveforms to the left and right halves of the display. 7.7 VLCD: LCD power supply Negative power supply for the liquid crystal display. This may be generated on-chip or supplied externally. 7.8 V0: VLCD control input The input level at this pin determines the generated VLCD output voltage. 7.9 OSC: oscillator When the on-chip oscillator is used this pin must be connected to VDD. This pin is the input for an external clock signal, if used. 7.10 SCL: serial clock line Input for the I2C-bus clock signal. 7.11 SDA: serial data line Input/output for the I2C-bus data line. 7.12 SA0: address pin The hardware sub-address line is used to program the device sub-address for 2 different PCF2116s on the same I2C-bus. 7.13 T1: test pad Must be connected to VSS. Not user accessible. 8. Functional description 8.1 LCD supply voltage generator for PCF2116x The on-chip voltage generator is controlled by bit G of the `Function set' instruction and V0. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 9 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers V0 is a high-impedance input and draws no current from the system power supply. Its range is between VSS and VDD - 1 V. When V0 is connected to VDD the generator is switched off and an external voltage must be supplied to pin VLCD. This can be more negative than VSS. When G = logic `1' the generator produces a negative voltage at pin VLCD, controlled by the input voltage at pin V0. The LCD operating voltage is given by the relationship: V OP = ( 1.8V DD - V 0 ) Where: V OP = ( V DD - V LCD ) and V LCD = ( V 0 - 0.8V DD ) When G = logic `0', the generated output voltage VLCD is equal to V0 (between VSS and VDD). In this instance: V OP = V DD - V 0 When VLCD is generated on-chip the VLCD pin must be de-coupled to VDD with a suitable capacitor. VDD and V0 must be selected to limit the maximum value of VOP to 9 V. Figure 3 and Figure 4 show the two generator control characteristics. 9 9V VOP VOP(max) = 1.8 x VDD 8 6 = VDD 7 G=1 5 6 4 5 3 3.5 VOP(min) = 0.8 x VDD +1 2.5 4 0 1 2 3 4 5 V0 6 mga798 (1) High voltage mode: VOP = 1.8VDD - V0 Fig 3. VOP as a function of V0 control characteristics (1) PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 10 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 9 VOP 8 7 G=0 6 5 6 = VDD 5 4 3.5 4 0 1 2 3 4 5 V0 6 mga799 (1) Buffer mode: VOP = VDD - V0 Fig 4. VOP as a function of V0 control characteristics (2) 8.2 Character generator ROM (CGROM) The character generator ROM generates 240 character patterns in 5 x 8 dot format from 8-bit character codes. Figure 5, Figure 6 and Figure 7 show the character sets currently available. The standard character sets A, C and G are available for the PCF2116x. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 11 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers lower 6 bits upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 mlb245 Fig 5. Character set `A' in CGROM: PCF2116A PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 12 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers lower 4 bits upper 4 bits 0000 xxxx 0000 CG RAM 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 mlb895 Fig 6. Character set `C' in CGROM: PCF2116C PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 13 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers lower 6 bits upper 4 bits 0000 xxxx 0000 CG RAM 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 mlb896 Fig 7. Character set `G' in CGROM: PCF2116G PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 14 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 8.3 LCD bias voltage generator The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for external bias chain resistors and significantly reduces the system power consumption. The optimum levels depend on the multiplex rate and are selected automatically when the number of lines in the display is defined. The optimum value of VOP depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships in Table 4. Using a 5-level bias scheme for 1:16 MUX rate allows VOP < 5 V for most LCD liquids. The effect on the display contrast is negligible. Table 4. Optimum values for VOP MUX rate Number of bias levels VOP/Vth Discrimination Von/Voff 1:16 5 3.67 1.277 1:32 6 5.19 1.196 8.4 Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required. Pin OSC must be connected to VDD. 8.5 External clock If an external clock is to be used, it must be input at pin OSC. The resulting display frame frequency is given by fframe = 12304 fosc . A clock signal must always be present, otherwise the LCD is frozen in a DC state. 8.6 Power-on reset The power-on reset block initializes the chip after power-on or power failure. 8.7 Registers The PCF2116 has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as `Display clear' and `Cursor shift', and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written to, but not read, by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the Address Counter is written to the data register prior to being read by the `Read data' instruction. 8.8 Busy flag The Busy Flag indicates the free/busy status of the PCF2116. Logic `1' indicates that the chip is busy and further instructions will not be accepted. The Busy Flag is output to pin DB7 when RS = logic `0' and R/W = logic `1'. Instructions must only be written after checking that the Busy Flag is logic `0' or waiting for the required number of clock cycles. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 15 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 8.9 Address counter (AC) The Address Counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions `Set CGRAM address' and `Set DDRAM address'. After a read/write operation the Address Counter is automatically incremented or decremented by 1.The Address Counter contents are output to the bus (DB0 to DB6) when RS = logic `0' and R/W = logic `1'. 8.10 Display data RAM (DDRAM) The display data RAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping scheme is shown in Figure 8 and Figure 9. With no display shift the characters represented by the codes in the first 12 or 24 RAM locations starting at address 00 in line 1 are displayed. Subsequent lines display data starting at addresses 20h, 40h, or 60h. Figure 10, Figure 11, Figure 12 and Figure 13 show the DDRAM-to-display mapping principle when the display is shifted. Display Position (decimal) DDRAM Address (hex) 1 3 2 4 5 non-displayed DDRAM addresses 22 23 24 00 01 02 03 04 15 16 17 18 19 4C 4D 4E 4F 1-line display non-displayed DDRAM address DDRAM Address (hex) 00 01 02 03 04 15 16 17 18 19 24 25 26 27 line 1 40 41 42 43 44 55 56 57 58 59 64 65 66 67 line 2 mla792 2-line display Fig 8. DDRAM-to display mapping (1); no shift. non-displayed DDRAM addresses 1 2 3 4 5 6 7 8 9 10 11 12 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 line 1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 line 2 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 line 3 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 line 4 DDRAM Address (hex) 4 line display mla793 Fig 9. DDRAM-to display mapping (2); no shift. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 16 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 1 Display Position (decimal) DDRAM Address (hex) DDRAM Address (hex) 1 2 3 4 5 22 23 24 4F 00 01 02 03 27 00 01 02 03 14 15 16 line 1 67 40 41 42 43 54 55 56 line 2 DDRAM Address (hex) 3 4 5 6 7 8 9 10 11 12 13 00 01 02 03 04 05 06 07 08 09 0A line 1 33 20 21 22 23 24 25 26 27 28 29 2A line 2 53 40 41 42 43 44 45 46 47 48 49 4A line 3 73 60 61 62 63 64 65 66 67 68 69 6A line 4 mla802 5 22 23 24 01 02 03 04 05 16 17 18 Fig 11. DDRAM-to display mapping (2); right shift. 1 2 3 4 5 6 7 8 9 01 02 03 04 05 06 07 08 09 0A 0B 0C 10 11 12 line 1 21 22 23 24 25 26 27 28 29 2A 2B 2C line 2 41 42 43 44 45 46 47 48 49 4A 4B 4C line 3 61 62 63 64 65 66 67 68 69 6A 6B 6C line 4 DDRAM Address (hex) 1-line display 01 02 03 04 05 16 17 18 line 1 41 42 43 44 45 56 57 58 line 2 mla815 2-line display mla803 4-line display Fig 10. DDRAM-to display mapping (1); right shift. 2 4 Address (hex) 1-line display 1 3 DDRAM 14 15 16 2-line display Display Position (decimal) DDRAM Address (hex) 2 4-line display Fig 12. DDRAM-to display mapping (1); left shift. mla816 Fig 13. DDRAM-to display mapping (2); left shift. The display address ranges are shown in Table 5. Table 5. Display address ranges 1-line display 2-line display 4-line display 00 to 4F line 1: 00 to 27 line 1: 00 to 13 - line 2: 40 to 67 line 2: 20 to 33 - - line 3: 40 to 53 - - line 4: 60 to 73 For 2 and 4-line displays the end address of one line and the start address of the next line are not consecutive. When the display is shifted each line wraps around independently of the others (Figure 10, Figure 11, Figure 12 and Figure 13). When data is written into the DDRAM wrap-around occurs from 4F to 00 in 1-line mode and from 27 to 40 and 67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60 and 73 to 00 in 4-line mode. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 17 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 8.11 Character generator RAM (CGRAM) Up to 16 user-defined characters may be stored in the character generator RAM. The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Figure 5). Figure 14 shows the addressing principle for the CGRAM. character codes (DDRAM data) 7 6 5 4 3 2 higher order bits 0 0 0 0 0 0 CGRAM address 1 0 6 lower order bits 0 0 0 0 0 0 0 0 5 4 3 2 higher order bits 0 1 0 0 0 0 0 0 character patterns (CGRAM data) 1 0 lower order bits 0 1 4 3 higher order bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 2 1 0 lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 1 cursor position character pattern example 2 mga800 Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th line will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Figure 14 (bit 4 being at the left end). As shown in Figure 5 and Figure 14, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `Set CGRAM address' instruction. Bit 6 can be set using the `Set DDRAM address' instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `Read busy flag and address' instruction. Fig 14. Relationship between CGRAM addresses and data / display patterns 8.12 Cursor control circuit The cursor control circuit generates the cursor (underline and/or character blink as shown in Figure 15) at the DDRAM address contained in the Address Counter. When the Address Counter contains the CGRAM address the cursor will be inhibited. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 18 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers cursor mga801 5 x 7 dot character font alternating display cursor display example blink display example Fig 15. Cursor and blink display examples 8.13 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.14 LCD row and column drivers The PCF2116 contains 32 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display, in accordance with the data to be displayed. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figure 16 and Figure 17 show typical waveforms. In 1-line mode (1:16) the row outputs are driven in pairs: R1/R17, R2/R18 for example. This allows the output pairs to be connected in parallel, providing greater drive capability. Unused outputs should be left unconnected. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 19 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers frame n frame n 1 state 1 (ON) state 2 (ON) VDD V2 ROW 1 V3/V4 V5 VLCD VDD V2 ROW 9 V3/V4 V5 VLCD ROW 2 VDD V2 V3/V4 V5 VLCD COL 1 VDD V2 V3/V4 V5 VLCD COL 2 VDD V2 V3/V4 V5 VLCD 1-line display (1:16) VOP 0.25 VOP state 1 0 V -0.25 VOP -VOP VOP 0.25 VOP state 2 0 V -0.25 VOP -VOP 1 2 3 16 1 2 3 16 mga802 Fig 16. Typical LCD waveforms; 1-line mode PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 20 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers frame n ROW 1 VDD V2 V3 V4 V5 VLCD ROW 9 VDD V2 V3 V4 V5 VLCD ROW 2 VDD V2 V3 V4 V5 VLCD COL 1 VDD V2 V3 V4 V5 VLCD COL 2 VDD V2 V3 V4 V5 VLCD frame n + 1 state 1 (ON) state 2 (ON) 2-line display (1:32) VOP 0.15 VOP state 1 0 V -0.15 VOP -VOP VOP 0.15 VOP state 2 0 V -0.15 VOP -VOP 123 32123 32 mga803 Fig 17. Typical LCD waveforms; 2-line mode PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 21 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 8.15 Reset function The PCF2116 automatically initializes (resets) when power is turned on. After reset the chip has the following state (see Table 6): Table 6. State after reset Step Description 1 display clear 2 function set 3 display on/off control 4 entry mode set DL = 1 8-bit interface M, N = 0 1-line display G=0 voltage generator; VLCD = V0 D=0 display off C=0 cursor off B=0 blink off I/D = 1 +1 increment S=0 no shift 5 Default address pointer to DDRAM. The Busy Flag (BF) indicates the busy state (BF = logic `1') until initialization ends. The busy state lasts for 2 ms. The chip can also be initialized by software. (see Figure 18 and Figure 29). 6 I2C-bus interface reset 9. Instructions Only two PCF2116 registers, the Instruction Register (IR) and the Data Register (DR) are directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers to allow an interface to various types of microcontrollers which operate at different speeds or to allow an interface to peripheral control ICs. PCF2116 operation is controlled by the instructions shown in Table 8 together with their execution time. There are 4 categories of instructions, those that: * * * * designate PCF2116 functions such as display format, data length, etc. set internal RAM addresses perform data transfer with internal RAM others. In normal use, the data transfer instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation no instruction other than `Read busy flag and address' is executed. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 22 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers Because the Busy Flag is set to logic `1' while an instruction is being executed, check to make sure it is on logic `0' before sending the next instruction or wait for the maximum instruction execution time, as given in Table 8. An instruction sent while the Busy Flag is HIGH will not be executed. Table 7. Command bit identities Bit 0 1 I/D decrement increment S display freeze display shift D display off display on C cursor off cursor on B character at cursor position does not blink character at cursor position blinks S/C cursor move display shift R/L left shift right shift DL 4 bits 8 bits G voltage generator: VLCD = V0 voltage generator; VLCD = V0 - 0.8VDD PCF2116x 1 line x 24 characters; MUX 1:16 2 lines x 24 characters; MUX 1:32 N, (M = 1) reserved 4 lines x 12 characters; MUX 1:32 N, (M = 0) BF end of internal operation internal operation in progress Co last control byte, only data bytes to follow next two bytes are a data byte and another control byte PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 23 of 56 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCF2116_family_05 Product data sheet Table 8. Instructions Rev. 05.01 -- 20 July 2007 Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Required clock cycles NOP 0 0 0 0 0 0 0 0 0 0 No operation. 0 Clear display 0 0 0 0 0 0 0 0 0 1 Clears entire display and sets DDRAM address 0 in Address Counter. 165 Return Home 0 0 0 0 0 0 0 0 1 0 Sets DDRAM address 0 in Address 3 Counter. Also returns shifted display to original position. DDRAM contents remain unchanged. Entry mode set 0 0 0 0 0 0 0 1 I/D S Sets cursor move direction and specifies shift of display. These operations are performed during data write and read. Display control 0 0 0 0 0 0 1 D C B Sets entire display on/off (D), 3 cursor on/off (C) and blink of cursor position character (B). Cursor/display shift 0 0 0 0 0 1 S/C R/L 0 0 Moves cursor and shifts display 3 without changing DDRAM contents. Function set 0 0 0 0 1 DL N M G 0 Sets interface data length (DL), number of display lines (N, M) and voltage generator control (G). 3 Set CGRAM address 0 0 0 1 ACG Sets CGRAM address. 3 Set DDRAM address 0 0 1 ADD Sets DDRAM address. 3 Read busy flag and address 0 1 BF AC Reads Busy Flag (BF) indicating internal operation is being performed and reads Address Counter contents. 0 Read data 1 1 read data Reads data from CGRAM or DDRAM. 3 Write data 1 0 write data Writes data to CGRAM or DDRAM. 3 [2] In the I2C-bus mode a control byte is required when RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0. [3] Example: fosc = 150 kHz, T CY = ------------ = 6.67s ; 3 cycles = 20 s, 165 cycles = 1.1 ms. fOSC 1 PCF2116 family In the I2C-bus mode the DL bit is don't care. 8-bit mode is assumed. LCD controller / drivers 24 of 56 (c) NXP B.V. 2007. All rights reserved. [1] 3 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx START CONDITION (S) BIT 7 MSB (A7) BIT 6 (A6) BIT 0 LSB R/W ACKNOWLEDGE (A) NXP Semiconductors PCF2116_family_05 Product data sheet PROTOCOL STOP CONDITION (P) SDA tBUF tLOW tr SCL tHD;STA Rev. 05.01 -- 20 July 2007 tf tHIGH tSU;STO t/fSCL mga811 Fig 18. I2C-bus timing diagram; rise and fall times refer to VIL and VIH PCF2116 family LCD controller / drivers 25 of 56 (c) NXP B.V. 2007. All rights reserved. PCF2116 family NXP Semiconductors LCD controller / drivers RS R/W E DB7 IR7 IR3 BF AC3 DR7 DR3 DB6 IR6 IR2 AC6 AC2 DR6 DR2 DB5 IR5 IR1 AC5 AC1 DR5 DR1 DB4 IR4 IR0 AC4 AC0 DR4 DR0 busy flag and address counter read instruction write data register read mga804 Fig 19. 4-bit transfer example RS R/W E internal DB7 internal operation IR7 IR3 busy instruction write AC3 busy flag check not busy AC3 busy flag check D7 D3 instruction write mga805 (1) IR7, IR3: instruction 7th bit, 3rd bit. (2) AC3: Address counter 3rd bit. Fig 20. 4-bit transfer timing sequence PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 26 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers RS R/W E internal internal operation data DB7 instruction write busy busy busy flag check busy flag check not busy busy flag check data instruction write mga806 Fig 21. Busy flag check timing sequence 9.1 Clear display `Clear display' writes space code 20h into all DDRAM addresses (The character pattern for character code 20 must be a blank pattern). Sets the DDRAM Address Counter to logic `0'. Returns the display to its original position if it was shifted. So, the display disappears and the cursor or blink position goes to the left edge of the display (the first line if 2 or 4 lines are displayed). Sets entry mode I/D = logic `1' (increment mode). S of entry mode does not change. The instruction `Clear display' requires extra execution time. This is accommodated by checking the busy-flag (BF) or waiting for 2 ms. The latter must be applied where no read-back options are foreseen, as in some chip-on-glass (COG) applications. 9.2 Return home `Return home' sets the DDRAM Address Counter to logic `0' and returns the display to its original position if it was shifted. The DDRAM contents do not change. The cursor or blink position goes to the left of the display (the first line if 2 or 4 lines are displayed). I/D and S of entry mode do not change. 9.3 Entry mode set 9.3.1 I/D When I/D = logic `1' (or `0') the DDRAM or CGRAM address increments (or decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor and blink are inhibited when the CGRAM is accessed. 9.3.2 S When S = logic `1', the entire display shifts either to the right (I/D = logic `0') or to the left (I/D = logic `1') during a DDRAM write. So, it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing into or reading from the CGRAM. When S = logic `0' the display does not shift. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 27 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 9.4 Display on/off control 9.4.1 D The display is on when D = logic `1' and off when D = logic `0'. Display data in the DDRAM is not affected and can be displayed immediately by setting D to logic `1'. 9.4.2 C The cursor is displayed when C = logic `1' and inhibited when C = logic `0'. Even if the cursor disappears, the display functions e.g. I/D, remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Figure 15). 9.4.3 B The character indicated by the cursor blinks when B = logic `1'. The blink is displayed by switching between display characters and all dots on with a period of 1 second when fosc = 150 kHz (see Figure 15). At other clock frequencies the blink period is equal to 150 kHz/fosc. The cursor and the blink can be set to display simultaneously. 9.5 Cursor display shift `Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2 or 4-line displays, the cursor moves to the next line when it passes the last position (40 or 20 decimal) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the cursor shift. 9.6 Function set 9.6.1 DL (parallel mode only) Defines interface data width when the parallel data interface is used. Data is sent or received in bytes (bits DB7 to DB0) when DL = logic `1', or in two 4-bit nibbles (DB7 to DB4) when DL = logic `0'. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 are left open (internal pull-ups). Hence in the first `Function set' instruction after power-on, G and H are set to 1. A second `Function set' must then be sent (2 nibbles) to set G and H to their required values. When using the I2C-bus interface the DL should not previously have been set to 0 using the parallel interface. 9.6.2 N, M Sets the number of display lines. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 28 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 9.6.3 G Controls the VLCD voltage generator characteristic. 9.7 Set CGRAM address `Set CGRAM address' sets bit 0 to 5 of the CGRAM address (ACG in Table 8 ) into the Address Counter (binary A[5] to A[0]). Data can then be written to or read from the CGRAM. Only bits 0 to 5 of the CGRAM address are set by the `Set CGRAM address' instruction. Bit 6 can be set using the `Set DDRAM address' instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `Read busy flag and address' instruction. 9.8 Set DDRAM address `Set DDRAM address' sets the DDRAM address (ADD in Table 8) into the Address Counter (binary A[6] to A[0]). Data can then be written to or read from the DDRAM. Table 9. Hexadecimal address ranges (pcf2116) Address (h) Function 00 to 4F 1-line by 24 00 to 27 and 40 to 67 2-lines by 24 00 to 13, 20 to 33, 40 to 53 and 60 to 73 4-lines by 12 9.9 Read busy flag and address `Read busy flag and address' reads the Busy Flag (BF). BF = logic 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = logic 0, so BF should be checked before sending another instruction. At the same time, the value of the Address Counter (AC in Table 8) expressed in binary A[6] to A[0] is read out. The Address Counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction. 9.10 Write data to CGRAM or DDRAM Writes binary 8-bit data D[7] to D[0] to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written into is determined by the previous specification of the CGRAM or DDRAM address setting. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits D[4] to D[0] of CGRAM data are valid, bits D[7] to D[5] are `don't care' CGRAM addresses. 9.11 Read data from CGRAM or DDRAM Reads binary 8-bit data D[7] to D[0] from the CGRAM or DDRAM. The most recent `Set address' instruction determines whether the CGRAM or DDRAM is to be read. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 29 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers The `Read data' instruction gates the content of the data register (DR) to the bus while E = HIGH. After E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. Remark: the only three instructions which update the data register (DR) are: * `Set CGRAM address' * `Set DDRAM address' * `Read data' from CGRAM or DDRAM. Other instructions (e.g. `Write data', `Cursor/Display shift', `Clear display', `Return home') do not modify the data register content. 10. Interface to microcontroller (parallel interface) The PCF2116 can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB0 to DB7. Three further control lines E, RS, and R/W are required. In 4-bit mode data is transferred in two cycles of 4-bits each. The higher order bits (corresponding to DB4 to DB7 in 8-bit mode) are sent in the first cycle and the lower order bits (DB0 to DB3 in 8-bit mode) in the second. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the Busy Flag check. 4-bit operation is selected by instruction. See Figure 19, Figure 20 and Figure 21 for examples of bus protocol. In 4-bit mode pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally. 11. Interface to microcontroller (I2C-bus interface) 11.1 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 11.2 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 30 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 11.3 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). 11.4 System configuration A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. 11.5 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 11.6 I2C-bus protocol Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different PCF2116 READ and WRITE cycles is shown in Figure 22, Figure 23 and Figure 24. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 31 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers acknowledgement from PCF2116 S S 0 1 1 1 0 1 A 0 A 1 0 CONTROL BYTE A 0 DATA 2n 0 bytes slave address R/W A Co CONTROL BYTE DATA A A P n 0 bytes 1 byte Co update data pointer S 0 1 1 1 0 1 A 0 0 PCF2116 slave address mbh668 R/W Fig 22. Master transmits to slave receiver; WRITE mode acknowledgement from PCF2116 S SLAVE ADDRESS S A 1 A 0 acknowledgement from master DATA n bytes A no acknowledgement from master DATA 1 P last byte R/W update data pointer mga810 Fig 23. Master reads slave immediately after first byte; READ mode (RS previously defined) PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 32 of 56 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCF2116_family_05 Product data sheet acknowledgement from PCF2116 S S 0 1 1 1 0 1 A 0 A 1 0 CONTROL BYTE DATA 2n 0 bytes slave address R/W A Co A 0 1 1 CONTROL SLAVE ADDRESS Rev. 05.01 -- 20 July 2007 S A 1 A 0 A 2 bytes Co acknowledgement from PCF2116 S DATA(1) A no acknowledgement from master DATA A DATA n bytes 1 P last byte R/W update data pointer mga809 (1) Last data byte is a dummy byte (may be omitted). Fig 24. Master reads after setting word address; write word address, set RS/RW; READ data SDA 33 of 56 (c) NXP B.V. 2007. All rights reserved. Fig 25. Bit transfer change of data allowed mbc621 LCD controller / drivers data line stable; data valid PCF2116 family SCL PCF2116 family NXP Semiconductors LCD controller / drivers SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 26. Definition of START and STOP conditions MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL mga807 Fig 27. System configuration data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 28. Acknowledgement on the I2C-bus PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 34 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 12. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage Min Max Unit -0.5 8.0 V VDD - 11 VDD V VDD + 0.5 V VLCD - 0.5 VDD + 0.5 V VLCD LCD supply voltage VI input voltage on each of the pins OSC, V0, RS, R/W, VSS - 0.5 E, and DB0 to DB7 VO output voltage on each of the pins R1 to R32, C1 to C60 and VLCD II input current -10 +10 mA IO output current -10 +10 mA IDD supply current -50 +50 mA ISS ground supply current -50 +50 mA ILCD LCD supply current -50 +50 mA Ptot total power dissipation - 400 mW PO output power - 100 mW Tstg storage temperature -65 +150 C CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. 12.1 ESD values * ESD protection exceeds 5000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101. * Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA. 13. Static characteristics Table 11. Static characteristics VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9.0 V; TAMB = -40 to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - 6.0 V Supplies VDD supply voltage 2.5 VLCD LCD supply voltage VDD - 9 - VDD - 3.5 V IDD supply current external VLCD IDD1 supply current 1 external VLCD [1] - 200 500 A IDD2 supply current 2 VDD = 5 V; VOP = 9 V; fOSC = 150 kHz; Tamb = 25 C [1] - 200 300 A [1] PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 35 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers Table 11. Static characteristics ...continued VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9.0 V; TAMB = -40 to +85 C; unless otherwise specified. Symbol Parameter Conditions IDD3 supply current 3 VDD = 3 V; VOP = 5 V; fOSC = 150 kHz; Tamb = 25 C [1] IDD4 supply current 4 internal VLCD [1] [2] Min Typ Max Unit - 150 200 A - 700 1100 A - 600 900 A - 500 800 A [8] IDD5 IDD6 ILCD VPOR supply current 5 supply current 6 VDD = 5 V; VOP = 9 V; fOSC = 150 kHz; Tamb = 25 C [1] [2] VDD = 3 V; VOP = 5 V; fOSC = 150 kHz; Tamb = 25 C [1] [2] [8] [8] LCD supply current [1] [7] - 50 100 A power on reset supply voltage [3] - 1.3 1.8 V - 0.3 VDD V V Logic VIL1 LOW-level input voltage input voltage on pins E, RS, R/W, DB0 to DB7 and SA0 VSS VIH1 HIGH-level input voltage input voltage on pins E, RS, R/W, DB0 to DB7 and SA0 0.7 VDD - VDD VIL(OSC) LOW-level input voltage on pin OSC VSS - VDD - 1.5 V VIL(V0) LOW-level input voltage on pin V0 VSS - VDD - 1.5 V VIH(OSC) HIGH-level input voltage on pin OSC VDD - 0.1 - VDD V VIH(V0) HIGH-level input voltage on pin V0 VDD - 0.05 - VDD V IPU pull-up current pull-up current on pins DB0 to DB7; VI = VSS 0.04 0.15 1.0 A IOL(DB) LOW-level output current low level output current on pins DB0 to DB7; VOL = 0.4 V; VDD = 5 V 1.6 - - mA IOH(DB) HIGH-level output current high level output current on pins -1.0 DB0 to DB7; VOL = 0.4 V; VDD = 5 V - - mA IL1 leakage current VI = VDD or VSS; leakage current on pins OSC, V0, E, RS, R/W, DB0 to DB7 and SA0 -1.0 - +1.0 A Vtol2 output voltage variation LCD supply voltage (VLCD) tolerance [2] -300 40 +300 mV Vtol1 output voltage variation bias voltage tolerance on each pin: R1 - R32 and C1 to C60 [7] -300 40 +300 mV RROW output resistance output resistance on [6] - 1.5 3.0 k LCD outputs each pin: R1 - R32 PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 36 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers Table 11. Static characteristics ...continued VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9.0 V; TAMB = -40 to +85 C; unless otherwise specified. Symbol RCOL Parameter output resistance Conditions output resistance on Min Typ Max Unit [6] - 3.0 6.0 k - each pin: C1 - C60 I2C-bus SDA, SCL VIL2 LOW-level input voltage [4] VSS 0.3 VDD V VIH2 HIGH-level input voltage [4] 0.7 VDD - VDD V IL2 leakage current -1.0 - +1.0 A Ci input capacitance - - 7 pF IOL(SDA) LOW level output current on pin SDA 3 - - mA VI = VDD or VSS; leakage current on pins SDA and SCL [5] VOL = 0.4 V; VDD = 5 V [1] LCD outputs are open-circuit; inputs at VDD or VSS; V0 = VDD; bus inactive; internal or external clock with duty cycle 50% (IDD1 only). [2] LCD outputs are open-circuit; LCD supply voltage generator is on; load current at VLCD = 20 A. [3] Resets all logic when VDD < VPOR. [4] When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current must not exceed 0.5 mA. [5] Tested on sample basis. [6] Resistance of output terminals (R1 to R32 and C1 to C60) with load current = 150 A; VOP = VDD - VLCD = 9 V; outputs measured one at a time; (external VLCD). [7] LCD outputs open-circuit; external VLCD. [8] Maximum value occurs at 85 C. 14. Dynamic characteristics Table 12. Dynamic characteristics VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9.0 V; TAMB = -40 to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit fosc clock frequency external clock frequency 90 150 225 kHz fFR LCD frame frequency internal clock 40 65 100 Hz [1] [1] [2] Timing characteristics: Parallel interface Write operation (writing data from microcontroller to PCF2116) TCY enable cycle time 500 - - ns PWEH enable pulse width 220 - - ns tASU address set-up time 50 - - ns tAH address hold time 25 - - ns tDSW data set-up time 60 - - ns tHD data hold time 25 - - ns Read operation (reading data from PCF2116 to microcontroller) TCY enable cycle time 500 - - ns PWEH enable pulse width 220 - - ns PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 37 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers Table 12. Dynamic characteristics ...continued VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9.0 V; TAMB = -40 to +85 C; unless otherwise specified. Symbol Parameter tASU Min Typ Max Unit address set-up time 50 - - ns tAH address hold time 25 - - ns tDHD data delay time - - 150 ns tHD data hold time 20 - 100 ns - - 100 kHz Timing characteristics: fSCL Conditions I2C-bus [2] SCL clock frequency on the I2C-bus tSW tolerable spike pulse width - - 100 ns tBUF bus free time between a STOP and START 4.7 - - s tSU;STA set-up time for a repeated START condition 4.7 - - s tHD;STA START condition hold time 4.0 - - s tLOW SCL LOW time 4.7 - - s tHIGH SCL HIGH time 4.0 - - s tr rise time of both SDA and SCL signals - - 1.0 s tf fall time of both SDA and SCL signals - - 0.3 s tSU;DAT data set-up time 250 - - ns tHD;DAT data hold time 0.0 - - ns tSU;STO set-up time for STOP condition 4.0 - - s [1] VDD = 5 V. [2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. RS VIH1 VIH1 VIL1 VIL1 tAS R/W tAH VIL1 VIL1 tAH PWEH VIH1 E VIL1 VIH1 VIL1 VIL1 tH tDSW VIH1 DB0 to DB7 VIL1 Valid Data Tcy VIH1 VIL1 mla798 Fig 29. Parallel bus write operation sequence; writing data from microcontroller to PCF2116 PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 38 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers VIH1 RS VIH1 VIL1 VIL1 tAS tAH VIH1 VIH1 R/W tAH PWEH VIH1 VIH1 VIL1 E VIL1 VIL1 tDHR t DDR VOH1 VOL1 DB0 to DB7 VOH1 VOL1 mla799 Tcy Fig 30. Parallel bus read operation sequence; reading data from PCF2116 to microcontroller 15. Application information P20 RS P21 R/W P22 E 32 P80CL51 R1 to R32 to LCD PCF2116 60 P10 to P17 8 C1 to C60 DB0 to DB7 mga812 Fig 31. Direct connection to 8-bit microcontroller, 8-bit bus P10 RS P11 R/W P12 E 32 P80CL51 R1 to R32 to LCD PCF2116 60 P14 to P17 4 C1 to C60 DB4 to DB7 mga813 Fig 32. Direct connection to 8-bit microcontroller, 4-bit bus PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 39 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers R7 to R16 R25 to R32 VLCD 16 100 nF VDD VDD R1 to R8 R17 to R24 OSC PCF2116 100 nF 16 100 k 2 x 24 CHARACTER LCD DISPLAY (SPLIT SCREEN) VO VSS DB0 to DB7 E 60 60 C1 to C60 VSS RS R/W mga816 Fig 33. Typical application using parallel interface VLCD R1 to R16 16 R17 to R24 2 x 24 CHARACTER LCD DISPLAY (SPLIT SCREEN) 100 nF VDD VDD OSC 100 nF PCF2116 100 k 16 VO VDD VDD VSS C1 to C60 VSS 60 60 SA0 VDD VLCD 100 nF VDD VDD R1 to R16 OSC 100 nF 100 k VSS PCF2116 16 4 x 12 CHARACTER LCD DISPLAY VO VSS C1 to C60 60 SA0 VSS SCL SDA MICRO CONTROLLER mga817_02 Fig 34. Application using I2C-bus interface PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 40 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers DISPLAY LAYOUT: COLUMNS C1 1 C16 15 31 45 45 31 15 31 61 91 30 46 60 60 46 30 PCF2116 column output numbers 1 LCD column numbers 120 PCF2116 column output numbers 16 DISPLAY LAYOUT: ROWS R8 to R1 R9 to R16 R17 to R24 R32 to R25 2 x 24 character display mga814 Fig 35. 2 x 24 display layout example (PCF2116x) R1 R8 PCF2116 CHIP-ON-GLASS R17 R24 R9 R16 4 LINE BY 12 CHARACTER R25 R32 C1 2116 R9 C60 SCL VSS VDD SDA V0 VLCD mga818 Fig 36. Chip-on-glass application PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 41 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers DISPLAY LAYOUT: COLUMNS C1 15 46 1 31 60 60 PCF2116 column output numbers LCD column numbers DOT MATRIX LCD C16 45 PCF2116 column output numbers DISPLAY LAYOUT: ROWS R8 to R1 R9 to R16 R17 to R24 R32 to R25 mga815 Fig 37. 4 x 12 display layout example (PCF2116) 15.1 4-bit operation, 1-line display using internal reset The program must set functions prior to 4-bit operation. Table 13 shows an example. When power is turned on, 8-bit operation is automatically selected and the PCF2116 attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 13 step 3). So, DB4 to DB7 of the function set are written twice. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 42 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers Table 13. 4-bit operation, 1-line display example; using internal reset Step Instruction 1 power supply on (PCF2116 is initialized by the internal reset circuit) 2 function set 3 Display RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 Operation Initialized. No display appears. Sets to 4-bit operation. In this instance operation is handled as 8-bits by initialization and only this instruction completes with one write. function set 4 0 0 0 0 1 0 0 0 0 0 0 0 Sets to 4-bit operation, selects 1-line display and VLCD = V0. 4-bit operation starts from this point and resetting is needed. display on/off control 5 0 0 0 0 0 0 0 0 1 1 1 0 _ Turns on display and cursor. Entire display is blank after initialization. _ Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted. P_ Writes `P'. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. entry mode set 6 0 0 0 0 0 0 0 0 0 1 1 0 write data to CGRAM/DDRAM 1 0 0 1 0 1 1 0 0 0 0 0 15.2 8-bit operation, 1-line display using internal reset Table 14 shows an example of a 1-line display in 8-bit operation. The PCF2116 functions must be set by the `Function set' instruction prior to display. Since the display data RAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes the display position only and DDRAM contents remain unchanged, display data entered first can be displayed when the Return Home operation is performed. 15.3 8-bit operation, 2-line display For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line is written. So, if there are only 8 characters in the first line, the DDRAM address must be set after the eighth character is completed (see Table 15). Note that both lines of the display are always shifted together; data does not shift from one line to the other. 15.4 I2C-bus operation, 1-line display A control byte is required with most instructions (see Table 16). 15.5 Initializing by instruction If the power supply conditions for correctly operating the internal reset circuit are not met, the PCF2116 must be initialized by instruction. Table 17 and Table 18 show how this may be performed for 8-bit and 4-bit operation. PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 43 of 56 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 8-bit operation, 1-line display example; using internal reset (character set `A') Step Instruction 1 power supply on (PCF2116 is initialized by the internal reset function) 2 function set 3 Initialized. No display appears. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 0 0 0 Sets to 8-bit operation, selects 1-line display and VLCD = V0. 0 Turns on display and cursor. Entire display is blank after initialization. display mode on/off control 0 0 0 0 0 1 1 1 - entry mode set 0 0 0 0 0 0 1 1 0 - Sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM. Display is not shifted. write data to CGRAM/DDRAM 1 Rev. 05.01 -- 20 July 2007 6 Operation R/W 0 5 Display RS 0 4 NXP Semiconductors PCF2116_family_05 Product data sheet Table 14. 0 0 1 0 1 0 0 0 0 P_ Writes `P'. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. 0 1 0 0 0 PH_ Writes `H'. write data to CGRAM/DDRAM 1 0 0 1 0 7 | | | 8 write data to CGRAM/DDRAM 1 9 1 0 1 0 0 1 1 PHILIPS_ Writes `S'. 0 0 0 0 0 0 1 1 1 PHILIPS_ Sets mode for display shift at the time of write. 0 0 0 0 0 PHILIPS_ Writes space. 0 1 1 0 1 PHILIPS M_ Writes `M'. write data to CGRAM/DDRAM 0 0 0 1 write data to CGRAM/DDRAM 1 0 0 1 0 | | 44 of 56 (c) NXP B.V. 2007. All rights reserved. | 13 write data to CGRAM/DDRAM 1 14 0 0 1 0 0 1 1 1 1 MICROKO Writes `O'. 0 0 1 0 0 0 0 MICROKO Shifts only the cursor position to the left. cursor or display shift 0 0 0 LCD controller / drivers 12 PCF2116 family 1 11 0 entry mode set 0 10 0 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 8-bit operation, 1-line display example; using internal reset (character set `A') Step Instruction 15 cursor or display shift 0 16 0 1 0 0 0 0 MICROKO Shifts only the cursor position to the left. 0 0 1 0 0 0 0 1 1 ICROCO Writes `C' correction. The display moves to the left. 0 0 0 0 1 1 1 0 0 MICROCO Shifts the display and cursor to the right. 0 0 1 0 1 0 0 MICROCO_ Shifts only the cursor to the right. 0 1 1 0 1 ICROCOM_ Writes `M'. cursor or display shift 0 19 0 cursor or display shift 0 Z18 0 Operation write data to CGRAM/DDRAM 1 17 0 Display NXP Semiconductors PCF2116_family_05 Product data sheet Table 14. 0 0 write data to CGRAM/DDRAM 1 0 0 1 0 20 | Rev. 05.01 -- 20 July 2007 | | 21 Return Home 0 0 0 0 0 0 0 0 1 0 PHILIPS M Returns both display and cursor to the original position (address 0). PCF2116 family LCD controller / drivers 45 of 56 (c) NXP B.V. 2007. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 8-bit operation, 2-line display example; using internal reset Step Instruction 1 power supply on (PCF2116 is initialized by the internal reset function) Initialized. No display appears. 2 function set Sets to 8-bit operation, selects 2-line display and voltage generator off. 3 Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 0 0 0 display on/off control - 0 4 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 Rev. 05.01 -- 20 July 2007 0 0 1 0 1 0 0 0 Turns on display and cursor. Entire display is blank after initialization. _ Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM. Display is not shifted. P_ Writes `P'. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. 0 Write data to CGRAM/DDRAM 1 Operation 0 entry mode set 0 5 NXP Semiconductors PCF2116_family_05 Product data sheet Table 15. 0 6 | | | 7 write data to CGRAM/DDRAM Writes `S'. PHILIPS_ 1 8 0 1 0 1 0 0 1 1 set DDRAM address 0 1 PHILIPS 1 0 0 0 0 0 0 _ write data to CGRAM/ DDRAM Writes `M'. 46 of 56 (c) NXP B.V. 2007. All rights reserved. 10 0 0 1 0 0 1 1 0 1 M_ | | | LCD controller / drivers PHILIPS 1 Sets DDRAM address to position the cursor at the head of the 2nd line. PCF2116 family 0 9 0 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 8-bit operation, 2-line display example; using internal reset Step Instruction Display 11 write data to CGRAM/ DDRAM NXP Semiconductors PCF2116_family_05 Product data sheet Table 15. Operation Writes `O'. PHILIPS 1 12 0 0 1 0 0 1 1 1 1 MICROCO_ write data to CGRAM/ DDRAM Sets mode for display shift at the time of write. PHILIPS 0 13 0 0 0 0 0 0 1 1 1 MICROCO_ write data to CGRAM/ DDRAM PHILIPS 1 0 0 1 0 0 1 1 0 1 14 Writes `M'. Display is shifted to the left. The first and second lines shift together. ICROCOM_ | | Rev. 05.01 -- 20 July 2007 | 15 return Home PHILIPS 0 0 0 0 0 0 0 0 1 0 Returns both display and cursor to the original position (address 0). MICROCOM PCF2116 family LCD controller / drivers 47 of 56 (c) NXP B.V. 2007. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS [1]) Step Instruction 1 I2C START Initialized. No display appears. 2 slave address for write During the acknowledge cycle SDA is pulled-down by the PCF2116. 3 4 5 Rev. 05.01 -- 20 July 2007 6 Display SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 0 1 send a control byte for function set R/W 0 0 0 X X X X X 1 function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 1 X 0 0 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 1 1 1 0 1 - DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 1 1 0 1 - - SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 0 1 Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM. Display is not shifted. For writing data to DDRAM, RS must be set to 1. Therefore a control byte is needed. - Co RS R/W 0 1 0 Ack X X X X X 1 - write data to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 0 0 1 Writes `P'. The DDRAM has been selected at power-up. The cursor is incremented by 1 and shifted to the right. P_ write data to DDRAM Writes `H'. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 1 PH_ PCF2116 family send a control byte for write data LCD controller / drivers 48 of 56 (c) NXP B.V. 2007. All rights reserved. 11 Turns on display and cursor. Entire display shows character 20h (blank in ASCII-like character sets). entry mode set slave address for write 10 Selects 1-line display and VLCD = V0; SCL pulse during acknowledge cycle starts execution of instruction. display on/off control 8 9 Ack RS I2C START Operation Control byte sets RS and R/W for following data bytes. Co 7 NXP Semiconductors PCF2116_family_05 Product data sheet Table 16. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS [1]) Step Instruction Display 12 to 15 NXP Semiconductors PCF2116_family_05 Product data sheet Table 16. Operation | | | 16 write data to DDRAM DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 1 1 1 PHILIPS_ start + slave address for write (as step 8) PHILIPS_ I2C 17 (optional 18 control byte 19 Rev. 05.01 -- 20 July 2007 20 stop) I2C Co RS R/W 1 0 0 X X 1 PHILIPS_ DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 1 0 1 PHILIPS control byte for read Co RS R/W 0 1 1 DDRAM content will be read from following instructions. The R/W has to be set to 1 while still in I2C-write mode Ack X X X X X 1 PHILIPS PHILIPS SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 1 1 PHILIPS 8 x SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA. MSB is DB7. During master acknowledge content of DDRAM address 01 is loaded into the I2C interface. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack X X X X X X X X 0 read data: 8 x SCL + master acknowledge 8 x SCL; code of letter `H' is read first. During master acknowledge code of `I' is loaded into the I2C interface. [2] DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 0 PHILIPS read data: 8 x SCL + no master acknowledge [2] DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 1 1 X = don't care. PHILIPS PHILIPS No master acknowledge; After the content of the I2C interface register is shifted out no internal action is performed. No new data is loaded to the interface register, Data Register (DR) is not updated, Address Counter (AC) is not incremented and cursor is not shifted. PCF2116 family PHILIPS During the acknowledge cycle the content of the DR is loaded into the internal I2C interface to be shifted out. In the previous instruction neither a `Set address' nor a `Read data' has been performed. Therefore the content of the DR was unknown. read data: 8 x SCL + master acknowledge [2] I2C stop Sets DDRAM address 0 in Address Counter. (also returns shifted display to original position. DDRAM contents unchanged). This instruction does not update the Data Register (DR). LCD controller / drivers 49 of 56 (c) NXP B.V. 2007. All rights reserved. [1] X 0 slave address for read 26 X 0 22 25 X DB7 I2C START 24 Ack Return Home 21 23 Writes `S'. DB7 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SDA is left at high-impedance by the microcontroller during the READ acknowledge. Table 17. NXP Semiconductors PCF2116_family_05 Product data sheet [2] Initialization by instruction, 8 bit interface [1] Step Description power-on or unknown state wait 2 ms after VDD rises above VPOR RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction 0 0 0 0 1 1 x x x x Function set (interface is 8 bits long) wait 2 ms RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction 0 0 0 0 1 1 x x x x Function set (interface is 8 bits long) wait more than 40 s Rev. 05.01 -- 20 July 2007 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction 0 0 0 0 1 1 x x x x Function set (interface is 8 bits long) BF can be checked after the following instructions. When the BF is not checked the waiting time between instructions is the specified instruction time (see Table 8). RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N M G 0 Function set (interface is 8 bits long). Specify the number of display lines and voltage generator characteristics. 0 0 0 0 0 0 1 0 0 0 Display off. 0 0 0 0 0 0 0 0 0 1 Clear display. 0 0 0 0 0 0 0 1 I/D S Entry mode set. Initialization ends [1] X = don't care. PCF2116 family LCD controller / drivers 50 of 56 (c) NXP B.V. 2007. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCF2116_family_05 Product data sheet Table 18. Initialization by instruction, 4 bit interface. Not applicable for I2C-bus operation. Step Description power-on or unknown state wait 2 ms after VDD rises above VPOR RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction 0 0 0 0 1 1 Function set (interface is 8 bits long) RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction 0 0 0 0 1 1 Function set (interface is 8 bits long) wait 2 ms wait more than 40 s RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction 0 0 0 0 1 1 Function set (interface is 8 bits long) Rev. 05.01 -- 20 July 2007 BF can be checked after the following instructions. When the BF is not checked the waiting time between instructions is the specified instruction time (see Table 8). RS R/W DB7 DB6 DB5 DB4 Function set (set interface to 4 bits long). 0 0 0 0 1 1 Interface is 8 bits long 0 0 0 0 1 0 Function set (interface is 4 bits long). 0 0 N M G 0 Specify the number of display lines and voltage generator characteristics. 0 0 0 0 0 0 0 0 1 0 0 0 Display off. 0 0 0 0 0 0 Clear display. 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 I/D S Entry mode set. LCD controller / drivers 51 of 56 (c) NXP B.V. 2007. All rights reserved. PCF2116 family Initialization ends PCF2116 family NXP Semiconductors LCD controller / drivers 16. Package outline Not applicable. 17. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5. 18. Packing information Table 19. Tray dimensions (see Figure 38) Symbol Description Value A pocket pitch in x direction 5.64 mm B pocket pitch in y direction 5.64 mm C pocket width in x direction 4.08 mm D pocket width in y direction 4.08 mm E tray width in x direction 50.8 mm F tray width in y direction 50.8 mm G cut corner to pocket 1.1 centre 5.66 mm H cut corner to pocket 1.1 centre 5.66 mm x number of pockets, x direction 8 y number of pockets, y direction 8 x G A C H y 1,1 2,1 x,1 D 1,2 B F x,y 1,y E 001aag783 Fig 38. Tray details PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 52 of 56 PCF2116 family NXP Semiconductors PC2116-1 LCD controller / drivers 001aag782 Fig 39. Tray alignment PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 53 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 19. Revision history Table 20. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF2116_FAM_5.01 <tbd> Product data sheet 20070711 (date) PCF2116_FAM_4 Modifications: * * * Character set `A' in CGROM corrected, Section 8.2. * Legal texts have been adapted to the new company name where appropriate. Packing information added, Section 18 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. PCF2116_FAM_4 19970407 Product data sheet PCF2116_3 PCF2116_3 19961025 Product data sheet PCF2116_2 PCF2116_2 19941010 Product data sheet PCF2116A_1 PCF2116A_1 19931215 Product data sheet - PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 54 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 20.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 21. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com PCF2116_family_05 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 05.01 -- 20 July 2007 55 of 56 PCF2116 family NXP Semiconductors LCD controller / drivers 22. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 9 9.1 9.2 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RS: register select (parallel control) . . . . . . . . . 8 R/W: read/write (parallel control) . . . . . . . . . . . 8 E: data bus clock . . . . . . . . . . . . . . . . . . . . . . . 8 DB0 to DB7: data bus . . . . . . . . . . . . . . . . . . . . 9 C1 to C60: column driver outputs . . . . . . . . . . . 9 R1 to R32: row driver outputs . . . . . . . . . . . . . . 9 VLCD: LCD power supply . . . . . . . . . . . . . . . . . 9 V0: VLCD control input . . . . . . . . . . . . . . . . . . . . 9 OSC: oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 9 SCL: serial clock line . . . . . . . . . . . . . . . . . . . . 9 SDA: serial data line . . . . . . . . . . . . . . . . . . . . . 9 SA0: address pin . . . . . . . . . . . . . . . . . . . . . . . 9 T1: test pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . . 9 LCD supply voltage generator for PCF2116x . . 9 Character generator ROM (CGROM) . . . . . . . 11 LCD bias voltage generator . . . . . . . . . . . . . . 15 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 15 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Busy flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address counter (AC) . . . . . . . . . . . . . . . . . . . 16 Display data RAM (DDRAM) . . . . . . . . . . . . . 16 Character generator RAM (CGRAM) . . . . . . . 18 Cursor control circuit. . . . . . . . . . . . . . . . . . . . 18 Timing generator. . . . . . . . . . . . . . . . . . . . . . . 19 LCD row and column drivers . . . . . . . . . . . . . 19 Reset function. . . . . . . . . . . . . . . . . . . . . . . . . 22 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clear display . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Return home. . . . . . . . . . . . . . . . . . . . . . . . . . 27 Entry mode set . . . . . . . . . . . . . . . . . . . . . . . . 27 I/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Display on/off control . . . . . . . . . . . . . . . . . . . 28 D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.4.3 9.5 9.6 9.6.1 9.6.2 9.6.3 9.7 9.8 9.9 9.10 9.11 10 11 11.1 11.2 11.3 11.4 11.5 11.6 12 12.1 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Cursor display shift . . . . . . . . . . . . . . . . . . . . 28 Function set . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DL (parallel mode only) . . . . . . . . . . . . . . . . . 28 N, M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Set CGRAM address . . . . . . . . . . . . . . . . . . . 29 Set DDRAM address . . . . . . . . . . . . . . . . . . . 29 Read busy flag and address . . . . . . . . . . . . . 29 Write data to CGRAM or DDRAM . . . . . . . . . 29 Read data from CGRAM or DDRAM . . . . . . . 29 Interface to microcontroller (parallel interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Interface to microcontroller (I2C-bus interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Characteristics of the I2C-bus . . . . . . . . . . . . 30 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 START and STOP conditions. . . . . . . . . . . . . 31 System configuration . . . . . . . . . . . . . . . . . . . 31 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 31 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 31 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 35 ESD values . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Static characteristics . . . . . . . . . . . . . . . . . . . 35 Dynamic characteristics. . . . . . . . . . . . . . . . . 37 Application information . . . . . . . . . . . . . . . . . 39 4-bit operation, 1-line display using internal reset 42 8-bit operation, 1-line display using internal reset 43 8-bit operation, 2-line display . . . . . . . . . . . . . 43 I2C-bus operation, 1-line display . . . . . . . . . . 43 Initializing by instruction . . . . . . . . . . . . . . . . . 43 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 52 Handling information . . . . . . . . . . . . . . . . . . . 52 Packing information . . . . . . . . . . . . . . . . . . . . 52 Revision history . . . . . . . . . . . . . . . . . . . . . . . 54 Legal information . . . . . . . . . . . . . . . . . . . . . . 55 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 55 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Contact information . . . . . . . . . . . . . . . . . . . . 55 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 July 2007 Document identifier: PCF2116_family_05