AGL030V2-UCG81I - Actel Corporation

November 2009 I

IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• 5 µW Power Consumption in Flash*Freeze Mode

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze Mode

High Capacity

• 15 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design When Powered Off

• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption (except ARM®-enabled IGLOO®

devices) via JTAG (IEEE 1532–compliant)†

•FlashLock

® to Secure FPGA Contents

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X†, and

LVCMOS 2.5 V / 5.0 V Input†

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os‡

• Programmable Output Slew Rate† and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

Clock Conditioning Circuit (CCC) and PLL†

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit† RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• True Dual-Port SRAM (except ×18)†

ARM Processor Support in IGLOO FPGAs

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

† AGL015 and AGL030 devices do not support this feature. ‡ Supported only by AGL015 and AGL030 devices.

IGLOO Product Family

IGLOO Devices AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000

ARM-Enabled IGLOO Devices M1AGL250 M1AGL600 M1AGL1000

System Gates 15 k 30 k 60 k 125 k 250 k 400 k 600 k 1 M

Typical Equivalent Macrocells 128 256 512 1,024 2,048 – – –

VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576

Flash*Freeze Mode (typical, µW) 5 5 10 16 24 32 36 53

RAM kbits (1,024 bits) – – 18 36 36 54 108 144

4,608-Bit Blocks ––488122432

FlashROM Bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k

Secure (AES) ISP 1– – Yes Yes Yes Yes Yes Yes

Integrated PLL in CCCs 2 ––111111

VersaNet Globals 36 6 18 18 18 18 18 18

I/O Banks 22224444

Maximum User I/Os 49 81 96 133 143 194 235 300

Package Pins

UC/CS

QFN

VQFP

FBGA

QN68

UC81/CS81

QN48, QN68,

QN132

VQ100

CS121

QN132

VQ100

FG144 5

CS196

QN132

VQ100

FG144

CS196 4

QN132 4,5

VQ100

FG144

CS196

FG144,

FG256,

FG484

CS281

FG144,

FG256,

FG484

CS281

FG144,

FG256,

FG484

Notes:

1. AES is not available for ARM-enabled IGLOO devices.

2. AGL060 in CS121 does not support the PLL.

3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

4. The M1AGL250 device does not support this package.

5. Device/package support TBD

6. The IGLOOe handbook provides information on higher densities and additional features.

v2.0

IGLOO Low-Power Flash FPGAs

II v2.0

I/Os Per Package1

IGLOO Devices AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000

ARM-Enabled

IGLOO Devices M1AGL250 3M1AGL400 M1AGL600 M1AGL1000

Package

I/O Type

Single-Ended I/O

Single-Ended I/O 2

Differential I/O Pairs

Single-Ended I/O 2

Differential I/O Pairs

Single-Ended I/O 2

Differential I/O Pairs

Single-Ended I/O 2

Differential I/O Pairs

QN48 – 34 – – – – –––– – –

QN68 49 49 – – – – –––– – –

UC81 – 66 – – – – –––– – –

CS81 – 66 – – – – –––– – –

CS121 – – 96 – – – –––– – –

VQ100 – 77 71 71 68 13 –––– – –

QN132 – 81808487

719 7–––– – –

CS196 – – – 133 143 35 143 35 – – – –

FG144 ––96

797 97 24 97 25 97 25 97 25

FG256 – – – – – – 178 38 177 43 177 44

CS281 – – – – – – – – 215 53 215 53

FG484 – – – – – – 194 38 235 60 300 74

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO Low-Power Flash FPGAs

handbook to ensure compliance with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. The M1AGL250 device does not support QN132 or CS196 packages. Refer to the IGLOO Low-Power Flash FPGAs

handbook for position assignments of the 15 LVPECL pairs.

4. FG256 and FG484 are footprint-compatible packages.

5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of

single-ended user I/Os available is reduced by one.

6. "G" indicates RoHS-compliant packages. Refer to "IGLOO Ordering Information" on page III for the location of the

"G" in the part number.

7. Device/package support TBD.

IGLOO FPGAs Package Sizes Dimensions

Package UC81 CS81 CS121 QN68 QN132 CS196 CS281 FG144 VQ100 FG256 FG484

Length × Width

(mm\mm)

4 × 4 5 × 5 6 × 6 8 × 8 8 × 8 8 × 8 10 × 10 13 × 13 14 × 14 17 × 17 23 × 23

Nominal Area

(mm2)

16 25 36 64 64 64 100 169 196 289 529

Pitch (mm) 0.4 0.5 0.5 0.4 0.5 0.5 0.5 1.0 0.5 1.0 1.0

Height (mm) 0.80 0.80 0.99 0.90 0.75 1.20 1.05 1.45 1.00 1.60 2.23

IGLOO Low-Power Flash FPGAs

v2.0 III

IGLOO Ordering Information

Note: Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.

Supply Voltage

2 = 1.2 V to 1.5 V

5 = 1.5 V only

AGL1000 V2 FG

Part Number

IGLOO Devices

Package Type

VQ =Very Thin Quad Flat Pack (0.5 mm pitch)

QN =Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch)

144 I

Package Lead Count

Lead-Free Packaging

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I= Industrial (–40°C to +85°C Ambient Temperature)

Blank = Standard Packaging

G= RoHS-Compliant Packaging (some packages also halogen-free)

PP = Pre-Production

ES=Engineering Sample (Room Temperature Only)

30,000 System Gates

AGL030 =

15,000 System Gates

AGL015 =

60,000 System Gates

AGL060=

125,000 System Gates

AGL125 =

250,000 System Gates

AGL250 =

600,000 System Gates

AGL600 =

400,000 System Gates

AGL400 =

1,000,000 System Gates

AGL1000 =

CS =Chip Scale Package (0.4 mm and 0.5 mm pitches)

UC=Micro Chip Scale Package (0.4 mm pitch)

FG=Fine Pitch Ball Grid Array (1.0 mm pitch)

IGLOO Devices with Cortex-M1

250,000 System Gates

M1AGL250 =

600,000 System Gates

M1AGL600 =

1,000,000 System Gates

M1AGL1000=

IGLOO Low-Power Flash FPGAs

IV v2.0

Temperature Grade Offerings

References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with

M1 (Cortex-M1).

Contact your local Actel representative for device availability:

http://www.actel.com/contact/default.aspx.

AGL015 and AGL030

The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features.

Package

AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000

M1AGL250 4M1AGL600 M1AGL1000

QN48 –C, I– – – –– –

QN68 C, I – – – – – – –

UC81 –C, I– – – –– –

CS81 –C, I– – – –– –

CS121 ––C, I– ––––

VQ100 – C, I C, I C, I C, I – – –

QN132 –C, IC, I

3C, I C, I 3–– –

CS196 –––C, IC, IC, I––

FG144 ––C, I

3C, I C, I C, I C, I C, I

FG256 –––– –C, IC, IC, I

CS281 –––– ––C, IC, I

FG484 –––– –C, IC, IC, I

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

3. Device/package support TBD.

4. The M1AGL250 device does not support FG256 or QN132 packages.

v2.0 1-1

1 – IGLOO Device Family Overview

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a

single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced

features.

The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low-

power mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze

technology simplifies power management through I/O and clock management with rapid recovery

to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 µW)

while the IGLOO device is completely functional in the system. This allows the IGLOO device to

control system power management based on external inputs (e.g., scanning for keyboard stimulus)

while consuming minimal power.

Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power,

single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-

market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and

AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates,

supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM

for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA

fabric. It has a three-stage pipeline that offers a good balance between low-power consumption

and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction

set, has a configurable nested interrupt controller, and can be implemented with or without the

debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOO FPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support

AES decryption.

Flash*Freeze Technology

The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit

ultra-low-power Flash*Freeze mode. IGLOO devices do not need additional components to turn off

I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of

IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction

in power consumption, thus achieving the lowest total system power.

When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and

data is retained.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices

the best fit for portable electronics.

IGLOO Device Family Overview

1-2 v2.0

Flash Advantages

Low Power

Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them

an ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on

current surge and no high-current transition period, both of which occur on many FPGAs.

IGLOO devices also have low dynamic power consumption to further maximize power savings;

power is even further reduced by the use of a 1.2 V core voltage.

Low dynamic power consumption, combined with low static power consumption and Flash*Freeze

technology, gives the IGLOO device the lowest total system power offered by any FPGA.

Security

The nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a

unique combination of reprogrammability and design security without external overhead,

advantages that only an FPGA with nonvolatile flash programming can offer.

IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in IGLOO devices can

be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. AES was adopted by the National Institute of Standards and Technology

(NIST) in 2000 and replaces the 1977 DES standard. IGLOO devices have a built-in AES decryption

engine and a flash-based AES key that make them the most comprehensive programmable logic

device security solution available today. IGLOO devices with AES-based security allow for secure,

remote field updates over public networks such as the Internet, and ensure that valuable IP

remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a

programmed IGLOO device cannot be read back, although secure design verification is possible.

Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been

used to make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES

security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable

IP is protected and secure, making remote ISP possible. An IGLOO device provides the most

impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

IGLOO FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

The Actel flash-based IGLOO devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based IGLOO devices greatly simplifies total system design

and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In

addition, glitches and brownouts in system power will not corrupt the IGLOO device's flash

configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system

power is restored. This enables the reduction or complete removal of the configuration PROM,

expensive voltage monitor, brownout detection, and clock generator devices from the PCB design.

Flash-based IGLOO devices simplify total system design and reduce cost and design risk while

increasing system reliability and improving system initialization time.

IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost

instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike

SRAM-based FPGAs the device does not need to reload configuration and design state from

IGLOO Low-Power Flash FPGAs

v2.0 1-3

external memory components; instead it retains all necessary information to resume operation

immediately.

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, Flash-based IGLOO devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property cannot be compromised or copied.

Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO family device

architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO

family a cost-effective ASIC replacement solution, especially for applications in the consumer,

networking/communications, computing, and avionics markets.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of IGLOO flash-

based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO FPGAs cannot

be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors

occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error

detection and correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The IGLOO family offers many benefits, including nonvolatility and reprogrammability, through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic

utilization without compromising device routability or performance. Logic functions within the

device are interconnected through a four-level routing hierarchy.

IGLOO family FPGAs utilize design and process techniques to minimize power consumption in all

modes of operation.

Advanced Architecture

The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The

IGLOO device consists of five distinct and programmable architectural features (Figure 1-1 on

page 1-4 and Figure 1-2 on page 1-4):

• Flash*Freeze technology

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory†

• Extensive CCCs and PLLs†

• Advanced I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the IGLOO core tile as either a three-input lookup

table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric.

The VersaTile capability is unique to the Actel ProASIC® family of third-generation-architecture

flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash

switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect

programming. Maximum core utilization is possible for virtually any design.

† The AGL015 and AGL030 do not support PLL or SRAM.

IGLOO Device Family Overview

1-4 v2.0

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of IGLOO devices via an IEEE 1532 JTAG interface.

*Not supported by AGL015 and AGL030 devices

Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks (AGL015, AGL030, AGL060, and

AGL125)

Figure 1-2 • IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and

AGL1000)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block*

VersaTile

CCC

I/Os

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Bank 0

Bank 1Bank 1

Bank 0Bank 0

Bank 1

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

(AGL600 and AGL1000)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

IGLOO Low-Power Flash FPGAs

v2.0 1-5

Flash*Freeze Technology

The IGLOO device has an ultra-low power static mode, called Flash*Freeze mode, which retains all

SRAM and register information and can still quickly return to normal operation. Flash*Freeze

technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating

the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and

global I/Os can still be driven and can be toggling without impact on power consumption, clocks

can still be driven or can be toggling without impact on power consumption, and the device retains

all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode

or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No

power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as

5 µW in this mode.

Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the

power management of the device.

The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to

decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a

regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the

inherent low power static (as low as 12 µW) and dynamic capabilities of the IGLOO device. Refer to

Figure 1-3 for an illustration of entering/exiting Flash*Freeze mode.

VersaTiles

The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core

tiles. The IGLOO VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-4 for VersaTile configurations.

Figure 1-3 • IGLOO Flash*Freeze Mode

Actel IGLOO

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-4 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR

D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

IGLOO Device Family Overview

1-6 v2.0

User Nonvolatile FlashROM

Actel IGLOO devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM

can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard IGLOO IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks (except in the AGL015 and AGL030 devices),

as in security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel IGLOO development software solutions, Libero® Integrated Design Environment (IDE)

and Designer, have extensive support for the FlashROM. One such feature is auto-generation of

sequential programming files for applications requiring a unique serial number in each part.

Another feature allows the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

IGLOO devices (except the AGL015 and AGL030 devices) have embedded SRAM blocks along their

north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory

configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have

independent read and write ports that can be configured with different bit widths on each port.

For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded

SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG

macro (except in the AGL015 and AGL030 devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

IGLOO devices provide designers with very flexible clock conditioning circuit (CCC) capabilities.

Each member of the IGLOO family contains six CCCs. One CCC (center west side) has a PLL. The

AGL015 and AGL030 do not have a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides. One

CCC (center west side) has a PLL.

IGLOO Low-Power Flash FPGAs

v2.0 1-7

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis (for PLL only)

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration (for PLL only).

• Output duty cycle = 50% ± 1.5% or better (for PLL only)

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used (for PLL only)

• Maximum acquisition time is 300 µs (for PLL only)

• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL

only)

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

fOUT_CCC (for PLL only)

Global Clocking

IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,

1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO FPGAs support many different I/O

standards—single-ended and differential.

The I/Os are organized into banks, with two or four banks per device. The configuration of these

banks determines the I/O standards supported (Table 1-1).

Table 1-1 • I/O Standards Supported

I/O Bank Type Device and Bank Location

I/O Standards Supported

LVTTL/

LVCMOS

PCI/PCI-X LVPECL, LVDS,

B-LVDS, M-LVDS

Advanced East and west banks of AGL250 and

larger devices

✓✓ ✓

Standard Plus North and south banks of AGL250 and

larger devices

All banks of AGL060 and AGL125K

✓✓

Not supported

Standard All banks of AGL015 and AGL030 ✓Not

supported

Not supported

IGLOO Device Family Overview

1-8 v2.0

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

• Single-Data-Rate applications

• Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications

IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS

and M-LVDS can support up to 20 loads.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of

a card in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data

undisturbed when the system is powered up, while the component itself is powered down, or

when power supplies are floating.

Wide Range I/O Support

Actel IGLOO devices support JEDEC-defined wide range I/O operation. IGLOO devices support both

the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V

to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to

1.575 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components

from the board or move to less costly components with greater tolerances. Wide range eases I/O

bank management and provides enhanced protection from system voltage spikes, while providing

the flexibility to easily run custom voltage applications.

Part Number and Revision Date

Part Number 51700095-001-10

Revised November 2009

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v2.0) Page

v1.6

(September 2009)

The version changed to v2.0 for IGLOO datasheet chapters, indicating the

datasheet contains information based on final characterization.

N/A

v1.5

(April 2009)

The "Reprogrammable Flash Technology" section was modified to add "250 MHz

(1.5 V systems) and 160 MHz (1.2 V systems) System Performance."

"IGLOO Ordering Information" was revised to note that halogen-free packages

are available with RoHS-compliant packaging.

III

Table 1-1 · I/O Standards Supported is new. 1-7

The definitions of hot-swap and cold-sparing were added to the "I/Os with

Advanced I/O Standards" section.

1-7

v1.4

(February 2009)

M1AGL400 is no longer offered and was removed from the "IGLOO Product

Family" table, "IGLOO Ordering Information", and "Temperature Grade

Offerings".

I, III, IV

The –F speed grade is no longer offered for IGLOO devices. The speed grade

column and note regarding –F speed grade were removed from "IGLOO

Ordering Information". The "Speed Grade and Temperature Grade Matrix"

section was removed.

III, IV

v1.3

(December 2008)

The "Advanced I/O" section was revised to include two bullets regarding wide

range power supply voltage support.

IGLOO Low-Power Flash FPGAs

v2.0 1-9

3.0 V wide range was added to the list of supported voltages in the "I/Os with

Advanced I/O Standards" section. The "Wide Range I/O Support" section is new.

1-8

v1.2

(October 2008)

QN48 and QN68 were added to the AGL030 for the following tables:

"IGLOO Product Family"

"IGLOO Ordering Information"

"Temperature Grade Offerings"

N/A

QN132 is fully supported by AGL125 so footnote 3 was removed.

v1.1

(July 2008)

This document was updated to include AGL400 device information. The

following sections were updated:

"IGLOO Product Family"

"IGLOO Ordering Information"

"Temperature Grade Offerings"

"IGLOO Product Family"

Figure 1-2 · IGLOO Device Architecture Overview with Four I/O Banks (AGL250,

AGL600, AGL400, and AGL1000)

N/A

v1.0

(March 2008)

As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core

voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to

1.5 V.

N/A

51700095-001-3

(March 2008)

This document was divided into two sections and given a version number,

starting at v1.0. The first section of the document includes features, benefits,

ordering information, and temperature and speed grade offerings. The second

section is a device family overview.

N/A

51700095-001-2

(February 2008)

The "Low Power" section was updated to change "1.2 V and 1.5 V Core

Voltage" to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 12 µW)"

was removed from "Low-Power Active FPGA Operation."

1.2_V was added to the list of core and I/O voltages in the "Advanced I/O" and

"I/Os with Advanced I/O Standards" sections.

I, 1-7

The "Embedded Memory" section was updated to remove the footnote

reference from the section heading and place it instead after "4,608-Bit" and

"True Dual-Port SRAM (except ×18)."

51700095-001-1

(January 2008)

This document was updated to include AGL015 device information. QN68 is a

new package that was added because it is offered in the AGL015. The following

sections were updated:

"Features and Benefits"

"IGLOO Ordering Information"

"Temperature Grade Offerings"

"IGLOO Product Family"

"IGLOO FPGAs Package Sizes Dimensions"

"AGL015 and AGL030" note

"IGLOO Device Family Overview"

N/A

The "Temperature Grade Offerings" table was updated to include M1AGL600. IV

In the "IGLOO Ordering Information" table, the QN package measurements

were updated to include both 0.4 mm and 0.5 mm.

III

In the "General Description" section, the number of I/Os was updated from 288

to 300.

1-5

51700095-001-0

(January 2008)

The "Low Power" section was updated to change the description of low-power

active FPGA operation to "from 12 µW" from "from 25 µW." The same update

was made in the "General Description" section and the "Flash*Freeze

Technology" section.

I, 1-1, 1-5

Previous Version Changes in Current Version (v2.0) Page

IGLOO Device Family Overview

1-10 v2.0

Advance v0.7

(November 2007)

This document was previously in datasheet Advance v0.7. As a result of moving

to the handbook format, Actel has restarted the version numbers. The new

version number is 51700095-001-0.

N/A

Advance v0.6

(November 2007)

Table 1 • IGLOO Product Family, the "I/Os Per Package1" table, and the

Temperature Grade Offerings table were updated to reflect the following:

CS196 is now supported for AGL250; device/package support for QN132 is to be

determined for AGL250; the CS281 package was added for AGL600 and

AGL1000.

i, ii, iv

Table 2 • IGLOO FPGAs Package Sizes Dimensions is new, and package sizes

were removed from the "I/Os Per Package1" table.

The "I/Os Per Package1"table was updated to reflect 77 instead of 79 single-

ended I/Os for the VG100 package for AGL030.

Advance v0.6

(November 2007)

A note was added to "IGLOO Ordering Information" regarding marking

information.

iii

Advance v0.5

(September 2007)

Table 1 • IGLOO Product Family, the "I/Os Per Package1" table, and the "IGLOO

Ordering Information", and the Temperature Grade Offerings table were

updated to add the UC81 package.

i, ii, iii, iv

Advance v0.4

(September 2007)

Table 1 • IGLOO Product Family was updated for AGL030 in the Package Pins

section to change CS181 to CS81.

Advance v0.3

(August 2007)

Cortex-M1 device information was added to Table 1 • IGLOO Product Family,

the "I/Os Per Package1" table, "IGLOO Ordering Information", and Temperature

Grade Offerings.

i, ii, iii, iv

The number of single-ended I/Os for the CS81 package for AGL030 was updated

to 66 in the "I/Os Per Package1" table.

Advance v0.2

(July 2007)

In Table 1 • IGLOO Product Family, the CS81 package was added for AGL030.

The CS196 was replaced by the CS121 for AGL060. Table note 3 was moved to

the specific packages to which it applies for AGL060: QN132 and FG144.

The CS81 and CS121 packages were added to the "I/Os Per Package1" table. The

number of single-ended I/Os was removed for the CS196 package in AGL060.

Table note 6 was moved to the specific packages to which it applies for AGL060:

QN132 and FG144.

Advance v0.2

(continued)

The CS81 and CS121 packages were added to the Temperature Grade Offerings

table. The temperature grade offerings were removed for the CS196 package in

AGL060. Table note 3 was moved to the specific packages to which it applies for

AGL060: QN132 and FG144.

Advance v0.1 The words "ambient temperature" were added to the temperature range in the

"IGLOO Ordering Information", Temperature Grade Offerings, and "Speed

Grade and Temperature Grade Matrix" sections.

iii, iv

Previous Version Changes in Current Version (v2.0) Page

IGLOO Low-Power Flash FPGAs

v2.0 1-11

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

v2.0 2-1

2 – IGLOO DC and Switching Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI and VMV 3DC I/O buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

TSTG 2Storage Temperature –65 to +150 °C

TJ2Junction Temperature +125 °C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention, maximum limits refer to Table 2-3 on page 2-2, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

3. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.

IGLOO DC and Switching Characteristics

2-2 v2.0

Table 2-2 • Recommended Operating Conditions 4

Symbol Parameter Commercial Industrial Units

TAAmbient Temperature 0 to +70 -40 to +85 °C

TJJunction Temperature 60 to +85 -40 to +100 °C

VCC 31.5 V DC core supply voltage1 1.425 to 1.575 1.425 to 1.575 V

1.2 V–1.5 V wide range core

voltage 2,10 1.14 to 1.575 1.14 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V

Operation 50 to 3.45 0 to 3.45 V

VCCPLL 7Analog power supply (PLL) 1.5 V DC core supply voltage1 1.4 to 1.6 1.4 to 1.6 V

1.2 V–1.5 V wide range core

voltage2, 10 1.14 to 1.26 1.14 to 1.26 V

VCCI and

VMV 81.2 V DC core supply voltage21.14 to 1.26 1.14 to 1.26 V

1.2 V DC wide range DC

supply voltage21.14 to 1.575 1.14 to 1.575 V

1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.0 V DC supply voltage 92.7 to 3.6 2.7 to 3.6 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. For IGLOO® V5 devices

2. For IGLOO V2 devices only, operating at VCCI

≥

VCC

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-24 on page 2-23. VCCI should be at the same voltage within a given I/O

bank.

4. All parameters representing voltages are measured with respect to GND unless otherwise specified.

5. VPUMP can be left floating during operation (not programming mode).

6. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel

recommends that the user follow best design practices using Actel’s timing and power simulation tools.

7. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information.

8. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.

9. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation.

10. All IGLOO devices (V5 and V2) must be programmed with the VCC core voltage at 1.5V. Applications using

the V2 devices powered by 1.2V supply must switch the core supply to 1.5V for in-system programming

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1

Product Grade Programming Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating Junction

Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device

operating conditions and absolute limits.

IGLOO DC and Switching Characteristics

v2.0 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every IGLOO device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In

addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

IGLOO I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V

Ramping down (V5 Devices): 0.5 V < trip_point_down < 1.1 V

Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V

VCC Trip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V

Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V

Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI

Average VCCI–GND Overshoot or

Undershoot Duration

as a Percentage of Clock Cycle2Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at junction temperature at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two

cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

IGLOO DC and Switching Characteristics

2-4 v2.0

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±

0.25 V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes low and/or

the output clock is lost. Refer to the Brownout Voltage section in the Power-Up/-Down Behavior of

Low-Power Flash Devices chapter of the ProASIC®3 and ProASIC3E handbooks for information on

clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

To make sure the transition from input buffers to output buffers is clean, ensure that there is no

path longer than 100 ns from input buffer to output buffer in your design.

Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

Deactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH/VIL , VOH/VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH/VIL levels, and output

buffers do not meet VOH/VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

IGLOO DC and Switching Characteristics

v2.0 2-5

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 2-1

where:

TA = Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5 on page 2-6.

P = Power dissipation

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because V

CCI

are below

specification. For the same reason, input

buffers do not meet V

levels, and

output buffers do not meet V

levels.

Min V

CCI

datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

= 1.14 V

Region 1: I/O Buffers are OFF

Activation trip point:

= 0.85 V ± 0.2 V

Deactivation trip point:

= 0.75 V ± 0.2 V

Activation trip point:

= 0.9 V ± 0.15 V

Deactivation trip point:

= 0.8 V ± 0.15 V

= 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, V

, V

, etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because V

CCI

below specification. For the

same reason, input buffers do not

meet V

levels, and output

buffers do not meet V

levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

CCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V

is below specification.

= V

CCI

+ VT

IGLOO DC and Switching Characteristics

2-6 v2.0

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal

resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The absolute

maximum junction temperature is 110°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for the AGL1000-FG484 package at commercial temperature

and in still air.

EQ 2-2

Disclaimer:

The simulation for determining the junction-to-air thermal resistance is based on JEDEC standards

(JESD51) and assumptions made in building the model. Junction-to-case is based on SEMI G38-88.

JESD51 is only used for comparing one package to another package, provided the two tests uses

the same condition. They have little relevance in actual application and therefore should be used

with a degree of caution.

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

--------------------------------------------------------------------------------------------------------------------------------------- 110°C70°C–

23.3°C/W

------------------------------------ 1 . 7 1 W===

Table 2-5 • Package Thermal Resistivities

Package Type Device Pin Count θjc

θja

UnitStill Air 1 m/s 2.5 m/s

Quad Flat No Lead AGL030 132 TBD 21.4 16.8 15.3 C/W

AGL060 132 TBD 21.2 16.6 15.0 C/W

AGL125 132 TBD 21.1 16.5 14.9 C/W

AGL250 132 TBD 21.0 16.4 14.8 C/W

AGL030 68 13.4 68.4 TBD TBD C/W

Very Thin Quad Flat Pack (VQFP)* 100 10.0 35.3 29.4 27.1 C/W

Chip Scale Package (CSP)* 196 TBD 57.8 47.6 43.3 C/W

Chip Scale Package (CSP) AGLN020 81 12.5 34.0 29.9 28.5 C/W

AGL030 81 12.4 32.8 28.5 27.2 C/W

AGL060 81 11.1 28.8 24.8 23.5 C/W

AGLN250 81 10.4 28.0 23.4 22.0 C/W

AGL250 81 10.4 26.9 22.3 20.9 C/W

Micro Chip Scale Package (UC) AGLN020 81 18.2 44.3 39.0 37.5 C/W

AGL030 81 16.9 40.6 35.2 33.7 C/W

Fine Pitch Ball Grid Array (FBGA) AGL060 144 18.6 55.2 49.4 47.2 C/W

AGL1000 144 6.3 31.6 26.2 24.2 C/W

AGL400 144 6.8 37.6 31.2 29.0 C/W

AGL250 256 12.0 38.6 34.7 33.0 C/W

AGL1000 256 6.6 28.1 24.4 22.7 C/W

AGLE3000 324 2.9 24.0 TBD TBD C/W

AGL1000 484 8.0 23.3 19.0 16.7 C/W

Note: *Thermal Resistances for other device-package combinations will be posted on the next revision.

IGLOO DC and Switching Characteristics

v2.0 2-7

Temperature and Voltage Derating Factors

Calculating Power Dissipation

Quiescent Supply Current

Quiescent supply current (IDD) calculation depends on multiple factors, including operating

voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power modes

usage. Actel recommends using the PowerCalculator and SmartPower software estimation tools to

evaluate the projected static and active power based on the user design, power mode usage,

operating voltage, and temperature.

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,

VCC =1.425V)

For IGLOO V2 or V5 devices, 1.5 V DC Core Supply Voltage

Array Voltage

VCC (V)

Junction Temperature (°C)

–40°C –20°C 0°C 25°C 70°C 85°C 100°C

1.425 0.934 0.953 0.971 1.000 1.007 1.013 1.425

1.500 0.855 0.874 0.891 0.917 0.924 0.929 1.500

1.575 0.799 0.816 0.832 0.857 0.864 0.868 1.575

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,

VCC =1.14V)

For IGLOO V2, 1.2 V DC Core Supply Voltage

Array

Voltage VCC

(V)

Junction Temperature (°C)

–40°C –20°C 0°C 25°C 70°C 85°C 100°C

1.14 0.967 0.973 0.978 0.991 1.000 1.006 1.010

1.20 0.864 0.869 0.874 0.885 0.894 0.899 0.902

1.26 0.794 0.799 0.803 0.814 0.821 0.827 0.830

Table 2-8 • Quiescent Supply Current (IDD) Characteristics, IGLOO Flash*Freeze Mode*

Core

Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units

Typical

(25°C)

1.2 V 44 813202730 44µA

1.5 V 6 6 10 18 34 51 72 127 µA

*IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and

PDC7).

IGLOO DC and Switching Characteristics

2-8 v2.0

Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode (VCC = VJTAG = VPP = 0 V)*

Core

Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units

VCCI/V

JTAG = 1.2 V (per

bank) Typical (25°C)

1.2 V 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 µA

VCCI/VJTAG = 1.5 V (per

bank) Typical (25°C)

1.2 V /

1.5 V

1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 µA

VCCI / VJTAG = 1.8 V (per

bank) Typical (25°C)

1.2 V /

1.5 V

1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 µA

VCCI / VJTAG = 2.5 V (per

bank) Typical (25°C)

1.2 V /

1.5 V

2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 µA

VCCI / VJTAG = 3.3 V (per

bank) Typical (25°C)

1.2 V /

1.5 V

2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 µA

*IDD includes VCC, VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7).

Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO Shutdown Mode (VCC, VCCI = 0 V)*

Core Voltage AGL015 AGL030 Units

Typical (25°C) 1.2 V / 1.5 V 0 0 µA

*IDD includes VCC, VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6

and PDC7).

Table 2-11 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode1

Core

Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units

ICCA Current2

Typical (25°C) 1.2 V 5 6 10 13 18 25 28 42 µA

1.5 V 14 16 20 28 44 66 82 137 µA

ICCI or IJTAG Current3, 4

VCCI/VJTAG = 1.2 V (per

bank) Typical (25°C)

1.2 V 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 µA

VCCI / VJTAG = 1.5 V

(per bank) Typical

(25°C)

1.2 V /

1.5 V

1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 µA

VCCI/VJTAG = 1.8 V (per

bank) Typical (25°C)

1.2 V /

1.5 V

1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 µA

VCCI/VJTAG = 2.5 V (per

bank) Typical (25°C)

1.2 V /

1.5 V

2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 µA

VCCI/VJTAG = 3.3 V (per

bank) Typical (25°C)

1.2 V /

1.5 V

2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 µA

Notes:

1. To calculate total device IDD, multiply the number of banks used by ICCI and add ICCA contribution.

2. Includes VCC , VPUMP and VCCPLL currents.

3. Per VCCI or VJTAG bank

4. Values do not include I/O static contribution (PDC6 and PDC7).

IGLOO DC and Switching Characteristics

v2.0 2-9

Power per I/O Pin

Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Advanced I/O Banks

VCCI (V)

Static Power

PDC6 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.27

3.3V LVCMOS Wide Range3 3.3 – 16.27

2.5 V LVCMOS 2.5 – 4.65

1.8 V LVCMOS 1.8 – 1.61

1.5 V LVCMOS (JESD8-11) 1.5 – 0.96

1.2 V LVCMOS41.2 – 0.58

1.2 V LVCMOS Wide Range41.2 – 0.58

3.3 V PCI 3.3 – 17.67

3.3 V PCI-X 3.3 – 17.67

Differential

LVDS 2.5 2.26 23.39

LVPECL 3.3 5.72 59.05

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

4. Applicable for IGLOO V2 devices only

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

VCCI (V)

Static Power

PDC6 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.41

3.3V LVCMOS Wide Range3 3.3 – 16.41

2.5 V LVCMOS 2.5 – 4.75

1.8 V LVCMOS 1.8 – 1.66

1.5 V LVCMOS (JESD8-11) 1.5 – 1.00

1.2 V LVCMOS41.2 – 0.61

1.2 V LVCMOS Wide Range41.2 – 0.61

3.3 V PCI 3.3 – 17.78

3.3 V PCI-X 3.3 – 17.78

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

3. Applicable for IGLOO V2 devices only.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

IGLOO DC and Switching Characteristics

2-10 v2.0

Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard I/O Banks

VCCI (V)

Static Power

PDC6 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.24

3.3V LVCMOS Wide Range3 3.3 – 17.24

2.5 V LVCMOS 2.5 – 5.64

1.8 V LVCMOS 1.8 – 2.63

1.5 V LVCMOS (JESD8-11) 1.5 – 1.97

1.2 V LVCMOS41.2 – 0.57

1.2 V LVCMOS Wide Range41.2 – 0.57

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

4. Applicable for IGLOO V2 devices only.

Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

Applicable to Advanced I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 – 136.95

3.3V LVCMOS Wide Range45 3.3 – 136.95

2.5 V LVCMOS 5 2.5 – 76.84

1.8 V LVCMOS 5 1.8 – 49.31

1.5 V LVCMOS (JESD8-11) 5 1.5 – 33.36

1.2 V LVCMOS55 1.2 – 16.24

1.2 V LVCMOS Wide Range55 1.2 – 16.24

3.3 V PCI 10 3.3 – 194.05

3.3 V PCI-X 10 3.3 – 194.05

Differential

LVDS – 2.5 7.74 156.22

LVPECL – 3.3 19.54 339.35

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

5. Applicable for IGLOO V2 devices only.

IGLOO DC and Switching Characteristics

v2.0 2-11

Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

Applicable to Standard Plus I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 – 122.16

3.3V LVCMOS Wide Range45 3.3 – 122.16

2.5 V LVCMOS 5 2.5 – 68.37

1.8 V LVCMOS 5 1.8 – 34.53

1.5 V LVCMOS (JESD8-11) 5 1.5 – 23.66

1.2 V LVCMOS55 1.2 – 14.90

1.2 V LVCMOS Wide Range55 1.2 – 14.90

3.3 V PCI 10 3.3 – 181.06

3.3 V PCI-X 10 3.3 – 181.06

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

5. Applicable for IGLOO V2 devices only.

Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

Applicable to Standard I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 – 104.38

3.3V LVCMOS Wide Range45 3.3 – 104.38

2.5 V LVCMOS 5 2.5 – 59.86

1.8 V LVCMOS 5 1.8 – 31.26

1.5 V LVCMOS (JESD8-11) 5 1.5 – 21.96

1.2 V LVCMOS55 1.2 – 13.49

1.2 V LVCMOS Wide Range55 1.2 – 13.49

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

5. Applicable for IGLOO V2 devices only.

IGLOO DC and Switching Characteristics

2-12 v2.0

Power Consumption of Various Internal Resources

Table 2-18 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices

For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Parameter Definition

Device Specific Dynamic Power

(µW/MHz)

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PAC1 Clock contribution of a

Global Rib

14.48 12.77 12.77 11.03 11.03 9.3 9.3 9.3

PAC2 Clock contribution of a

Global Spine

2.48 1.85 1.58 1.58 0.81 0.81 0.41 0.41

PAC3 Clock contribution of a

VersaTile row

0.81

PAC4 Clock contribution of a

VersaTile used as a

sequential module

0.11

PAC5 First contribution of a

VersaTile used as a

sequential module

0.057

PAC6 Second contribution of

a VersaTile used as a

sequential module

0.207

PAC7 Contribution of a

VersaTile used as a

combinatorial module

0.17

PAC8 Average contribution

of a routing net

0.7

PAC9 Contribution of an I/O

input pin (standard-

dependent)

See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.

PAC10 Contribution of an I/O

output pin (standard-

dependent)

See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.

PAC11 Average contribution

of a RAM block during

a read operation

25.00

PAC12 Average contribution

of a RAM block during

a write operation

30.00

PAC13 Dynamic PLL

contribution

2.70

*For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Actel Libero® Integrated Design Environment (IDE).

IGLOO DC and Switching Characteristics

v2.0 2-13

Table 2-19 • Different Components Contributing to the Static Power Consumption in IGLOO Devices

For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Parameter Definition

Device-Specific Static Power (mW)

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PDC1 Array static power in

Active mode

See Table 2-11 on page 2-8.

PDC2 Array static power in

Static (Idle) mode

See Table 2-10 on page 2-8.

PDC3 Array static power in

Flash*Freeze mode

See Table 2-8 on page 2-7.

PDC4 Static PLL contribution 1.84

PDC5 Bank quiescent power

(VCCI-dependent)

See Table 2-11 on page 2-8.

PDC6 I/O input pin static

power (standard-

dependent)

See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.

PDC7 I/O output pin static

power (standard-

dependent)

See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.

*For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Actel Libero® Integrated Design Environment (IDE).

IGLOO DC and Switching Characteristics

2-14 v2.0

Table 2-20 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices

For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage

Parameter Definition

Device Specific Dynamic Power

(µW/MHz)

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PAC1 Clock contribution of a

Global Rib

9.28 8.19 8.19 7.07 7.07 5.96 5.96 5.96

PAC2 Clock contribution of a

Global Spine

1.59 1.19 1.01 1.01 0.52 0.52 0.26 0.26

PAC3 Clock contribution of a

VersaTile row

0.52

PAC4 Clock contribution of a

VersaTile used as a

sequential module

0.07

PAC5 First contribution of a

VersaTile used as a

sequential module

0.045

PAC6 Second contribution of

a VersaTile used as a

sequential module

0.186

PAC7 Contribution of a

VersaTile used as a

combinatorial module

0.11

PAC8 Average contribution

of a routing net

0.45

PAC9 Contribution of an I/O

input pin (standard-

dependent)

See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.

PAC10 Contribution of an I/O

output pin (standard-

dependent)

See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.

PAC11 Average contribution

of a RAM block during

a read operation

25.00

PAC12 Average contribution

of a RAM block during

a write operation

30.00

PAC13 Dynamic PLL

contribution

2.10

*For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Libero IDE.

IGLOO DC and Switching Characteristics

v2.0 2-15

Table 2-21 • Different Components Contributing to the Static Power Consumption in IGLOO Device

For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage

Parameter Definition

Device Specific Static Power (mW)

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PDC1 Array static power in

Active mode

See Table 2-11 on page 2-8.

PDC2 Array static power in

Static (Idle) mode

See Table 2-10 on page 2-8.

PDC3 Array static power in

Flash*Freeze mode

See Table 2-8 on page 2-7.

PDC4 Static PLL contribution 0.90

PDC5 Bank quiescent power

(VCCI-Dependent)

See Table 2-11 on page 2-8.

PDC6 I/O input pin static

power (standard-

dependent)

See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.

PDC7 I/O output pin static

power (standard-

dependent)

See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.

*For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Actel Libero® Integrated Design Environment (IDE).

IGLOO DC and Switching Characteristics

2-16 v2.0

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE

software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock

generated

• The number of combinatorial and sequential cells used in the design

•The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-22 on

page 2-18.

• Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-23 on page 2-18.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-23 on page 2-18. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS * PDC6 + NOUTPUTS * PDC7

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

NBANKS is the number of I/O banks powered in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE* PAC2 + NROW * PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided

in Table 2-22 on page 2-18.

NROW is the number of VersaTile rows used in the design—guidelines are provided in

Table 2-22 on page 2-18.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on

page 2-18.

FCLK is the global clock signal frequency.

IGLOO DC and Switching Characteristics

v2.0 2-17

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on

page 2-18.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on

page 2-18.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-22 on page 2-18.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-22 on page 2-18.

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-23 on page 2-18.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-23

on page 2-18.

PLL Contribution—PPLL

PPLL = PDC4 + PAC13 *FCLKOUT

FCLKOUT is the output clock frequency.1

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its

corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.

IGLOO DC and Switching Characteristics

2-18 v2.0

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at

half of the clock frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-22 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 2-23 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operations 12.5%

β3RAM enable rate for write operations 12.5%

IGLOO DC and Switching Characteristics

v2.0 2-19

User I/O Characteristics

Timing Model

Figure 2-3 • Timing Model

Operating Conditions: Std. Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case

VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL (Applicable to

Advanced I/O Banks Only)L

LVPECL

(Applicable

to Advanced

I/O Banks only)

LVDS,

BLVDS,

M-LVDS

(Applicable for

Advanced I/O

Banks only)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTL Output drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 V Output drive strength = 4 mA

High slew rate

LVTTL Output drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

= 1.22 ns t

= 1.20 ns

= 1.72 ns

= 1.80 ns t

= 3.05 ns (Advanced I/O Banks)

= 1.49 ns

= 4.12 ns (Advanced I/O Banks)

= 0.86 ns t

= 4.42 ns (Advanced I/O Banks)

= 0.92 ns

= 0.87 ns

(Advanced I/O Banks)

CLKQ

= 0.90 ns t

OCLKQ

= 1.02 ns

SUD

= 0.82 ns t

OSUD

= 0.52 ns

= 3.05 ns

(Advanced I/O Banks)

= 0.87 ns (Advanced I/O Banks)

= 1.35 ns

CLKQ

= 0.90 ns

SUD

= 0.82 ns

= 0.87 ns

(Advanced I/O Banks)

ICLKQ

= 0.43 ns

ISUD

= 0.47 ns

= 1.20 ns

IGLOO DC and Switching Characteristics

2-20 v2.0

Figure 2-4 • Input Buffer Timing Model and Delays (example)

tPY

(R)

PAD

Vtrip

GND tPY

(F)

Vtrip

50%

VIH

VCC

VIL

tDOUT

(R)

DIN

GND tDOUT

(F)

50%50%

VCC

PAD Y

tPY

CLK

I/O Interface

DIN

tDIN

To Array

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

IGLOO DC and Switching Characteristics

v2.0 2-21

Figure 2-5 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

IGLOO DC and Switching Characteristics

2-22 v2.0

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

trip

50%

90% V

CCI

trip

50% 50% t

50%

EOUT

PAD

E50%

EOUT (R)

50%

EOUT (F)

PAD

DOUT

EOUT

I/O Interface

EOUT

ZLS

trip

50%

ZHS

trip

50%

EOUT

PAD

E50% 50%

EOUT (R)

EOUT (F)

50%

CCI

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

IGLOO DC and Switching Characteristics

v2.0 2-23

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

I/O

Standard

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option2Slew

Rate

VIL VIH VOL VOH IOL1IOH1

Min.

V Max., V Min., V

Max.

V Max., V Min., V mA mA

3.3 V

LVTTL /

3.3 V

LVCMOS

12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

3.3 V

LVCMOS

Wide

Range3

100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1

2.5 V

LVCMOS

12 mA 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12

1.8 V

LVCMOS

12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12

1.5 V

LVCMOS

12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

1.2 V

LVCMOS42 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 22

1.2 V

LVCMOS

Wide

Range4,5

100 µA 2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 1.575 0.1 VCCI – 0.1 0.1 0.1

3.3 V PCI Per PCI specifications

3.3 V

PCI-X

Per PCI-X specifications

Notes:

1. Currents are measured at 85°C junction temperature.

2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100

A drive strength only. The

configuration will NOT operate at the equivalent software default drive strength. These values are for

Normal Ranges ONLY.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8b specification.

4. Applicable to V2 Devices operating at VCCI ≥ VCC.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12

specification.

IGLOO DC and Switching Characteristics

2-24 v2.0

Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

I/O

Standard

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option2Slew

Rate

VIL VIH VOL VOH IOL IOH

Min.

V Max, V Min, V

Max.

V Max., V Min., V mA mA

3.3 V

LVTTL /

3.3 V

LVCMOS

12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

3.3 V

LVCMOS

Wide

Range3

100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VDD-0.2 0.1 0.1

2.5 V

LVCMOS

12 mA 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12

1.8 V

LVCMOS

8 mA 8 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8

1.5 V

LVCMOS

4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 44

1.2 V

LVCMOS42 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 22

1.2 V

LVCMOS

Wide

Range4

100 µA 2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 1.575 0.1 VCCI – 0.1 0.1 0.1

3.3 V PCI Per PCI specifications

3.3 V

PCI-X

Per PCI-X specifications

Notes:

1. Currents are measured at 85°C junction temperature.

2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100

A drive strength only. The

configuration will NOT operate at the equivalent software default drive strength. These values are for

Normal Ranges ONLY.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8b specification.

4. Applicable to V2 Devices operating at VCCI ≥ VCC.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12

specification.

IGLOO DC and Switching Characteristics

v2.0 2-25

Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard I/O Banks

I/O

Standard

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option2Slew

Rate

VIL VIH VOL VOH IOL1IOH1

Min, V Max, V Min, V

Max.

V Max, V Min, V mA mA

3.3 V

LVTTL /

3.3 V

LVCMOS

8 mA 8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8

3.3 V

LVCMOS

Wide

Range3

100 µA 8 mA High –0.3 0.8 2 3.6 0.2 VDD-0.2 0.1 0.1

2.5 V

LVCMOS

8 mA 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8

1.8 V

LVCMOS

4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4

1.5 V

LVCMOS

2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 22

1.2 V

LVCMOS41 mA 1 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 11

1.2 V

LVCMOS

Wide

Range4,5

100 µA 1 mA High –0.3 0.3 * VCCI 0.7 * VCCI 3.6 0.1 VCCI – 0.1 0.1 0.1

Notes:

1. Currents are measured at 85°C junction temperature.

2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100

A drive strength only. The

configuration will NOT operate at the equivalent software default drive strength. These values are for

Normal Ranges ONLY.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8b

specification.

4. Applicable to V2 Devices operating at VCCI ≥ VCC.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12

specification.

IGLOO DC and Switching Characteristics

2-26 v2.0

Table 2-27 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial1Industrial2

IIL4IIH5IIL4IIH5

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

3.3 V LVCMOS Wide Range 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

1.2 V LVCMOS3 10 10 15 15

1.2 V LVCMOS Wide Range3 10 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

Notes:

1. Commercial range (0°C < TA < 70°C)

2. Industrial range (–40°C < TA < 85°C)

3. Applicable to V2 Devices operating at VCCI ≥ VCC.

4. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL

5. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input

current is larger when operating outside recommended ranges

IGLOO DC and Switching Characteristics

v2.0 2-27

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-28 • Summary of AC Measuring Points

Standard Measuring Trip Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS 1.4 V

3.3 V VCMOS Wide Range 1.4 V

2.5 V LVCMOS 1.2 V

1.8 V LVCMOS 0.90 V

1.5 V LVCMOS 0.75 V

1.2 V LVCMOS 0.60 V

1.2 V LVCMOS Wide Range 0.60 V

3.3 V PCI 0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V PCI-X 0.285 * VCCI (RR)

0.615 * VCCI (FF)

Table 2-29 • I/O AC Parameter Definitions

Parameter Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

IGLOO DC and Switching Characteristics

2-28 v2.0

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard)

Applicable to Advanced I/O Banks

I/O Standard

Drive Strength

Equivalent Software Default

Drive Strength Option1 (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V

LVTTL /

3.3 V

LVCMOS

12 mA 12 High 5 – 0.97 2.09 0.18 0.85 0.66 2.14 1.68 2.67 3.05 5.73 5.27

3.3 V

LVCMOS

Wide

Range2

100 µA 12 High 5 – 0.97 2.93 0.18 1.19 0.66 2.95 2.27 3.81 4.30 6.54 5.87

2.5 V

LVCMOS

12 mA 12 High 5 – 0.97 2.09 0.18 1.08 0.66 2.14 1.83 2.73 2.93 5.73 5.43

1.8 V

LVCMOS

12 mA 12 High 5 – 0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60

1.5 V

LVCMOS

12 mA 12 High 5 – 0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86

3.3 V PCI Per PCI

spec

– High 10 25 20.97 2.32 0.18 0.74 0.66 2.37 1.78 2.67 3.05 5.96 5.38

3.3 V

PCI-X

Per

PCI-X

spec

– High 10 25 20.97 2.32 0.19 0.70 0.66 2.37 1.78 2.67 3.05 5.96 5.38

LVDS 24 mA – High – – 0.97 1.74 0.19 1.35 – – – – – – –

LVPECL 24 mA – High – – 0.97 1.68 0.19 1.16 – – – – – – –

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100

A drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-78 for connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-29

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard)

Applicable to Standard Plus I/O Banks

I/O Standard

Drive Strength

Equivalent Software Default

Drive Strength Option1 (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V

LVTTL /

3.3 V

LVCMOS

12 mA 12 High 5 – 0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99 ns

3.3 V

LVCMOS

Wide

Range2

100 µA 12 High 5 – 0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51 ns

2.5 V

LVCMOS

12 mA 12 High 5 – 0.97 1.75 0.18 1.08 0.66 1.79 1.52 2.38 2.70 5.39 5.11 ns

1.8 V

LVCMOS

8 mA 8 High 5 – 0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36 ns

1.5 V

LVCMOS

4 mA 4 High 5 – 0.97 2.25 0.18 1.18 0.66 2.30 2.00 2.53 2.68 5.89 5.59 ns

3.3 V PCI Per PCI

spec

– High 10 25 2 0.97 1.97 0.18 0.73 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns

3.3 V

PCI-X

Per

PCI-X

spec

– High 10 25 2 0.97 1.97 0.19 0.70 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100

A drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-78 for connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-30 v2.0

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard)

Applicable to Standard I/O Banks

I/O Standard

Drive Strength)

Equivalent Software Default

Drive Strength Option1 (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

Units

3.3 V

LVTTL /

3.3 V

LVCMOS

8 mA 8 High 5 – 0.97 1.85 0.18 0.83 0.66 1.89 1.46 1.96 2.26 ns

3.3 V

LVCMOS

Wide

Range2

100 µA 8 High 5 – 0.97 2.62 0.18 1.17 0.66 2.63 2.02 2.79 3.17 ns

2.5 V

LVCMOS

8 mA 8 High 5 – 0.97 1.88 0.18 1.04 0.66 1.92 1.63 1.95 2.15 ns

1.8 V

LVCMOS

4 mA 4 High 5 – 0.97 2.18 0.18 0.98 0.66 2.22 1.93 1.97 2.06 ns

1.5 V

LVCMOS

2 mA 2 High 5 – 0.97 2.51 0.18 1.14 0.66 2.56 2.21 1.99 2.03 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100

A drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-31

Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard)

Applicable to Advanced I/O Banks

I/O Standard

Drive Strength

Equivalent Software Default

Drive Strength Option1

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V

LVTTL /

3.3 V

LVCMOS

12 mA 12 mA High 5 – 1.55 2.67 0.26 0.98 1.10 2.71 2.18 3.25 3.93 8.50 7.97 ns

3.3 V

LVCMOS

Wide

Range2

100 µA 12 mA High 5 – 1.55 3.73 0.26 1.32 1.10 3.73 2.91 4.51 5.43 9.52 8.69 ns

2.5 V

LVCMOS

12 mA 12 mA High 5 – 1.55 2.64 0.26 1.20 1.10 2.67 2.29 3.30 3.79 8.46 8.08 ns

1.8 V

LVCMOS

12 mA 12 mA High 5 – 1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22 ns

1.5 V

LVCMOS

12 mA 12 mA High 5 – 1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48 ns

1.2 V

LVCMOS

2 mA 2 mA High 5 – 1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns

1.2 V

LVCMOS

Wide

Range3

100 µA 2 mA High 5 – 1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns

3.3 V PCI Per PCI

spec

– High 10 2521.55 2.91 0.26 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns

3.3 V

PCI-X

Per

PCI-X

spec

– High 10 2521.55 2.91 0.25 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns

LVDS 24 mA – High – – 1.55 2.27 0.25 1.57 – – – – – – – ns

LVPECL 24 mA – High – – 1.55 2.24 0.25 1.38 – – – – – – – ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100

A drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12

specification

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-78 for connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-32 v2.0

Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard)

Applicable to Standard Plus I/O Banks

I/O Standard

Drive Strength

Equivalent Software Default

Drive Strength Option1 (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V

LVTTL /

3.3 V

LVCMOS

12 mA 12 High 5 – 1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65 ns

3.3 V

LVCMOS

Wide

Range2

100 µA 12 High 5 – 1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31 ns

2.5 V

LVCMOS

12 mA 12 High 5 – 1.55 2.29 0.26 1.19 1.10 2.32 1.94 2.94 3.52 8.10 7.73 ns

1.8 V

LVCMOS

8 mA 8 High 5 – 1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94 ns

1.5 V

LVCMOS

4 mA 4 High 5 – 1.55 2.68 0.26 1.27 1.10 2.72 2.39 3.07 3.37 8.50 8.18 ns

1.2 V

LVCMOS

2 mA 2 High 5 – 1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns

1.2 V

LVCMOS

Wide

Range3

100 µA 2 High 5 – 1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns

3.3 V PCI Per

PCI

spec

– High 10 252 1.55 2.53 0.26 0.84 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns

3.3 V

PCI-X

Per

PCI-X

spec

– High 10 252 1.55 2.53 0.25 0.85 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100

A drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12

specification

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-78 for connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-33

Table 2-35 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard)

Applicable to Standard I/O Banks

I/O Standard

Drive Strength

Equivalent Software Default

Drive Strength Option1 (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

Units

3.3 V

LVTTL /

3.3 V

LVCMOS

8 mA 8 High 5 – 1.55 2.38 0.26 0.94 1.10 2.41 1.92 2.40 2.96 ns

3.3 V

LVCMOS

Wide

Range3

100 µA 8 High 5 – 1.55 3.33 0.26 1.29 1.10 3.33 2.62 3.34 4.07 ns

2.5 V

LVCMOS

8 mA 8 High 5 – 1.55 2.39 0.26 1.15 1.10 2.42 2.05 2.38 2.80 ns

1.8 V

LVCMOS

4 mA 4 High 5 – 1.55 2.60 0.26 1.08 1.10 2.64 2.33 2.38 2.62 ns

1.5 V

LVCMOS

2 mA 2 High 5 – 1.55 2.92 0.26 1.22 1.10 2.96 2.60 2.40 2.56 ns

1.2 V

LVCMOS

1 mA 1 High 5 – 1.55 3.59 0.26 1.53 1.10 3.47 3.06 2.51 2.49 ns

1.2 V

LVCMOS

Wide

Range3

100 µA 1 High 5 – 1.55 3.59 0.26 1.53 1.10 3.47 3.06 2.51 2.49 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100

A drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b

specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12

specification

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-34 v2.0

Detailed I/O DC Characteristics

Table 2-36 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 2-37 • I/O Output Buffer Maximum Resistances1

Applicable to Advanced I/O Banks

Standard Drive Strength

RPULL-DOWN

(Ω)2RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

3.3 V LVCMOS Wide Range 100 μATBD TBD

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

16 mA 20 40

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

1.2 V LVCMOS42 mA TBD TBD

1.2 V LVCMOS Wide Range4100 μATBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X

specification

25 75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

4. Applicable to IGLOO V2 Devices operating at VCCI ≥ VCC

IGLOO DC and Switching Characteristics

v2.0 2-35

Table 2-38 • I/O Output Buffer Maximum Resistances1

Applicable to Standard Plus I/O Banks

Standard Drive Strength

RPULL-DOWN

(Ω)2RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 25 75

3.3 V LVCMOS Wide Range 100 μATBD TBD

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

1.2 V LVCMOS42 mA TBD TBD

1.2 V LVCMOS Wide Range4100 μATBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X

specification

25 75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

4. Applicable to IGLOO V2 Devices operating at VCCI ≥ VCC

IGLOO DC and Switching Characteristics

2-36 v2.0

Table 2-39 • I/O Output Buffer Maximum Resistances1

Applicable to Standard I/O Banks

Standard Drive Strength

RPULL-DOWN

(Ω)2RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

3.3 V LVCMOS Wide Range 100 μATBD TBD

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

1.5 V LVCMOS 2 mA 200 224

1.2 V LVCMOS 1 mA TBD TBD

1.2 V LVCMOS Wide Range4100 μATBD TBD

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

Table 2-40 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R(WEAK PULL-UP)1

(Ω)

R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

3.3 V Wide Range I/Os 10 k 45k 10 k 45k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

1.2 V 25 k 110 k 25 k 150 k

1.2 V Wide Range I/Os 19 k 110 k 19 k 150 k

Notes:

1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN)

2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)

IGLOO DC and Switching Characteristics

v2.0 2-37

Table 2-41 • I/O Short Currents IOSH/IOSL

Applicable to Advanced I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

12 mA 103 109

16 mA 132 127

24 mA 268 181

3.3 V LVCMOS Wide Range 100 μATBD TBD

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

12 mA 65 74

16 mA 83 87

24 mA 169 124

1.8 V LVCMOS 2 mA 911

4 mA 17 22

6 mA 35 44

8 mA 45 51

12 mA 91 74

16 mA 91 74

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

6 mA 32 39

8 mA 66 55

12 mA 66 55

1.2 V LVCMOS 2 mA TBD TBD

1.2 V LVCMOS Wide Range 100 μATBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X specification 103 109

*TJ = 100°C

IGLOO DC and Switching Characteristics

2-38 v2.0

Table 2-42 • I/O Short Currents IOSH/IOSL

Applicable to Standard Plus I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

12 mA 103 109

16 mA 103 109

3.3 V LVCMOS Wide Range 100 μATBD TBD

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

12 mA 65 74

1.8 V LVCMOS 2 mA 911

4 mA 17 22

6 mA 35 44

8 mA 35 44

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

1.2 V LVCMOS 2 mA TBD TBD

1.2 V LVCMOS Wide Range 100 μATBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X specification 103 109

*TJ = 100°C

Table 2-43 • I/O Short Currents IOSH/IOSL

Applicable to Standard I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

3.3 V LVCMOS Wide Range 100 μATBD TBD

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

1.8 V LVCMOS 2 mA 911

4 mA 17 22

1.5 V LVCMOS 2 mA 13 16

1.2 V LVCMOS 1 mA TBD TBD

1.2 V LVCMOS Wide Range 100 μATBD TBD

*TJ = 100°C

IGLOO DC and Switching Characteristics

v2.0 2-39

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-44 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

–20°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

110°C 3 months

Table 2-45 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time

(min.)

Input Rise/Fall Time

(max.) Reliability

LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C)

LVDS/B-LVDS/M-LVDS/

LVPECL

No requirement 10 ns * 10 years (100°C)

*The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the

board noise. Actel recommends signal integrity evaluation/characterization of the system to

ensure that there is no excessive noise coupling into input signals.

IGLOO DC and Switching Characteristics

2-40 v2.0

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS

3.3 V software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a

specification.

Table 2-46 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 103 109 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

v2.0 2-41

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-7 • AC Loading

Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

03.31.45

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOO DC and Switching Characteristics

2-42 v2.0

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.97 4.47 0.18 0.85 0.66 4.56 3.89 2.24 2.19 8.15 7.48 ns

6 mA Std. 0.97 3.74 0.18 0.85 0.66 3.82 3.37 2.49 2.63 7.42 6.96 ns

8 mA Std. 0.97 3.74 0.18 0.85 0.66 3.82 3.37 2.49 2.63 7.42 6.96 ns

12 mA Std. 0.97 3.23 0.18 0.85 0.66 3.30 2.98 2.66 2.91 6.89 6.57 ns

16 mA Std. 0.97 3.08 0.18 0.85 0.66 3.14 2.89 2.70 2.99 6.74 6.48 ns

24 mA Std. 0.97 3.00 0.18 0.85 0.66 3.06 2.91 2.74 3.27 6.66 6.50 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.97 2.73 0.18 0.85 0.66 2.79 2.22 2.25 2.32 6.38 5.82 ns

6 mA Std. 0.97 2.32 0.18 0.85 0.66 2.37 1.85 2.50 2.76 5.96 5.45 ns

8 mA Std. 0.97 2.32 0.18 0.85 0.66 2.37 1.85 2.50 2.76 5.96 5.45 ns

12 mA Std. 0.97 2.09 0.18 0.85 0.66 2.14 1.68 2.67 3.05 5.73 5.27 ns

16 mA Std. 0.97 2.05 0.18 0.85 0.66 2.10 1.64 2.70 3.12 5.69 5.24 ns

24 mA Std. 0.97 2.07 0.18 0.85 0.66 2.12 1.60 2.75 3.41 5.71 5.20 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.97 3.94 0.18 0.85 0.66 4.02 3.46 1.98 2.03 7.62 7.05 ns

6 mA Std. 0.97 3.24 0.18 0.85 0.66 3.31 2.99 2.21 2.42 6.90 6.59 ns

8 mA Std. 0.97 3.24 0.18 0.85 0.66 3.31 2.99 2.21 2.42 6.90 6.59 ns

12 mA Std. 0.97 2.76 0.18 0.85 0.66 2.82 2.63 2.36 2.68 6.42 6.22 ns

16 mA Std. 0.97 2.76 0.18 0.85 0.66 2.82 2.63 2.36 2.68 6.42 6.22 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-43

Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.97 2.32 0.18 0.85 0.66 2.37 1.90 1.98 2.13 5.96 5.49 ns

6 mA Std. 0.97 1.94 0.18 0.85 0.66 1.99 1.57 2.20 2.53 5.58 5.16 ns

8 mA Std. 0.97 1.94 0.18 0.85 0.66 1.99 1.57 2.20 2.53 5.58 5.16 ns

12 mA Std. 0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99 ns

16 mA Std. 0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.97 3.80 0.18 0.83 0.66 3.88 3.41 1.74 1.78 ns

4 mA Std. 0.97 3.80 0.18 0.83 0.66 3.88 3.41 1.74 1.78 ns

6 mA Std. 0.97 3.15 0.18 0.83 0.66 3.21 2.94 1.96 2.17 ns

8 mA Std. 0.97 3.15 0.18 0.83 0.66 3.21 2.94 1.96 2.17 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.97 2.19 0.18 0.83 0.66 2.24 1.79 1.74 1.87 ns

4 mA Std. 0.97 2.19 0.18 0.83 0.66 2.24 1.79 1.74 1.87 ns

6 mA Std. 0.97 1.85 0.18 0.83 0.66 1.89 1.46 1.96 2.26 ns

8 mA Std. 0.97 1.85 0.18 0.83 0.66 1.89 1.46 1.96 2.26 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-44 v2.0

Applies to 1.2 V DC Core Voltage

Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 5.12 0.26 0.98 1.10 5.20 4.46 2.81 3.02 10.99 10.25 ns

6 mA Std. 1.55 4.38 0.26 0.98 1.10 4.45 3.93 3.07 3.48 10.23 9.72 ns

8 mA Std. 1.55 4.38 0.26 0.98 1.10 4.45 3.93 3.07 3.48 10.23 9.72 ns

12 mA Std. 1.55 3.85 0.26 0.98 1.10 3.91 3.53 3.24 3.77 9.69 9.32 ns

16 mA Std. 1.55 3.69 0.26 0.98 1.10 3.75 3.44 3.28 3.84 9.54 9.23 ns

24 mA Std. 1.55 3.61 0.26 0.98 1.10 3.67 3.46 3.33 4.13 9.45 9.24 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 3.33 0.26 0.98 1.10 3.38 2.75 2.82 3.18 9.17 8.54 ns

6 mA Std. 1.55 2.91 0.26 0.98 1.10 2.95 2.37 3.07 3.64 8.73 8.15 ns

8 mA Std. 1.55 2.91 0.26 0.98 1.10 2.95 2.37 3.07 3.64 8.73 8.15 ns

12 mA Std. 1.55 2.67 0.26 0.98 1.10 2.71 2.18 3.25 3.93 8.50 7.97 ns

16 mA Std. 1.55 2.63 0.26 0.98 1.10 2.67 2.14 3.28 4.01 8.45 7.93 ns

24 mA Std. 1.55 2.65 0.26 0.98 1.10 2.69 2.10 3.33 4.31 8.47 7.89 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 4.56 0.26 0.97 1.10 4.63 3.98 2.54 2.83 10.42 9.76 ns

6 mA Std. 1.55 3.84 0.26 0.97 1.10 3.90 3.50 2.77 3.24 9.69 9.29 ns

8 mA Std. 1.55 3.84 0.26 0.97 1.10 3.90 3.50 2.77 3.24 9.69 9.29 ns

12 mA Std. 1.55 3.35 0.26 0.97 1.10 3.40 3.13 2.93 3.51 9.19 8.91 ns

16 mA Std. 1.55 3.35 0.26 0.97 1.10 3.40 3.13 2.93 3.51 9.19 8.91 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-45

Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 2.89 0.26 0.97 1.10 2.93 2.38 2.53 2.96 8.72 8.17 ns

6 mA Std. 1.55 2.50 0.26 0.97 1.10 2.54 2.04 2.77 3.37 8.33 7.82 ns

8 mA Std. 1.55 2.50 0.26 0.97 1.10 2.54 2.04 2.77 3.37 8.33 7.82 ns

12 mA Std. 1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65 ns

16 mA Std. 1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 1.55 4.39 0.26 0.94 1.10 4.46 3.91 2.17 2.44 ns

4 mA Std. 1.55 4.39 0.26 0.94 1.10 4.46 3.91 2.17 2.44 ns

6 mA Std. 1.55 3.72 0.26 0.94 1.10 3.78 3.43 2.40 2.85 ns

8 mA Std. 1.55 3.72 0.26 0.94 1.10 3.78 3.43 2.40 2.85 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 1.55 2.74 0.26 0.94 1.10 2.78 2.26 2.17 2.55 ns

4 mA Std. 1.55 2.74 0.26 0.94 1.10 2.78 2.26 2.17 2.55 ns

6 mA Std. 1.55 2.38 0.26 0.94 1.10 2.41 1.92 2.40 2.96 ns

8 mA Std. 1.55 2.38 0.26 0.94 1.10 2.41 1.92 2.40 2.96 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-46 v2.0

3.3 V LVCMOS Wide Range

Table 2-62 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Advanced I/O Banks

3.3 V LVCMOS Wide Range VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2IIH3

Drive

Strength

Equivalent

Software

Default Drive

Strength

Option1Min.,

Max.,

Min.,

Max.,

V Min., V µA µA

Max.,

mA4Max.,

mA4µA5µA5

100 µA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 µA 4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 µA 6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 µA 8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 µA 12 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 µA 16 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 µA 24 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

v2.0 2-47

Table 2-63 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Standard Plus I/O Banks

3.3 V LVCMOS Wide Range VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2IIH3

Drive

Strength

Equivalent

Software

Default Drive

Strength

Option1Min.,

Max.,

Min.,

Max.,

V Min., V µA µA

Max.,

mA4Max.,

mA4µA5µA5

100 μA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 μA 4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 μA 6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 μA 8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 μA12 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 μA 16 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

2-48 v2.0

Table 2-64 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Standard I/O Banks

3.3 V LVCMOS Wide Range VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2IIH3

Drive

Strength

Equivalent

Software

Default Drive

Strength

Option1Min.,

Max.,

Min.,

Max.,

V Min., V µA µA

Max.,

mA4Max.,

mA4µA5µA5

100 µA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 µA 4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 µA 6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

100 µA 8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 TBD TBD 10 10

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

Table 2-65 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

03.31.45

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

IGLOO DC and Switching Characteristics

v2.0 2-49

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-66 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Advanced Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

100 µA 4 mA Std. 0.97 6.61 0.18 1.19 0.66 6.63 5.63 3.15 2.98 10.22 9.23 ns

100 µA 6 mA Std. 0.97 5.49 0.18 1.19 0.66 5.51 4.84 3.54 3.66 9.10 8.44 ns

100 µA 8 mA Std. 0.97 5.49 0.18 1.19 0.66 5.51 4.84 3.54 3.66 9.10 8.44 ns

100 µA 12 mA Std. 0.97 4.69 0.18 1.19 0.66 4.71 4.25 3.80 4.10 8.31 7.85 ns

100 µA 16 mA Std. 0.97 4.46 0.18 1.19 0.66 4.48 4.11 3.86 4.21 8.07 7.71 ns

100 µA 24 mA Std. 0.97 4.34 0.18 1.19 0.66 4.36 4.14 3.93 4.64 7.95 7.74 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-67 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Advanced Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

100 µA 4 mA Std. 0.97 3.92 0.18 1.19 0.66 3.94 3.10 3.16 3.17 7.54 6.70 ns

100 µA 6 mA Std. 0.97 3.28 0.18 1.19 0.66 3.30 2.54 3.54 3.86 6.90 6.14 ns

100 µA 8 mA Std. 0.97 3.28 0.18 1.19 0.66 3.30 2.54 3.54 3.86 6.90 6.14 ns

100 µA 12 mA Std. 0.97 2.93 0.18 1.19 0.66 2.95 2.27 3.81 4.30 6.54 5.87 ns

100 µA 16 mA Std. 0.97 2.87 0.18 1.19 0.66 2.89 2.22 3.86 4.41 6.49 5.82 ns

100 µA 24 mA Std. 0.97 2.90 0.18 1.19 0.66 2.92 2.16 3.94 4.86 6.51 5.75 ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

2. Software default selection highlighted in gray.

3. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

IGLOO DC and Switching Characteristics

2-50 v2.0

Table 2-68 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Standard Plus Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

100 µA 4 mA Std. 0.97 5.84 0.18 1.20 0.66 5.86 5.04 2.74 2.71 9.46 8.64 ns

100 µA 6 mA Std. 0.97 4.76 0.18 1.20 0.66 4.78 4.33 3.09 3.33 8.37 7.93 ns

100 µA 8 mA Std. 0.97 4.76 0.18 1.20 0.66 4.78 4.33 3.09 3.33 8.37 7.93 ns

100 µA 12 mA Std. 0.97 4.02 0.18 1.20 0.66 4.04 3.78 3.33 3.73 7.64 7.37 ns

100 µA 16 mA Std. 0.97 4.02 0.18 1.20 0.66 4.04 3.78 3.33 3.73 7.64 7.37 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-69 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Standard Plus Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

100 µA 4 mA Std. 0.97 3.33 0.18 1.20 0.66 3.35 2.68 2.73 2.88 6.94 6.27 ns

100 µA 6 mA Std. 0.97 2.75 0.18 1.20 0.66 2.77 2.17 3.08 3.50 6.36 5.77 ns

100 µA 8 mA Std. 0.97 2.75 0.18 1.20 0.66 2.77 2.17 3.08 3.50 6.36 5.77 ns

100 µA 12 mA Std. 0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51 ns

100 µA 16 mA Std. 0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

3. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

v2.0 2-51

Table 2-70 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Standard Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

100 µA 2 mA Std. 0.97 5.64 0.18 1.17 0.66 5.65 4.98 2.45 2.42 ns

100 µA 4 mA Std. 0.97 5.64 0.18 1.17 0.66 5.65 4.98 2.45 2.42 ns

100 µA 6 mA Std. 0.97 4.63 0.18 1.17 0.66 4.64 4.26 2.80 3.02 ns

100 µA 8 mA Std. 0.97 4.63 0.18 1.17 0.66 4.64 4.26 2.80 3.02 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-71 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Standard Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

100 µA 2 mA 0.97 3.16 0.18 1.17 0.66 3.17 2.53 2.45 2.56 0.97 ns

100 µA 4 mA 0.97 3.16 0.18 1.17 0.66 3.17 2.53 2.45 2.56 0.97 ns

100 µA 6 mA 0.97 2.62 0.18 1.17 0.66 2.63 2.02 2.79 3.17 0.97 ns

100 µA 8 mA 0.97 2.62 0.18 1.17 0.66 2.63 2.02 2.79 3.17 0.97 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

3. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

2-52 v2.0

Applies to 1.2 V DC Core Voltage

Table 2-72 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V

Applicable to Advanced Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

100 µA 4 mA Std. 1.55 7.52 0.26 1.32 1.10 7.52 6.38 3.84 4.02 13.31 12.16 ns

100 µA 6 mA Std. 1.55 6.37 0.26 1.32 1.10 6.37 5.57 4.23 4.73 12.16 11.35 ns

100 µA 8 mA Std. 1.55 6.37 0.26 1.32 1.10 6.37 5.57 4.23 4.73 12.16 11.35 ns

100 µA 12 mA Std. 1.55 5.55 0.26 1.32 1.10 5.55 4.96 4.50 5.18 11.34 10.75 ns

100 µA 16 mA Std. 1.55 5.32 0.26 1.32 1.10 5.32 4.82 4.56 5.29 11.10 10.61 ns

100 µA 24 mA Std. 1.55 5.19 0.26 1.32 1.10 5.19 4.85 4.63 5.74 10.98 10.63 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-73 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7

Applicable to Advanced Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

100 µA 4 mA Std. 1.55 4.75 0.26 1.32 1.10 4.75 3.77 3.84 4.27 10.54 9.56 ns

100 µA 6 mA Std. 1.55 4.10 0.26 1.32 1.10 4.10 3.19 4.24 4.98 9.88 8.98 ns

100 µA 8 mA Std. 1.55 4.10 0.26 1.32 1.10 4.10 3.19 4.24 4.98 9.88 8.98 ns

100 µA 12 mA Std. 1.55 3.73 0.26 1.32 1.10 3.73 2.91 4.51 5.43 9.52 8.69 ns

100 µA 16 mA Std. 1.55 3.67 0.26 1.32 1.10 3.67 2.85 4.57 5.55 9.46 8.64 ns

100 µA 24 mA Std. 1.55 3.70 0.26 1.32 1.10 3.70 2.79 4.65 6.01 9.49 8.58 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

3. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

v2.0 2-53

Table 2-74 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7

Applicable to Standard Plus Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS

Units

100 µA 4 mA Std. 1.55 6.69 0.26 1.32 1.10 6.69 5.73 3.41 3.72 12.48 11.52 ns

100 µA 6 mA Std. 1.55 5.58 0.26 1.32 1.10 5.58 5.01 3.77 4.35 11.36 10.79 ns

100 µA 8 mA Std. 1.55 5.58 0.26 1.32 1.10 5.58 5.01 3.77 4.35 11.36 10.79 ns

100 µA 12 mA Std. 1.55 4.82 0.26 1.32 1.10 4.82 4.44 4.02 4.76 10.61 10.23 ns

100 µA 16 mA Std. 1.55 4.82 0.26 1.32 1.10 4.82 4.44 4.02 4.76 10.61 10.23 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-75 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7

Applicable to Standard Plus Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

100 µA4 mAStd.1.55 4.10 0.26 1.32 1.10 4.10 3.30 3.40 3.92 9.89 9.09 ns

100 µA 6 mA Std. 1.55 3.51 0.26 1.32 1.10 3.51 2.79 3.76 4.56 9.30 8.57 ns

100 µA8 mAStd.1.55 3.51 0.26 1.32 1.10 3.51 2.79 3.76 4.56 9.30 8.57 ns

100 µA12 mA Std. 1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31 ns

100 µA 16 mA Std. 1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

3. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

2-54 v2.0

Table 2-76 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case 1.14 V, Worst-Case VCCI = 2.7

Applicable to Standard Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

100 µA 2 mA Std. 1.55 6.44 0.26 1.29 1.10 6.44 5.64 2.99 3.28 ns

100 µA 4 mA Std. 1.55 6.44 0.26 1.29 1.10 6.44 5.64 2.99 3.28 ns

100 µA 6 mA Std. 1.55 5.41 0.26 1.29 1.10 5.41 4.91 3.35 3.89 ns

100 µA 8 mA Std. 1.55 5.41 0.26 1.29 1.10 5.41 4.91 3.35 3.89 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-77 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7

Applicable to Standard Banks

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1 Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

100 µA 2 mA Std. 1.55 3.89 0.26 1.29 1.10 3.89 3.13 2.99 3.45 ns

100 µA 4 mA Std. 1.55 3.89 0.26 1.29 1.10 3.89 3.13 2.99 3.45 ns

100 µA 6 mA Std. 1.55 3.33 0.26 1.29 1.10 3.33 2.62 3.34 4.07 ns

100 µA 8 mA Std. 1.55 3.33 0.26 1.29 1.10 3.33 2.62 3.34 4.07 ns

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

3. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

v2.0 2-55

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-78 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 2.7 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10

12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10

16 mA –0.3 0.7 1.7 2.7 0.7 1.7 16 16 83 87 10 10

24 mA –0.3 0.7 1.7 2.7 0.7 1.7 24 24 169 124 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-79 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 2.7 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10

12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

2-56 v2.0

Table 2-80 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-8 • AC Loading

Table 2-81 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

02.51.25

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOO DC and Switching Characteristics

v2.0 2-57

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-82 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.97 4.96 0.18 1.08 0.66 5.06 4.59 2.26 2.00 8.66 8.19 ns

6 mA Std. 0.97 4.15 0.18 1.08 0.66 4.24 3.94 2.54 2.51 7.83 7.53 ns

8 mA Std. 0.97 4.15 0.18 1.08 0.66 4.24 3.94 2.54 2.51 7.83 7.53 ns

12 mA Std. 0.97 3.57 0.18 1.08 0.66 3.65 3.47 2.73 2.84 7.24 7.06 ns

16 mA Std. 0.97 3.39 0.18 1.08 0.66 3.46 3.36 2.78 2.92 7.06 6.95 ns

24 mA Std. 0.97 3.38 0.18 1.08 0.66 3.38 3.38 2.83 3.25 6.98 6.98 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-83 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.97 2.77 0.18 1.08 0.66 2.83 2.60 2.26 2.08 6.42 6.19 ns

6 mA Std. 0.97 2.34 0.18 1.08 0.66 2.39 2.08 2.54 2.60 5.99 5.68 ns

8 mA Std. 0.97 2.34 0.18 1.08 0.66 2.39 2.08 2.54 2.60 5.99 5.68 ns

12 mA Std. 0.97 2.09 0.18 1.08 0.66 2.14 1.83 2.73 2.93 5.73 5.43 ns

16 mA Std. 0.97 2.05 0.18 1.08 0.66 2.09 1.78 2.78 3.02 5.69 5.38 ns

24 mA Std. 0.97 2.06 0.18 1.08 0.66 2.10 1.72 2.83 3.35 5.70 5.32 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-84 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.97 4.42 0.18 1.08 0.66 4.51 4.10 1.96 1.85 8.10 7.69 ns

6 mA Std. 0.97 3.62 0.18 1.08 0.66 3.70 3.52 2.21 2.32 7.29 7.11 ns

8 mA Std. 0.97 3.62 0.18 1.08 0.66 3.70 3.52 2.21 2.32 7.29 7.11 ns

12 mA Std. 0.97 3.09 0.18 1.08 0.66 3.15 3.09 2.39 2.61 6.74 6.68 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-58 v2.0

Table 2-85 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.97 2.36 0.18 1.08 0.66 2.41 2.21 1.96 1.92 6.01 5.81 ns

6 mA Std. 0.97 1.97 0.18 1.08 0.66 2.01 1.75 2.21 2.40 5.61 5.34 ns

8 mA Std. 0.97 1.97 0.18 1.08 0.66 2.01 1.75 2.21 2.40 5.61 5.34 ns

12 mA Std. 0.97 1.75 0.18 1.08 0.66 1.79 1.52 2.38 2.70 5.39 5.11 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-86 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.97 4.27 0.18 1.04 0.66 4.36 4.06 1.71 1.62 ns

4 mA Std. 0.97 4.27 0.18 1.04 0.66 4.36 4.06 1.71 1.62 ns

6 mA Std. 0.97 3.54 0.18 1.04 0.66 3.61 3.48 1.95 2.08 ns

8 mA Std. 0.97 3.54 0.18 1.04 0.66 3.61 3.48 1.95 2.08 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-87 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.97 2.24 0.18 1.04 0.66 2.29 2.09 1.71 1.68 ns

4 mA Std. 0.97 2.24 0.18 1.04 0.66 2.29 2.09 1.71 1.68 ns

6 mA Std. 0.97 1.88 0.18 1.04 0.66 1.92 1.63 1.95 2.15 ns

8 mA Std. 0.97 1.88 0.18 1.04 0.66 1.92 1.63 1.95 2.15 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-59

Applies to 1.2 V Core Voltage

Table 2-88 • 2.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 5.59 0.26 1.20 1.10 5.68 5.14 2.82 2.80 11.47 10.93 ns

6 mA Std. 1.55 4.76 0.26 1.20 1.10 4.84 4.47 3.10 3.33 10.62 10.26 ns

8 mA Std. 1.55 4.76 0.26 1.20 1.10 4.84 4.47 3.10 3.33 10.62 10.26 ns

12 mA Std. 1.55 4.17 0.26 1.20 1.10 4.23 3.99 3.30 3.67 10.02 9.77 ns

16 mA Std. 1.55 3.98 0.26 1.20 1.10 4.04 3.88 3.34 3.76 9.83 9.66 ns

24 mA Std. 1.55 3.90 0.26 1.20 1.10 3.96 3.90 3.40 4.09 9.75 9.68 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-89 • 2.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 3.33 0.26 1.20 1.10 3.38 3.09 2.82 2.91 9.17 8.88 ns

6 mA Std. 1.55 2.89 0.26 1.20 1.10 2.93 2.56 3.10 3.45 8.72 8.34 ns

8 mA Std. 1.55 2.89 0.26 1.20 1.10 2.93 2.56 3.10 3.45 8.72 8.34 ns

12 mA Std. 1.55 2.64 0.26 1.20 1.10 2.67 2.29 3.30 3.79 8.46 8.08 ns

16 mA Std. 1.55 2.59 0.26 1.20 1.10 2.63 2.24 3.34 3.88 8.41 8.03 ns

24 mA Std. 1.55 2.60 0.26 1.20 1.10 2.64 2.18 3.40 4.22 8.42 7.97 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-90 • 2.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 5.02 0.26 1.19 1.10 5.11 4.60 2.50 2.62 10.89 10.38 ns

6 mA Std. 1.55 4.21 0.26 1.19 1.10 4.27 4.00 2.76 3.10 10.06 9.79 ns

8 mA Std. 1.55 4.21 0.26 1.19 1.10 4.27 4.00 2.76 3.10 10.06 9.79 ns

12 mA Std. 1.55 3.66 0.26 1.19 1.10 3.71 3.55 2.94 3.41 9.50 9.34 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-60 v2.0

Table 2-91 • 2.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 2.91 0.26 1.19 1.10 2.95 2.66 2.50 2.72 8.74 8.45 ns

6 mA Std. 1.55 2.51 0.26 1.19 1.10 2.54 2.18 2.75 3.21 8.33 7.97 ns

8 mA Std. 1.55 2.51 0.26 1.19 1.10 2.54 2.18 2.75 3.21 8.33 7.97 ns

12 mA Std. 1.55 2.29 0.26 1.19 1.10 2.32 1.94 2.94 3.52 8.10 7.73 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-92 • 2.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 1.55 4.85 0.26 1.15 1.10 4.93 4.55 2.13 2.24 ns

4 mA Std. 1.55 4.85 0.26 1.15 1.10 4.93 4.55 2.13 2.24 ns

6 mA Std. 1.55 4.09 0.26 1.15 1.10 4.16 3.95 2.38 2.71 ns

8 mA Std. 1.55 4.09 0.26 1.15 1.10 4.16 3.95 2.38 2.71 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-93 • 2.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 1.55 2.76 0.26 1.15 1.10 2.80 2.52 2.13 2.32 ns

4 mA Std. 1.55 2.76 0.26 1.15 1.10 2.80 2.52 2.13 2.32 ns

6 mA Std. 1.55 2.39 0.26 1.15 1.10 2.42 2.05 2.38 2.80 ns

8 mA Std. 1.55 2.39 0.26 1.15 1.10 2.42 2.05 2.38 2.80 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-61

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-94 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 4 4 17 22 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 6 6 35 44 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8 45 51 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI– 0.45 12 12 91 74 10 10

16 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCCI – 0.45 16 16 91 74 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-95 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 4 4 17 22 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 6 6 35 44 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8 35 44 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

2-62 v2.0

Table 2-96 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17 22 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-9 • AC Loading

Table 2-97 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.80.95

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOO DC and Switching Characteristics

v2.0 2-63

Timing Characteristics

1.5 V DC Core Voltage

Table 2-98 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.97 6.38 0.18 1.01 0.66 6.51 5.93 2.33 1.56 10.10 9.53 ns

4 mA Std. 0.97 5.35 0.18 1.01 0.66 5.46 5.04 2.67 2.38 9.05 8.64 ns

6 mA Std. 0.97 4.62 0.18 1.01 0.66 4.71 4.44 2.90 2.79 8.31 8.04 ns

8 mA Std. 0.97 4.37 0.18 1.01 0.66 4.46 4.31 2.95 2.89 8.05 7.90 ns

12 mA Std. 0.97 4.32 0.18 1.01 0.66 4.37 4.32 3.03 3.30 7.97 7.92 ns

16 mA Std. 0.97 4.32 0.18 1.01 0.66 4.37 4.32 3.03 3.30 7.97 7.92 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-99 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.97 3.25 0.18 1.01 0.66 3.21 3.25 2.33 1.61 6.80 6.85 ns

4 mA Std. 0.97 2.62 0.18 1.01 0.66 2.68 2.51 2.66 2.46 6.27 6.11 ns

6 mA Std. 0.97 2.31 0.18 1.01 0.66 2.36 2.15 2.90 2.87 5.95 5.75 ns

8 mA Std. 0.97 2.25 0.18 1.01 0.66 2.30 2.08 2.95 2.98 5.89 5.68 ns

12 mA Std. 0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60 ns

16 mA Std. 0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-100 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.97 5.78 0.18 1.01 0.66 5.90 5.32 1.95 1.47 9.49 8.91 ns

4 mA Std. 0.97 4.75 0.18 1.01 0.66 4.85 4.54 2.25 2.21 8.44 8.13 ns

6 mA Std. 0.97 4.07 0.18 1.01 0.66 4.15 3.98 2.46 2.58 7.75 7.57 ns

8 mA Std. 0.97 4.07 0.18 1.01 0.66 4.15 3.98 2.46 2.58 7.75 7.57 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-64 v2.0

Table 2-101 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.97 2.76 0.18 1.01 0.66 2.79 2.76 1.94 1.51 6.39 6.35 ns

4 mA Std. 0.97 2.25 0.18 1.01 0.66 2.30 2.09 2.24 2.29 5.89 5.69 ns

6 mA Std. 0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36 ns

8 mA Std. 0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-102 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.97 5.63 0.18 0.98 0.66 5.74 5.30 1.68 1.24 ns

4 mA Std. 0.97 4.69 0.18 0.98 0.66 4.79 4.52 1.97 1.98 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-103 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 2.62 0.18 0.98 0.66 2.67 2.59 1.67 1.29 2.62 ns

4 mA Std. 2.18 0.18 0.98 0.66 2.22 1.93 1.97 2.06 2.18 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-65

1.2 V DC Core Voltage

Table 2-104 • 1.8 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 6.97 0.26 1.11 1.10 7.08 6.48 2.87 2.29 12.87 12.27 ns

4 mA Std. 1.55 5.91 0.26 1.11 1.10 6.01 5.57 3.21 3.14 11.79 11.36 ns

6 mA Std. 1.55 5.16 0.26 1.11 1.10 5.24 4.95 3.45 3.55 11.03 10.74 ns

8 mA Std. 1.55 4.90 0.26 1.11 1.10 4.98 4.81 3.50 3.66 10.77 10.60 ns

12 mA Std. 1.55 4.83 0.26 1.11 1.10 4.90 4.83 3.58 4.08 10.68 10.61 ns

16 mA Std. 1.55 4.83 0.26 1.11 1.10 4.90 4.83 3.58 4.08 10.68 10.61 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-105 • 1.8 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 3.73 0.26 1.11 1.10 3.71 3.73 2.86 2.34 9.49 9.51 ns

4 mA Std. 1.55 3.12 0.26 1.11 1.10 3.16 2.97 3.21 3.22 8.95 8.75 ns

6 mA Std. 1.55 2.79 0.26 1.11 1.10 2.83 2.59 3.45 3.65 8.62 8.38 ns

8 mA Std. 1.55 2.73 0.26 1.11 1.10 2.77 2.52 3.50 3.75 8.56 8.30 ns

12 mA Std. 1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22 ns

16 mA Std. 1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-106 • 1.8 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 6.32 0.26 1.11 1.10 6.43 5.81 2.47 2.16 12.22 11.60 ns

4 mA Std. 1.55 5.27 0.26 1.11 1.10 5.35 5.01 2.78 2.92 11.14 10.79 ns

6 mA Std. 1.55 4.56 0.26 1.11 1.10 4.64 4.44 3.00 3.30 10.42 10.22 ns

8 mA Std. 1.55 4.56 0.26 1.11 1.10 4.64 4.44 3.00 3.30 10.42 10.22 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-66 v2.0

Table 2-107 • 1.8 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 3.22 0.26 1.11 1.10 3.26 3.18 2.47 2.20 9.05 8.97 ns

4 mA Std. 1.55 2.72 0.26 1.11 1.10 2.75 2.50 2.78 3.01 8.54 8.29 ns

6 mA Std. 1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94 ns

8 mA Std. 1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-108 • 1.8 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 1.55 6.13 0.26 1.08 1.10 6.24 5.79 2.08 1.78 ns

4 mA Std. 1.55 5.17 0.26 1.08 1.10 5.26 4.98 2.38 2.54 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-109 • 1.8 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 3.06 0.26 1.08 1.10 3.10 3.01 2.08 1.83 3.06 ns

4 mA Std. 2.60 0.26 1.08 1.10 2.64 2.33 2.38 2.62 2.60 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-67

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-110 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength

Min.,

V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 6 6 32 39 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 8 8 66 55 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 66 55 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-111 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

2-68 v2.0

Table 2-112 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength

Min.,

V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-10 • AC Loading

Table 2-113 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.50.755

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOO DC and Switching Characteristics

v2.0 2-69

Timing Characteristics

1.5 V DC Core Voltage

Table 2-114 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.97 6.62 0.18 1.17 0.66 6.75 6.06 2.79 2.31 10.35 9.66 ns

4 mA Std. 0.97 5.75 0.18 1.17 0.66 5.86 5.34 3.06 2.78 9.46 8.93 ns

6 mA Std. 0.97 5.43 0.18 1.17 0.66 5.54 5.19 3.12 2.90 9.13 8.78 ns

8 mA Std. 0.97 5.35 0.18 1.17 0.66 5.46 5.20 2.63 3.36 9.06 8.79 ns

12 mA Std. 0.97 5.35 0.18 1.17 0.66 5.46 5.20 2.63 3.36 9.06 8.79 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-115 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.97 2.97 0.18 1.17 0.66 3.04 2.90 2.78 2.40 6.63 6.50 ns

4 mA Std. 0.97 2.60 0.18 1.17 0.66 2.65 2.45 3.05 2.88 6.25 6.05 ns

6 mA Std. 0.97 2.53 0.18 1.17 0.66 2.58 2.37 3.11 3.00 6.18 5.96 ns

8 mA Std. 0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86 ns

12 mA Std. 0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-116 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.97 5.93 0.18 1.18 0.66 6.04 5.46 2.30 2.15 9.64 9.06 ns

4 mA Std. 0.97 5.11 0.18 1.18 0.66 5.21 4.80 2.54 2.58 8.80 8.39 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-70 v2.0

Table 2-117 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.97 2.58 0.18 1.18 0.66 2.64 2.41 2.29 2.24 6.23 6.01 ns

4 mA Std. 0.97 2.25 0.18 1.18 0.66 2.30 2.00 2.53 2.68 5.89 5.59 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-118 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.97 5.88 0.18 1.14 0.66 6.00 5.45 2.00 1.94 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-119 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.97 2.51 0.18 1.14 0.66 2.56 2.21 1.99 2.03 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-71

1.2 V DC Core Voltage

Table 2-120 • 1.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 7.17 0.26 1.27 1.10 7.29 6.60 3.33 3.03 13.07 12.39 ns

4 mA Std. 1.55 6.27 0.26 1.27 1.10 6.37 5.86 3.61 3.51 12.16 11.64 ns

6 mA Std. 1.55 5.94 0.26 1.27 1.10 6.04 5.70 3.67 3.64 11.82 11.48 ns

8 mA Std. 1.55 5.86 0.26 1.27 1.10 5.96 5.71 2.83 4.11 11.74 11.50 ns

12 mA Std. 1.55 5.86 0.26 1.27 1.10 5.96 5.71 2.83 4.11 11.74 11.50 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-121 • 1.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 3.44 0.26 1.27 1.10 3.49 3.35 3.32 3.12 9.28 9.14 ns

4 mA Std. 1.55 3.06 0.26 1.27 1.10 3.10 2.89 3.60 3.61 8.89 8.67 ns

6 mA Std. 1.55 2.98 0.26 1.27 1.10 3.02 2.80 3.66 3.74 8.81 8.58 ns

8 mA Std. 1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48 ns

12 mA Std. 1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-122 • 1.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 6.43 0.26 1.27 1.10 6.54 5.95 2.82 2.83 12.32 11.74 ns

4 mA Std. 1.55 5.59 0.26 1.27 1.10 5.68 5.27 3.07 3.27 11.47 11.05 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-72 v2.0

Table 2-123 • 1.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 3.02 0.26 1.27 1.10 3.07 2.81 2.82 2.92 8.85 8.59 ns

4 mA Std. 1.55 2.68 0.26 1.27 1.10 2.72 2.39 3.07 3.37 8.50 8.18 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-124 • 1.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 1.55 6.35 0.26 1.22 1.10 6.46 5.93 2.40 2.46 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-125 • 1.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 1.55 2.92 0.26 1.22 1.10 2.96 2.60 2.40 2.56 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-73

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose

1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Furthermore, all

LVCMOS 1.2 V software macros comply with LVCMOS 1.2V wide range as specified in the JESD8-12A

specification.

Table 2-126 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.2 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2 TBD TBD 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-127 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.2 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2 TBD TBD 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

2-74 v2.0

Table 2-128 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.2 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL1IIH2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max.,

mA3µA4µA4

1 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 1 1 TBD TBD 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-11 • AC Loading

Table 2-129 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.20.65

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOO DC and Switching Characteristics

v2.0 2-75

Timing Characteristics

1.2 V DC Core Voltage

Table 2-130 • 1.2 V LVCMOS Low Slew

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 8.37 0.26 1.60 1.10 8.04 7.17 3.94 3.52 13.82 12.95 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-131 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-132 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Plus I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 7.59 0.26 1.59 1.10 7.29 6.54 3.30 3.35 13.08 12.33 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-133 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Plus I/O Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-134 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

1 mA Std. 1.55 8.57 0.26 1.53 1.10 8.23 7.38 2.51 2.39 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-76 v2.0

1.2 V LCMOS Wide Range

Table 2-135 • 1.2 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Banks

Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

1 mA Std. 1.55 3.59 0.26 1.53 1.10 3.47 3.06 2.51 2.49 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-136 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range

Applicable to Advanced I/O Banks

1.2 V LVCMOS

Wide Range VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2IIH3

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1Min.,

V Max., V Min., V

Max.,

V Max., V Min., V mA mA

Max.,

mA4Max.,

mA4µA5µA5

100 µA 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 100 100 TBD TBD 10 10

Notes:

1. Note that 1.2 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

IGLOO DC and Switching Characteristics

v2.0 2-77

Timing Characteristics

Refer to LVCMOS 1.2 V (normal range) "Timing Characteristics" on page 2-75 for worst-case timing.

Table 2-137 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range

Applicable to Standard Plus I/O Banks

1.2 V LVCMOS Wide

Range VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2IIH3

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1Min.

V Max., V Min., V

Max.,

V Max., V Min., V mA mA

Max.,

mA4Max.

, mA4µA5µA5

100 µA 2mA –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 100 100 TBD TBD 10 10

Notes:

1. Note that 1.2 V LVCMOS wide range is applicable to 100

A drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

Table 2-138 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range

Applicable to Standard I/O Banks

1.2 V LVCMOS Wide

Range VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2IIH3

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1Min.

V Max., V Min., V

Max.,

V Max., V Min., V mA mA

Max.

mA4Max.

mA4µA5µA5

100 µA 1 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 100 100 TBD TBD 10 10

Notes:

1. Note that 1.2 V LVCMOS wide range is applicable to 100

A drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH<VIN<VCCI. Input

current is larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

Table 2-139 • 1.2 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.20.65

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

IGLOO DC and Switching Characteristics

2-78 v2.0

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI

Bus applications.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable

path characterization are described in Figure 2-12.

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is

described in Table 2-141.

Table 2-140 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced and Standard Plus I/Os

3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1Max, mA1µA2µA2

Per PCI

specification

Per PCI curves 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-12 • AC Loading

Test Point

Enable Path

R to V for t /t /t

CCI LZ ZL ZLS

10 pF for t /t /t /t

ZH ZHS ZLSZL

5 pF for tHZ /tLZ

R to GND for t /t /t

HZ ZH ZH

R = 1 k

Test Point

Datapath

R = 25 R to VCCI for tDP (F)

R to GND for tDP (R)

Table 2-141 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

0 3.3 0.285 * VCCI for tDP(R)

0.615 * VCCI for tDP(F)

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

IGLOO DC and Switching Characteristics

v2.0 2-79

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-142 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.97 2.32 0.19 0.70 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-143 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.97 1.97 0.19 0.70 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-144 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.91 0.25 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-145 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.53 0.25 0.85 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-80 v2.0

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Actel Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-13. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Along with LVDS I/O, IGLOO also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Figure 2-13 • LVDS Circuit Diagram and Board-Level Implementation

140 Ω100 Ω

Z0 = 50 Ω

165 Ω

–

INBUF_LVDS

OUTBUF_LVDS

FPGA FPGA

Bourns Part Number: CAT16-LV4F12

IGLOO DC and Switching Characteristics

v2.0 2-81

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-146 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Typ. Max. Units

VCCI Supply Voltage 2.375 2.5 2.625 V

VOL Output LOW Voltage 0.9 1.075 1.25 V

VOH Output HIGH Voltage 1.25 1.425 1.6 V

IOL 4Output Lower Current 0.65 0.91 1.16 mA

IOH 4Output HIGH Current 0.65 0.91 1.16 mA

VIInput Voltage 0 2.925 V

IIH 3Input HIGH Leakage Current 10 µA

IIL 3Input LOW Leakage Current 10 µA

VODIFF Differential Output Voltage 250 350 450 mV

VOCM Output Common-Mode Voltage 1.125 1.25 1.375 V

VICM Input Common-Mode Voltage 0.05 1.25 2.35 V

VIDIFF Input Differential Voltage 100 350 mV

Notes:

1. ± 5%

2. Differential input voltage = ±350 mV.

3. Currents are measured at 85°C junction temperature.

4. IOL/IOH is defined by VODIFF/(resistor network).

Table 2-147 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V)

1.075 1.325 Cross point

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Table 2-148 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Speed Grade tDOUT tDP tDIN tPY Units

Std. 0.97 1.67 0.19 1.31 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 and Table 2-7

on page 2-7 for derating values.

Table 2-149 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Speed Grade tDOUT tDP tDIN tPY Units

Std. 1.55 2.19 0.25 1.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 and Table 2-7

on page 2-7 for derating values.

IGLOO DC and Switching Characteristics

2-82 v2.0

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard

to high-performance multipoint bus applications. Multidrop and multipoint bus configurations

may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers

require series terminations for better signal quality and to control voltage swing. Termination is

also required at both ends of the bus since the driver can be located anywhere on the bus. These

configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with

appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz

with a maximum of 20 loads. A sample application is given in Figure 2-14. The input and output

buffer delays are available in the LVDS section in Table 2-148 on page 2-81 and Table 2-149 on

page 2-81.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the

required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:

RS=60Ω and RT=70Ω, given Z0=50Ω (2") and Zstub =50Ω (~1.5").

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It

requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It

also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-15. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVDS implementation

because the output standard specifications are different.

Figure 2-14 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

...

BIBUF_LVDS

-T

-R

-T

EN EN EN EN EN

Receiver Transceiver Receiver TransceiverDriver

RSRSRSRSRSRSRSRS

RSRS

Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub

Figure 2-15 • LVPECL Circuit Diagram and Board-Level Implementation

187 W 100 Ω

= 50 Ω

100 Ω

–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA FPGA

Bourns Part Number: CAT16-PC4F12

IGLOO DC and Switching Characteristics

v2.0 2-83

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-150 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Max. Min. Max. Min. Max. Units

VCCI Supply Voltage 3.0 3.3 3.6 V

VOL Output LOW Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V

VOH Output HIGH Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V

VIL, VIH Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V

VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V

VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V

VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V

VIDIFF Input Differential Voltage 300 300 300 mV

Table 2-151 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V)

1.64 1.94 Cross point

*Measuring point = Vtrip. See Table 2-28 on page 2-103 for a complete table of trip points.

Table 2-152 • LVPECL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Speed Grade tDOUT tDP tDIN tPY Units

Std. 0.97 1.67 0.19 1.16 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-153 • LVPECL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Speed Grade tDOUT tDP tDIN tPY Units

Std. 1.55 2.24 0.25 1.37 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

2-84 v2.0

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Preset

Figure 2-16 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

INBUF

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive-Edge Triggered

Pad Out

CLK

Enable

Preset

Data_out

Data

EOUT

DOUT

Enable

CLK

DFN1E1P1

PRE

DFN1E1P1

PRE

DFN1E1P1

PRE

D_Enable

Core

Array

IGLOO DC and Switching Characteristics

v2.0 2-85

Table 2-154 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOSUE Enable Setup Time for the Output Data Register G, H

tOHE Enable Hold Time for the Output Data Register G, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOESUE Enable Setup Time for the Output Enable Register K, H

tOEHE Enable Hold Time for the Output Enable Register K, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tISUE Enable Setup Time for the Input Data Register B, A

tIHE Enable Hold Time for the Input Data Register B, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

*See Figure 2-16 on page 2-84 for more information.

IGLOO DC and Switching Characteristics

2-86 v2.0

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Clear

Figure 2-17 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Enable

CLK

Pad Out

CLK

Enable

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1E1C1

CLR

DFN1E1C1

CLR

DFN1E1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Enable

Active High Clear

Positive-Edge Triggered Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

IGLOO DC and Switching Characteristics

v2.0 2-87

Table 2-155 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOSUE Enable Setup Time for the Output Data Register GG, HH

tOHE Enable Hold Time for the Output Data Register GG, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOESUE Enable Setup Time for the Output Enable Register KK, HH

tOEHE Enable Hold Time for the Output Enable Register KK, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tISUE Enable Setup Time for the Input Data Register BB, AA

tIHE Enable Hold Time for the Input Data Register BB, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

*See Figure 2-17 on page 2-86 for more information.

IGLOO DC and Switching Characteristics

2-88 v2.0

Input Register

Timing Characteristics

1.5 V DC Core Voltage

Figure 2-18 • Input Register Timing Diagram

50%

Preset

Clear

Out_1

CLK

Data

Enable

tISUE

50%

tISUD

tIHD

50% 50%

tICLKQ

tIHE

tIRECPRE tIREMPRE

tIRECCLR tIREMCLR

tIWCLR

tIWPRE

tIPRE2Q

tICLR2Q

tICKMPWH tICKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-156 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description Std. Units

tICLKQ Clock-to-Q of the Input Data Register 0.42 ns

tISUD Data Setup Time for the Input Data Register 0.47 ns

tIHD Data Hold Time for the Input Data Register 0.00 ns

tISUE Enable Setup Time for the Input Data Register 0.67 ns

tIHE Enable Hold Time for the Input Data Register 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.79 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.79 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns

tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns

tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IGLOO DC and Switching Characteristics

v2.0 2-89

1.2 V DC Core Voltage

Output Register

Table 2-157 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V

Parameter Description Std. Units

tICLKQ Clock-to-Q of the Input Data Register 0.68 ns

tISUD Data Setup Time for the Input Data Register 0.97 ns

tIHD Data Hold Time for the Input Data Register 0.00 ns

tISUE Enable Setup Time for the Input Data Register 1.02 ns

tIHE Enable Hold Time for the Input Data Register 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 1.19 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 1.19 ns