1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1996-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Central office quality DTMF transmitter/receiver
• Single 5 Volt power supply
• Adaptive micro interface enables compatibility
with Intel and Motorola processors
• DTMF transmitter/receiver power-down via
register control or power-down pin
• Adjustable guard time
• Automatic tone burst mode
• Call progress tone detection to -30 dBm
Applications
• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Pay phones
• Remote monitor/Control systems
Description
The MT8885 is a monolithic DTMF transc eiver with call
progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
The receiver section is based upon the industry
standard MT8870 DTMF receiver. The transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8885 utilizes an adaptive micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external logic.
September 2005
Ordering Information
MT8885AN 24 Pin SSOP Tubes
MT8885AP 28 Pin PLCC Tubes
MT8885AE 24 Pin PDIP Tubes
MT8885AN1 24 Pin SSOP* Tubes
MT8885AE1 24 Pin PDIP* Tubes
MT8885ANR 24 Pin SSOP Tape & Reel
MT8885ANR1 24 Pin SSOP* Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
MT8885
Integrated DTMF Transceiver with Power
Down and Adaptive Micro Interface
Data Sheet
Figure 1 - Functional Block Diagram
TONE
IN+
IN-
GS
OSC1
OSC2
VDD VRef VSS ESt St/GT
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
∑D/A
Converters Row and
Column
Counters Transmit Data
Register
Data
Bus
Buffer
Tone Burst
Gating Cct.
+
-
Oscillator
Circuit
Bias
Circuit
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Logic
Steering
Logic
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
Interrupt
Logic
I/O
Control
Low Group
Filter
High Group
Filter
Dial
Tone
Filter
PWDN
MT8885 Data Sheet
2
Zarlink Semiconductor Inc.
The MT8885 provides enhanced power-down features. The transmitter and receiver may independently be
powered down via register control.
Figure 2 - Pin Connections
Pin Description
Pin # Name Description
24 28
11 IN+Non-inverting op-amp input.
22 IN-Inverting op-amp input.
34 GSGain Select. Gives access to output of front end differential amplifier for connection
of feedback resistor.
46 V
Ref Reference Voltage output (VDD/2).
57 V
SS Ground (0 V).
68OSC1Oscillator input. This pin can also be driven directly by an external clock.
79OSC2Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
10 12 TONE Output from internal DTMF transmitter.
11 13 R/W(WR)(Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible.
12 14 CS Chip Select input must be gated externally by either address strobe (A S), valid
memory address (VMA) or address latch enable (ALE) signal, depending on
processor used. See Figure 12. Must not be tied low. CMOS compatible.
13 15 RS0 Register Select input. Refer to Table 3 for bit interpre tation. CMOS compatible.
14 17 DS (RD)(Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is
only required when the device is being accessed. CMOS comp atible.
NC
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
IRQ/CP
DS/RD
RS0
24 PIN DIP/SSOP
27
4
3
2
1
28
26
5
6
7
8
9
10
11
25
24
23
22
21
20
19
17
12
13
14
15
16
18
•
NC
VRef
VSS
OSC1
OSC2
NC
NC
GS
NC
IN-
IN+
VDD
ESt
D3
D2
D1
D0
NC
PWDN
NC
TONE
R/W/WR
CS
RS0
NC
DS/RD
IRQ/CP
28 PIN PLCC
MT8885 Data Sheet
3
Zarlink Semiconductor Inc.
1.0 Functional Description
The MT8885 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain
setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and
pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.
The adaptive micro interface allows various microcontrollers to access the MT8885 internal registers.
1.1 Power-Down
The MT8885 provides enhanced power-down functionality to facilitate minimization of supply current consumption.
DTMF transmitter and receiver circuit blocks may be independently powered down via register control. When
asserted, the RxEN control bit powers down all analog and digital circuitry associated solely with the DTMF and
Call Progress receiver. The TOUT control bit is used to disable the transmitter and put all circuitry associated only
with the DTMF transmitter in power-d own mode. With th e TOUT control bit asserted, the T ONE output pin is held in
a high impedance (floating) state. When both power-down control bits are asserted, circuits utilized by both the
DTMF transmitter and receiver are also powered down. This power-down control disables the crystal oscillators,
and the VRef generator. In addition, the IRQ, TONE output and DATA pins are held in a high impedance state.
Finally, the whole device is put in a power-down state when the PWDN pin is asserted.
15 18 IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output
goes low when a valid DTMF tone burst has been transmitted or received. In call
progress mode, this pin will output a rectangular signal representative of the input
signal applied at the input op-amp. The input signal must be within the bandwidth
limits of the call progress filter, see Figure 8.
16 19 PWDN Power-Down (input). Active Hi gh. Powers down the device and in hibits the oscillator.
IRQ and TONE output are high impedance. Data bus is he ld in tri-state. This pin has
no internal pulldown resistor. Therefore, must be tied to logic low when no t u se d .
18-21 21-24 D0-D3 Microprocessor dat a bus. High impedance when CS = 1 or DS =0 (Motorola) or RD =
1 (Intel). TTL compatible.
22 26 ESt Early Steering output. Presents a logic high once the digital algorithm has detected
a valid tone pair (signal condition). Any momentary loss of signal co ndition will cause
ESt to return to a logic low.
23 27 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt
detected at St causes the device to register the detected tone pair and upd ate the
output latch. A voltage less than VTSt frees the device to accept a new tone pair. The
GT output acts to reset the external steering time-constant; its state is a function of
ESt and the voltage on St.
24 28 VDD Positive power supply (5 V typ.).
8, 9
17 3, 5,
10,11
16, 20,
25
NC No Connection.
Pin Description
Pin # Name Description
24 28
MT8885 Data Sheet
4
Zarlink Semiconductor Inc.
1.2 Input Configuration
The input arrangement of the MT8885 provides a differential-input operational amplifier as well as a bias source
(VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-
amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in
Figure 3.
Figure 4 shows the nece ssary connections for a differential input configuration.
1.3 Receiver Section
Separation of th e low and high g roup tones is ach ieved by applying the DT MF signal to the inp ut s of two sixth-order
switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies
(see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each
filter output is followed by a single order switched capac itor filter section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the
incoming DTMF signals.
Figure 3 - Single-Ended Input Configuration
Figure 4 - Differential Input Configuration
CRIN
RF
IN+
IN-
GS
VRef
VOLTAGE GAIN
(AV) = RF / RIN
MT8885
C1
C2
R1
R2
R3
R4 R5
IN+
IN-
GS
VRef
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60 kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(AV diff) - R5/R1 INPUT IMPEDANCE
(ZINdiff) = 2 R12 + (1/ωC)2
MT8885
MT8885 Data Sheet
5
Zarlink Semiconductor Inc.
0= LOGIC LOW, 1= LOGIC HIGH
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state.
1.4 Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt
remains high) for the v alidation period (t GTP), v c reaches the th reshold (VTSt) of the steering logic to register the tone
pair, latching its corresponding 4-bit code (see Table 1) into the Receive Dat a Register. At this point the GT output is
activated and driv es vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to
allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has
been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the
status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is
active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit paus e between signals . Thus, as w ell as re jectin g signals too short to be considered va lid, the
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together
with the capability of selecting the steering time constants externally, allows the designer to tailor performance to
meet a wide variety of system requirement s.
FLOW FHIGH Digit D3D2D1D0
697 1209 1 0001
697 1336 2 0010
697 1477 3 0011
770 1209 4 0100
770 1336 5 0101
770 1477 6 0110
852 1209 7 0111
852 1336 8 1000
852 1477 9 1001
941 1336 0 1010
941 1209 * 1011
941 1477 # 1100
697 1633 A 1101
770 1633 B 1110
852 1633 C 1111
941 1633 D 0000
Table 1 - Functiona l Encode/Deco de Table
MT8885 Data Sheet
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Zarlink Semiconductor Inc.
Figure 5 - Basi c Steering Circuit
1.5 Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen
according to the following inequalities (see Figure 7):
tREC ≥ tDPmax + tGTPmax - tDAmin
tREC ≤ tDPmin + tGTPmin - tDAmax
tID ≥ tDAmax + tGTAmax - tDPmin
tDO ≤ tDAmin + tGTAmin - tDPmax
The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration
to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be
selected by the designer. Different steering arrangements may be used to select independent tone present (tGTP)
and tone absent (tGTA) guard times. This may be necessary to meet system specifications which place both accept
and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor
system parameters su ch as talk-off and noise immunity.
Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will
maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO
would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs
are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
VDD
VDD
St/GT
ESt
C1
Vc
R1
MT8885
tGTA = (R1C1) In (VDD / VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
MT8885 Data Sheet
7
Zarlink Semiconductor Inc.
Figure 6 - Guard Time Adjustment
VDD
St/GT
ESt
VDD
St/GT
ESt
C1
R1 R2
C1
R1 R2
tGTA = (R1C1) In (VDD/VTSt)
tGTP = (RPC1 ) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
tGTA = (RpC1) In (VDD/VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
a) decreasing tGTP; (tGTP < tGTA)
b) decreasing tGTA; (tGTP > tGTA)
MT8885 Data Sheet
8
Zarlink Semiconductor Inc.
2.0 Call Progress Filter
A call progress mode, using the MT8885, can be sele cted to allow the detection of various tones, which identify the
progress of a telephone call on the network. The call progress tone input and DTMF input are common, however,
call progress tones can only be detected when CP mode has been selected.
Figure 7 - Receiver Timing Diagram
Figure 8 - Call Progress Response
Vin
ESt
St/GT
RX0-RX3
b3
b2
Read
Status
Register
IRQ/CP
EVENTS ABCDEF
tREC tREC tID tDO
TONE #n TONE
#n + 1 TONE
#n + 1
tDP tDA
tGTP tGTA
tPStRX
tPStb3
DECODED TONE # (n-1) # n # (n + 1)
VTSt
LEVEL
(dBm)
FREQUENCY (Hz)
-25
0 250 500 750
= Reject
= May Accept
= Accept
MT8885 Data Sheet
9
Zarlink Semiconductor Inc.
Figure 9 - Description o f Timing Events
DTMF signals cannot be detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect
bandwidth of the call progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth
limits of the filter, are hard-limited by a high gain comparator with the IRQ/CP pin serving as the output. The
squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement
to determine the nature of the call progress tone being detected. Frequencies which are in the ‘reject’ area will not
be detected and consequently the IRQ/CP pin will remain low.
3.0 DTMF Generator
The DTMF transmitter employed in the MT8885 is capable of generating all sixteen standard DTMF tone pairs with
low distortion and high accura cy. All frequencies are derived fro m an external 3.579545 MHz crysta l. The sinusoidal
waveforms for the individual tones are digitally synthesized by using row and column programmable dividers and
switched cap acitor D/A co nverters. The row a nd c olumn to nes are mixed and filtered to provide a D TMF signal with
low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format
shown in Table 1 must be written to the transmit Data Register. Note that Table 1 is the same as the receiver
output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and High
Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group
frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB
to compensate for high group attenuation on long loops.
The period of each tone consist s of 32 equal tim e segment s. The period of a tone is controlled by varying the length
of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched
and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time
segment length which will u ltimately de termine the frequency of the tone . Wh en the divider reac hes the appropriate
EXPLANATION OF EVENTS
A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECOD ED AND LATC HED IN RX DATA R EGISTER.
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMAT ION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNC HANGED.
F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, IN FORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
Vin DTMF COMPOSITE INPUT SIGNAL.
ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT STEERING INPUT/GUARD TIME OUTPUT. DR IVES EXTERNAL RC TIMING CIRCUIT.
RX0-RX34-BIT DECODED DATA IN RECEIVE DATA REG ISTER
b3 DELAYED STEERING IN STATUS REGISTER (BIT 3) INDICATES THAT VALID FREQUENC IES HAVE BEEN
PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. AC TIVE LOW
FOR THE DURATION OF A VALID DTMF SIGNAL.
b2 RECEIVE DATA R EGISTER FU LL (BIT 2) IN STATUS REGISTER INDICATES THAT VAL ID DATA IS IN THE
RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ.
IRQ/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS
CLEARED AFTER THE STAT US REGISTER IS READ.
tREC MAXIMUM DTMF SIGNAL DURATION NOT D ETECTED AS VALID. TYPICALLY 20 MS.
tREC MINIMUM DTMF SIGNAL DURATIO N REQUIRED FOR VALID RECOGNITIO N. TYPICALLY 40 MS.
tID MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS. TYPICALLY 40 MS.
tDO MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. TYPICALLY 20 MS.
tDP TIME TO DETECT VALID FREQUENCIES PRESEN T.
tDA TIME TO DETECT VALID FREQUENCIES ABSENT.
tGTP GUARD TIME, TONE PRESENT.
tGTA GUARD TIME, TONE ABSENT.
MT8885 Data Sheet
10
Zarlink Semiconductor Inc.
count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time
segments is fixed at 32, however, by varying the segment length as described above, the frequency can also be
varied. The divider output clocks anothe r counter, which addresses the sinewave lookup ROM.
The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and
highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which
are then mixed by using a low noise summing amplifier. A bandwidth limiting filter is incorporated and serves to
attenuate distortion products above 8 kHz. Figure 10 shows that the distortion products are very low in amplitude.
Figure 10 - Spectrum Plot
4.0 Burst Mode
In certain telephony applications it is required that DTMF signals being generated are of a specific duration
determined either by the particular application or by any one of the exchange transmitter specifications currently
existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is
capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1 ms
which is a st andard interv al for autodialer and cen tral office applications. After the burst/pause has been issued, the
appropriate bit is set in the Status Register to indicate that the transmitter is ready for more data. The timing
described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode)
is selected, the burst/pause duration is doubled to 102 ms ±2 ms. Note that when CP mode and Burst mode have
been selected, DTMF tones may only be transmitted and not received. In applications where a non-standard
burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses
when the burst mode is disabled by enabling and disabling the transmitter.
5.0 Single Tone Generation
A single tone mode is available whereby individual tones from the low group or high group can be generated. This
mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion
measurements. Refer to Control Register B description for details.
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
MT8885 Data Sheet
11
Zarlink Semiconductor Inc.
6.0 Distortion Calculations
The MT8885 is capable of producin g precise tone burst s with minimal error in frequency (see Table 2). The internal
summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic components
and intermodulation product s . The total harmonic distortion for a single tone can be calculated by usin g Eq uatio n 1,
which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency
expressed as a percentage.
Equation 1. THD (%) For a Single Tone
The Fourier component s of the to ne output corre spond to V2f.... Vnf as measured on the output waveform. The tot al
harmonic distortion for a dual tone can be calculated by using Equation 2. VL and VH correspond to the low group
amplitude and high group amplitude, respectively and V2IMD is the sum of all the intermodulation components. The
internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as
shown in Figure 10.
Equation 2. THD (%) For a Dual Tone
Active
Input
Output Frequency (Hz) %Error
Specified Actual
L1 697 699.1 +0.30
L2 770 766.2 -0.49
L3 852 847.4 -0.54
L4 941 948.0 +0.74
H1 1209 1215.9 +0.57
H2 1336 1331.7 -0.32
H3 1477 1471.9 -0.35
H4 1633 1645.0 +0.73
Table 2 - Actual Frequencies Versus Standard Requirements
THD (%) = 100 V2fundamental
V22f + V23f + V24f + .... V2nf
V2L + V2H
V22L + V23L + .... V2nL + V22H +
V23H + .. V2nH + V2IMD
THD (%) = 100
MT8885 Data Sheet
12
Zarlink Semiconductor Inc.
7.0 DTMF Clock Circuit
The internal clock circuit is completed with the additions of a standard television colour burst crystal. The crystal
specification is as follows:
Frequency: 3.579545 MHz
Frequency Tolerance: ±0.1%
Resonance Mode: Parallel
Load Capacitance: 18 p F
Maximum Series Resistance: 150 ohms
Maximum Drive Level: 2 m W
e.g.CTS Knights MP036S
Toyocom TQC-203 -A-9S
A number of MT8885 devices can be connected as shown in Figure 11 such that only one crystal is required.
Alternatively, the OSC1 inputs on all devices can be driven from a CMOS buffer with the OSC2 outputs left
unconnected.
Figure 11 - Common Cr ystal Connection
8.0 Microprocessor Interface
The MT8885 design incorporates an adaptive interface, which allows it to be connected to various kinds of
microprocessors. Key functions of this interface include the following:
• Continuous activity on DS/RD is not necessary to update the internal status registers.
• Compatible with Motorola and Intel processors. Determines whether input timing is that of an Intel or
Motorola controller by monitoring
DS/RD, on the CS falling edge.
• Differentiates between multiplexed and non-multiplexed microprocessor buses. A ddress and data are
latched in accordingly.
Figure 16 shows the timing diagram for the Motorola microcontrollers. The chip select (CS) input is formed by
NANDing address s trobe (AS) and address dec ode output. The MT8885 examines the st ate of DS/RD on the falling
edge of CS. For Motorola bus timing DS/RD must be low on the falling edge of CS. Figure 12(a) shows the
connection of the MC68HC11 Motorola processor to the MT8885 DTMF transceiver.
Figures 17 and 18 are the timing diagrams for Intel mic ro-controllers with multiplexed address and data buses. The
MT8885 latches in the state of DS/RD on the falling edge of CS. When DS/RD is high, Intel processor operation is
selected. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS
can be generated. Figure 12(b) shows the connection of the se Intel processors to the MT8885 transceiver.
MT8885
OSC1 OSC2
MT8885
OSC1 OSC2
MT8885
OSC1 OSC2
3.57954 5 MH z
MT8885 Data Sheet
13
Zarlink Semiconductor Inc.
NOTE: The adaptive micro interface relies on high-to-low transition on CS to recognize the microcontroller
interface. This pin must not be tied permanently low. Only one register access is allowed on any CS assertion.
The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register
contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data
Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is
accomplished with two contro l registers (see Tables 6 and 7), CRA and CRB, whic h have the same address. A write
operation to CRB is ex ecuted by first setting the most signi ficant bit (b3) in CRA. The following write operation to the
same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-
only st atus register indicates the current transceiver state (see Table 8).
A software reset must be included at the beginning of all programs to initialize the control registers upon power-up
or power reset (see Figure 14). Refer to Tables 4-7 for bit descriptions of the two control registers.
The multiplexed IRQ/CP pin can be pro grammed to generate an interrupt upon validation of DTMF signals or when
the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a
square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external
pull-up resistor (see Figure 13).
Table 3 - Internal Register Function s
Table 4 - CRA Bit Positions
Table 5 - CRB Bit Positions
Motorola Intel
RS0 R/W WR RD Function
0 0 0 1 Write to Transmit
Data Register
0 1 1 0 Read from Receive
Data Register
1 0 0 1 Write to Control Register
1 1 1 0 Read from Status Register
b3 b2 b1 b0
RSEL IRQ CP/DTMF TOUT
b3 b2 b1 b0
C/R S/D RxEN BURST
ENABLE
MT8885 Data Sheet
14
Zarlink Semiconductor Inc.
Figure 12 a) & b) - MT8885 Interface Connectio ns for Various Intel and Motorola Micros
Bit Name Description
b0 TOUT Tone Output Control. A logic high enables the tone output; a logic low put s the DTMF
transmitter in power-down mode. The TONE output pin is held in high impedance and the
transmit register is cleared. See Note 1 below.
b1 CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is cap able of receiving and
transmitting DTMF signals. In CP mode a rectangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
b2 IRQ Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control reg ister A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
b3 RSEL Register Select. A lo gic high selec ts control register B for the next write cycle to th e co ntrol
register address. After writing to control register B, the following control register write cycle
will be directed to control register A.
Table 6 - Control Register A Description
MT8885 MT8885
8031/8051/
A8-A15
AS
AD0-AD3
RW
CS
RS0
D0-D3
R/W/WR
DS/RD
E
A8-A15
ALE
P0
RD
WR
CS
D0-D3
RS0
DS/RD
R/W/WR
12 (b) Intel12 (a) Motorola
MC68HC11 8080/8085
MT8885 Data Sheet
15
Zarlink Semiconductor Inc.
Note 1: When both TOUT and RxEN are asserted to power-down, the crystal oscillator and the Vref circuits are powered down.
Bit Name Description
b0 BURST Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital c ode repre senting a DTMF signal (see Table 1) can be written to
the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1 RxEN This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both
circuits. A logic hig h deactivates and put s bo th receiver circuit s into power-down mode. See
Note 1 below.
b2 S/D Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
b3 C/R Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2). Table 7 - Control Register B Description
Bit Name Status Flag Set Status Flag Cleared
b0 IRQ Interrupt has occurred. Bit one
(b1) or bit two (b2) is set. Interrupt is inactive. Cleared after
Status Register is read.
b1 TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2 RECEIVE DATA REGISTER
FULL Vali d data is in the Receive Data
Register. Cleared after Status Register is
read.
b3 DELAYED STEERING Set upon the valid detection of the
absence of a DTMF signal. Cleared upon the detection of a
valid DTMF signal.
Table 8 - Status Register Description
MT8885 Data Sheet
16
Zarlink Semiconductor Inc.
Figure 13 - Application Circuit (Single-Ended Input)
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT8885 ca n be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
RD
RS0
DTMF/CP
INPUT
DTMF
OUTPUT
C1 R1
R2
X-tal
C4 RL
VDD
C3
C2
R4
R3
To µP
or µC
MT8885
R5
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 kΩ 1%
R4 = 3.3 kΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
C4 = 10 nF 10%
X-tal = 3.579545 MHz
R5 = 4.7 MΩ 10%
MT8885 Data Sheet
17
Zarlink Semiconductor Inc.
Figure 14 - Application Notes
INITIALIZATION PROCEDURE
A software reset must be included at the beginning of all programs to initialize the control registers after
power up.
Description: Motorola Intel Data
RS0 R/W WR RD b3 b2 b1 b0
1) Read Status Register 1 1 1 0 X X X X
2) Write to Control Register 1 0 0 1 0 0 0 0
3) Write to Control Register 1 0 0 1 0 0 0 0
4) Write to Control Register 1 0 0 1 1 0 0 0
5) Write to Control Register 1 0 0 1 0 0 0 0
6) Read Status Register 1 1 1 0 X X X X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence: RS0 R/W WR RD b3 b2 b1 b0
1) Write to Control Register A 1 0 0 1 1 1 0 1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B 1 0 0 1 0 0 0 0
(burst mode)
3) Write to Transm it Data Register 0 0 0 1 0 1 1 1
(send a digit 7)
4) Wait for an Interrupt or Poll Status Register
5) Read the Status Register 1 1 1 0 X X X X
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register 0 0 0 1 0 1 0 1
(send a digit 5)
-if bit 2 is set, a DTMF tone has been re ceived, in which case....
Read the Receive Data Register 0 1 1 0 X X X X
-if both bits are set...
Read the Receive Data Register 0 1 1 0 X X X X
Write to Transmit Data Register 0 0 0 1 0 1 0 1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)
MT8885 Data Sheet
18
Zarlink Semiconductor Inc.
* Exceeding these values may cause permanent damage. Functional operation under these conditi ons is not implied.
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings*
Parameter Symbol Min. Max. Units
1 Power supply voltage VDD-VSS VDD -VSS 6.0 V
2 Voltage on any pin VIVSS-0.3 VDD+0.3 V
3 Current at any pin (Except VDD and VSS)10mA
4 Storage temperature TST -65 +150 °C
5 Package power dissipation PD1000 mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter Sym Min. Typ.‡Max. Units Test Conditions
1 Positive power supply VDD 4.75 5.0 5.25 V
2 Operating temperature TO-40 +85 °C
3 Crystal clock frequency fCLK 3.575965 3.579545 3.583124 MHz
DC Electrical Characteristics † - VSS=0 V.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1
S
U
P
P
L
Y
Standby supply current IDDQ 3.0 15.0 µA TOUT and RxEN bits
asserted to power-
down mode
2 Transmitter supply
current IDDTX 5.5 9.0 mA Transmitter fully
enabled and RxEN bit
asserted to power-
down mode
3 Receiver supply current IDDRX 4.5 8.0 mA Receiver fully enabled
and TOUT bit
asserted to power-
down mode
4 Operating supply current IDD 7.0 11.0 mA Device fully enabled
5
I
N
P
U
T
S
High level input volt age
(OSC1) VIHO 0.7
VDD
V
6 Low level input voltage
(OSC1) VILO 0.3 VDD V
7 Steering threshold
voltage VTSt 0.43
VDD
0.46
VDD
0.51
VDD
VV
DD = 5 V
MT8885 Data Sheet
19
Zarlink Semiconductor Inc.
† Characteristics are over recommended operating conditions unless otherwise st ated.
‡ Typical figures are at 25 °C, VDD =5 V and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
8
O
U
T
P
U
T
S
Low level output voltage
(OSC2) VOLO
0.1 VDD V No load
9 High level output voltage
(OSC2) VOHO
0.9
VDD
V No load
10 Output leakage current
(IRQ) (Tone) IOZT
110µA
11 VRef output voltage VRef 0.47
VDD
0.53
VDD
V No load
12 VRef output resistance ROR 2.5 kΩNote 9
13 D
i
g
i
t
a
l
Low level input voltage VIL 0.3 VDD V
14 High level input voltage VIH 0.7
VDD
V
15 Input leakage current IIZ 10 µAV
IN=VSS to VDD
16 Output high impedance IOZD 10 µAV
IN=VSS to VDD
17 Data
Bus Source current IOHD 1.4 6.6 mA VOH=0.9VDD
18 Sink current IOLD 2.0 4.0 mA VOL=0.1VDD
19 ESt
and
St/G
T
Source current IOHE 0.5 3.0 mA VOH=0.9VDD
20 Sink current IOLE 2.0 4 mA VOL=0.1VDD
21 IRQ/
CP Sink current IOLI 4.0 16.0 mA VOL=0.1VDD
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (V SS) unless otherwise stated, VSS= 0V, VDD=5 V, TO=25°C.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Input leakage current IIN 100 nA VSS ≤ VIN ≤ VDD
Note 9
2 Input resistance RIN 10 MΩNote 9
3 Input offset voltage VOS 25 mV Note 9
4 Power supply rejection PSRR 50 dB 1 kHz, See Note 9
5 Common mode rejection CMRR 40 dB VSS + 0.75V ≤ VIN ≤ VDD -
0.75V biased at VREF =
1.5 V
Note 9
6 DC open loop voltage gain AVOL 32 dB Note 9
7 Unity gain bandwidth fc 0.3 MHz Note 9
DC Electrical Characteristics (continued)† - VSS=0 V.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
MT8885 Data Sheet
20
Zarlink Semiconductor Inc.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
† Characteristics are over recommended operating conditions unless otherwise st ated.
‡ Typical figures are at 25°C, VDD = 5 V, and for design aid only: not guaranteed and not subject to production testing.
* *See “Notes” following AC Electrical Characteristics Tables.
† Characteristics are over recommended operating conditions unless otherwise st ated.
‡ Typical figures are at 25°C, VDD=5 V, and for desi gn aid only: not gu aranteed and not subject to production testing.
8 Outpu t voltage swing VO2.2 Vpp RLGS ≥ 100 kΩ to VSS at
GS, 3 KHz
Note 9
9 Allowable capacitive load
(GS) CLGS 100 pF Note 9
10 Allowable resistive load (GS) RLGS 50 kΩNote 9
11 Common mode range VCM 1.5 Vpp VDD = 5 V, No Load
Note 9
MT8885 AC Electrical Characteristics† - Voltages are with res pect to ground (VSS) unless otherwise stated.
Characteristics Sym. Min. Typ.
‡Max. Units Notes*
1R
X
Valid input signal levels
(each tone of compo site
signal)
-29 1 dBm 1, 2, 3, 5, 6
27.5 869 mVRMS 1, 2, 3, 5, 6
2
R
X
Positive twist accept 8 dB 2, 3, 6, 9
3 Negative twist accept 8 dB 2, 3, 6, 9
4 Freq. deviation accept ±1.5%± 2 Hz 2, 3, 5
5 Freq. deviation reject ±3.5% 2, 3, 5
6 Third tone tolerance -16 dB 2, 3, 4, 5, 9, 10
7 Noise tolerance -12 dB 2, 3, 4, 5, 7, 9, 10
8 Dial tone tolerance 22 dB 2, 3, 4, 5, 8, 9
AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Conditions
1 Accept Bandwidth fA320 500 Hz @ -25 dBm
Note 9
2 Lower freq. (REJECT) fLR 290 Hz @ -25 dBm
Note 9
3 Upper freq. (REJECT) fHR 540 Hz @ -25 dBm
Note 9
4 Call progress tone detect level (total
power) -30 dBm
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (V SS) unless otherwise stated, VSS= 0V, VDD=5 V, TO=25°C.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
MT8885 Data Sheet
21
Zarlink Semiconductor Inc.
† Timing is over recommended temperature & powe r supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics † - Voltages are with respec t to ground (VSS), unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Conditions
1T
O
N
E
I
N
Tone present detect time tDP 4 11 14 ms Note 11
2 Tone absent detect time tDA 0.5 4 8.5 ms Note 11
3 Delay St to b3 tPStb3 20 µs Figure 7, Note 9
4 Delay St to RX0-RX3tPStRX 11 µs Figure 7, Note 9
5
T
O
N
E
O
U
T
Tone burst duration tBST 50 52 ms DTMF mode
6 Tone pause duration tPS 50 52 ms DTMF mode
7 Tone burst duration (extended) tBSTE 100 104 ms Call Progress mode
8 Tone pause duration
(extended) tPSE 100 104 ms Call Progress mode
9 High group output level VHOUT -6.1 -2.1 dBm RLT=10 kΩ
10 Low group output level VLOUT -8.1 -4.1 dBm RLT=10 kΩ
11 Pre-emphasis dBP23dBR
LT=10 kΩ
12 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth
13 RLT=10 kΩ, Note 9
14 Frequency dev iation fD±0.7 ±1.5 % fC=3.579545 MHz
15 Output load resistance RLT 10 50 kΩNote 9
16
X
T
A
L
Crystal/c lock frequency fC3.575
93.579
53.583
1MHz Note 9
17 Clock input rise and fall time tCLRF 110 ns Ext. clock, Note 9
18 Clock input duty cycle DCCL 40 50 60 % Ext. clock, Note 9
19 OSC2 load capacitance CLO 30 pF
20 Oscillator st art-up time tOST 10 ms Note 9
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Conditions
1RD
/WR low pulse width tCL 200 400 ns Figure 15, Note 12
tCL + tCH ≥ 1000 ns
2 DS high pulse width tCH 200 400 ns Figure 15, Note 12
tCL + tCH ≥ 1000 ns
3 Rise and fall time all digital inputs tR,tF20 ns Figure 15
4R/W
setup time tRWS 23 ns Figures 16
5R/W
hold time tRWH 20 ns Figures 16
6 Address setup time (RS0) tAS 0 ns Figur e s 16 - 18
7 Address hold time (RS0) tAH 40 ns Figures 16 - 18
MT8885 Data Sheet
22
Zarlink Semiconductor Inc.
† Characteristics are over recommended operating conditions unless otherwise st ated
‡ Typical figures are at 25°C, VDD=5 V, and for desi gn aid only: not gu aranteed and not subject to production testing
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration =40 ms. Tone pause = 40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the comp osite si gnal have a n equal a mplitude.
6) The tone pair is deviated by ± 1.5%±2 Hz.
7) Bandwidth limited (3 kH z) Gaussian noise.
8) The precise di al tone frequ encies are 350 and 4 40 Hz (±2%).
9) Guaranteed by design and character ization. Not s ubject to pr oduction te sting.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) For guard time calculation purposes.
12) Operation of micr oprocessor interfa ce requires that tCL + tCH ≥ 1000 ns
Figure 15 - Digital Signal Input Rise/Fall Times
8 Data hold time (read) tDHR 22 ns Figures 16 - 17
9DS/RD
to valid data delay (read) tDDR 100 ns Figures 16 - 17
10 Data setup time (wri te) tDSW 45 ns Figures 16, 18
11 Data hold time (write) tDHW 10 ns Figures 16, 18
12 Chip select setup time tCSS 45 ns Figures 16 - 18
13 Chip select hold time tCSH 40 ns Figures 16 - 18
14 DS/RD set up time prior to CS
assertion tRDS,tDSS 20 ns Figures 16, 17
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Conditions
tR
All Digital Inputs
tFVHM
VLM
*VHM = 0.7VDD, VLM = 0.3VDD
MT8885 Data Sheet
23
Zarlink Semiconductor Inc.
Figure 16 - Motorola BUS Timing Diagram
DS (E)
R/W
Read
AD3-AD0
(RS0, D0-D3)
Write
AD3-AD0
(RS0-D0-D3)
Addr *
non-mux
AS *
CS = AS.Addr
* microprocessor pins
tRWS
tRWH
tAS tDDR tDHR
Data
Data
tAH
tDSW tDHW
tCSH
tCSS
High Byte of Addr
Addr
Addr
tDSS
tCL tCH
MT8885 Data Sheet
24
Zarlink Semiconductor Inc.
Figure 17 - Intel Read Timing Diagram
Figure 18 - Intel Write Timing Diagram
ALE*
RD
P0*
(RS0,
D0-D3)
P2 *
(Addr)
CS = ALE.Addr
* microprocessor pins
tCSS
tAS tAH tDDR tDHR
Data
A8-A15 Address
tCSH
A0-A7
tRDS
WR
tCH tCL
ALE*
WR
P0*
(RS0,
D0-D3)
P2 *
(Addr)
* microprocessor pins
tCSS
tAS tAH tDSW tDHW
Data
A8-A15 Address
tCSH
A0-A7
RD**
** RD must be high on the falling edge of CS for Intel Bus Timing
tCH
tCL
CS = ALE.Addr
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