ee FAIRCHILD rg SEMICONDUCTOR m 100355 March 1998 Low Power Quad Multiplexer/Latch General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both En- able (En) inputs are LOW, the data that appears at an output is controlled by the Select (S,) inputs, as shown in the Oper- ating Mode table. In addition to routing data from either Dy or D,, the Select inputs can force the outputs LOW for the case where the latch is transparent (both Enables are LOW) and can steer a HIGH signal from either Dor D, to an output. The Select inputs can be tied together for applications re- quiring only that data be steered from either D,or D,. A positive-going signal on either Enable input latches the out- puts. A HIGH signal on the Master Reset (MR) input over- rides all the other inputs and forces the Q outputs LOW. All inputs have 50 kQ pulldown resistors. Features Greater than 40% power reduction of the 100155 2000V ESD protection Pin/function compatible with 100155 Voltage compensated operating range = -4.2V to -5.7V Available to MIL-STD-883 Available to industrial grade temperature range Ordering Code: Logic Symbol Pin Names Description eI IE E,, E> Enable Inputs (Active LOW) 1 2 _ Sp, $1 Select Inputs MR Master Reset E Doa Dia Don Dip DocD1c DogDia ds, we . DnaPna Data Inputs Hs Q,-Qa Data Outputs MR @% @ @ @ = = yl | 7 7 l 7 Q,-Qy Complementary Data Outputs DS010147-1 Connection Diagrams 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak Dowt -Y 24ep, Dib Pod Pra Vees Don Ga Oy Ey Ey MR Vee Sy 5g : oe (1) fo (3) (6) 2 8) biitil Qy-42 23I-Dy, Oh al heb 24 23 22 21 20 19 ay-43 22D, Dog 41 1BEDy, a44 21 Ey Die-42 17 Do, Q-45 20, Dog 5 16D, Veo 6 19 -MR Dig-4 15 = Dog Voca 7 18F-Ver Qs 14-0, a-48 17Es, a6 13a, aq 16-5, 7-8 9 10 11 12 a4 i (ec TCC *CCAMD b Qt 14F-Do, E8888 E D$010147-3 Poa} 12 3 Pte (19] Zo) (2i] 2) | 2a) BI 08010147-2 Poe Pre Pog VeEsP1q 4 Oy DS010147-4 1998 Fairchild Semiconductor Corporation DS010147 www fairchildsemi.com yoye7/4axa/dijjni PENH 4aM0d MO] GSEOOLMR E> Logic Diagram Ei Dig Lal E cD cD : rT Qa Operating Mode Table Controls Outputs mi mi N wl Q, Latched (Note 1) Latched (Note 1) Dox Dox + Dix ri}-7- 7 KX -|lrocowx xcrlxrrx =| L L xr r]/r-rxK x L Dix H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Truth Table Note 1: Stores data present before E went HIGH Inputs Outputs = x ml 2 mi Nn S, wl oO 3 x 9 x Tor rytr ere te rere yr rer cleo ei x DGr|rerererlirece x xmiM TrlO- rele or xz DT]D irer}ljr tt x <x <* clo r trli-r ct x x x olx tx x|x oo xP <x < Clo ek ek Clo kK eK x r]-rxrrtlor rip L Latched (Note 1) Latched (Note 1) 2lo a Qa DS010147-6 www fairchildsemi.comAbsolute Maximum Ratings (note 2) Above which the useful life may be impaired. Storage Temperature (Tera) -65C to +150C Maximum Junction Temperature (Tj) Ceramic H175C Plastic +150C Vee Pin Potential to Ground Pin -7.0V to +0.5V Input Voltage (DC) Vee to +0.5V Output Current (DC Output HIGH) -50 mA ESD (Note 3) 22000V Commercial Version DC Electrical Characteristics Recommended Operating Conditions Case Temperature (Tg) Commercial Industrial Military Supply Voltage (Vee) Note 2: Absolute maximum ratings are those values beyond which the de- vice may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Vee = 4.2V to -5.7V, Voo = Voca = GND, To = 0C to +85C (Note 4) -55C to +125C OC to +85C -40C to +85C -5.7V to -4.2V Symbol Parameter Min Typ Max Units Conditions Vou Output HIGH Voltage -1025 955 -870 mV Vin = Vin (max) Loading with VoL Output LOW Voltage -1830 -1705 -1620 mV or Vit (min) 50Q to -2.0V Vouc Output HIGH Voltage -1035 mV Vin = Vin (min Loading with Vote Output LOW Voltage -1610 mV or Vit (Max) 50Q to -2.0V Vin Input HIGH Voltage -1165 -870 mV Guaranteed HIGH Signal for ALL Inputs Vit Input LOW Voltage -1830 -1475 mV Guaranteed LOW Signal for ALL Inputs lit Input LOW Current 0.50 HA Vin = Vic amin) liq Input HIGH Current So, Sy 220 E,, Ep 350 HA Vin = Vin (max) DnaDna 340 MR 430 lee Power Supply Current -87 -40 mA Inputs Open Note 4: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. Commercial Version DIP AC Electrical Characteristics Vee = -4.2V to -5.7V, Voc = Veca = GND Symbol Parameter Te = 0C To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay TPHL Dna-Dna to Output 0.60 1.90 0.60 1.90 0.70 2.00 ns (Transparent Mode) TeLH Propagation Delay Figures 1, 2 TPHL So, S; to Output 1.00 2.60 1.00 2.60 1.20 2.70 ns (Transparent Mode) teLy Propagation Delay 0.80 2.00 0.80 2.00 0.80 2.10 ns TPH E,, EB to Output teLy Propagation Delay 0.80 2.30 0.80 2.30 0.80 2.30 ns Figures 1, 3 tpHL MR to Output tty Transition Time 0.60 1.40 0.60 1.40 0.60 1.40 ns Figures 1, 2 tra 20% to 80%, 80% to 20% www fairchildsemi.comCommercial Version DIP AC Electrical Characteristics (continued) Vee = -4.2V to -5.7V, Veg = Voca = GND Symbol Parameter To = OC To = +25C To = +85C Units Conditions Min Max Min Max Min Max ts Setup Time Dna-Pna 0.90 0.90 0.90 ns Figure 4 So, S; 1.70 1.70 1.70 MR (Release Time) 1.50 1.50 1.50 Figure 3 ty Hold Time Dna-Pna 0.40 0.40 0.40 ns Figure 4 So, S; 0.00 0.00 0.00 tow (L) Pulse Width LOW E,, Ep 2.00 2.00 2.00 ns Figure 2 tow (H) Pulse Width HIGH MR 2.00 2.00 2.00 ns Figure 3 Commercial Version PCC and Cerpak AC Electrical Characteristics Vee = -4.2V to -5.7V, Veo = Veca = GND Symbol Parameter To = OC To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay teu Dna-Dng to Output 0.60 1.70 | 0.60 1.70 0.70 1.80 ns (Transparent Mode) teLy Propagation Delay Figures 1, 2 teu Sp, S, to Output 1.00 240] 1.00 2.40 1.20 2.50 ns (Transparent Mode) teLy Propagation Delay 0.80 1.80 0.80 1.80 0.80 1.90 ns teat E,, E, to Output teLy Propagation Delay 0.80 2.10 0.80 2.10 0.80 2.10 ns Figures 1, 3 TPH MR to Output tty Transition Time 0.60 1.30 0.60 1.30 0.60 1.30 ns Figures 1, 2 tra 20% to 80%, 80% to 20% ts Setup Time Dna-Pna 0.80 0.80 0.80 ns Figure 4 So. 8 1.60 1.60 1.60 MR (Release Time) 1.40 1.40 1.40 Figure 3 ty Hold Time Dna-Pna 0.30 0.30 0.30 ns Figure 4 So. 8 -0.10 -0.10 -0.10 tow (L) Pulse Width LOW E,, Ep 2.00 2.00 2.00 ns Figure 2 tow (H) Pulse Width HIGH MR 2.00 2.00 2.00 ns Figure 3 tosHL Maximum Skew Common Edge PCC only Output-to-Output Variation 330 330 330 ps (Note 5) Data to Output Path tosLH Maximum Skew Common Edge PCC only Output-to-Output Variation 370 370 370 ps (Note 5) Data to Output Path tost Maximum Skew Opposite Edge PCC only Output-to-Output Variation 370 370 370 ps (Note 5) Data to Output Path www fairchildsemi.com 4Commercial Version PCC and Cerpak AC Electrical Characteristics (continued) Vee = -4.2V to -5.7V, Voc = Veca = GND Symbol Parameter Te = 0C To = +25C To = +85C Units Conditions Min Max Min Max Min Max tps Maximum Skew PCC only Pin (Signal) Transition Variation 270 270 270 ps (Note 5) Data to Output Path Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tggy), or LOW to HIGH (tog_y), or in opposite directions both HL and LH (tog7). Parameters tog7 and tps guaranteed by design. Industrial Version PCC DC Electrical Characteristics Vee = 4.2V to -5.7V, Veo = Voca = GND, Te = 40C to +85C (Note 6) Symbol Parameter To = -40C Te = OC to +85C Units Conditions Min Max Min Max Vou Output HIGH Voltage -1085 -870 -1025 -870 mV Vin = Vin (Max Loading with Voi Output LOW Voltage -1830 -1575 -1830 -1620 mV or Vit (min) 50Q to -2.0V Voue Output HIGH Voltage -1095 -1035 mV Vin = Vid min) Loading with Vote Output LOW Voltage -1565 -1610 mV or Vit (max) 50Q to -2.0V Vie Input HIGH Voltage -1170 -870 -1165 -870 mV Guaranteed HIGH Signal for ALL Inputs Vit Input LOW Voltage -1830 -1480 1830 1475 mV Guaranteed LOW Signal for ALL Inputs lit Input LOW Current 0.50 0.50 HA Vin = Vic cminy lie Input HIGH Current So, $1 300 220 E,, E> 350 350 HA | Vin = Vin (max DnaDna 340 340 MR 430 430 lee Power Supply Current -87 -40 -87 -40 mA Inputs Open Note 6: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. Industrial Version PCC AC Electrical Characteristics Vee = 4.2V to -5.7V, Voo = Veca = GND Symbol Parameter Te = -40C To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay Figures 1, 2 TPHL Dna-Pna to Output 0.60 1.70 0.60 1.70 0.70 1.80 ns (Transparent Mode) teLy Propagation Delay TPHL Sp, S, to Output 1.00 2.40 1.00 2.40 1.20 2.50 ns (Transparent Mode) teLy Propagation Delay 0.80 1.80 0.80 1.80 0.80 1.90 ns tout E,, E, to Output teLy Propagation Delay 0.80 2.10 0.80 2.10 0.80 2.10 ns Figures 1, 3 teu MR to Output www fairchildsemi.comIndustrial Version PCC AC Electrical Characteristics (continued) Ver = -4.2V to -8.7V, Vog = Voc, = GND Symbol Parameter Te = -40C To = +25C To = +85C Units Conditions Min Max Min Max Min Max truuttue | Transition Time 0.40 1.90 0.60 1.30 0.60 1.30 ns Figures 1, 2 20% to 80%, 80% to 20% ts Setup Time Dna-Pna 0.90 0.80 0.80 ns Figure 4 So, Si 2.40 1.60 1.60 MR (Release Time) 1.50 1.40 1.40 Figure 3 ty Hold Time Dna-Pna 0.40 0.30 0.30 ns Figure 4 So, 8 0.00 -0.10 -0.10 tow (L) Pulse Width LOW E,, E> 2.00 2.00 2.00 ns Figure 2 tow (H) Pulse Width HIGH MR 2.00 2.00 2.00 ns Figure 3 Military Version DC Electrical Characteristics Vee = -4.2V to -5.7V, Voc = Veca = GND, Te = -55C to +125C Symbol Parameter Min Max | Units Te Conditions Notes Vou | Output HIGH Voltage |-1025 | -870 mV OC to +125C -1085 | -870 mV -55C Vin = Vin (Max) Loading with (Notes 7, 8, Vo Output LOW Voltage |-1830 |-1620 | mV 0C to +125C or Vit (min) 50Q to -2.0V 9) -1830 | -1555 mV -55C Vouc | Output HIGH Voltage | -1035 mV 0C to +125C -1085 mV -55C Vin = Vin (min Loading with (Notes 7, 8, Vote | Output LOW Voltage -1610] mV 0C to +125C or Vit (Max) 50Q to -2.0V 9) -1555 mV -55C Vin Input HIGH Voltage -1165 | -870 mV 55C to Guaranteed HIGH Signal (Notes 7, 8, +125C for ALL Inputs 9, 10) Vit Input LOW Voltage -1830 |-1475 | mV -58C to Guaranteed LOW Signal (Notes 7, 8, +125C for ALL Inputs 9, 10) liv Input LOW Current 0.50 HA 55C to Vee = -4.2V (Notes 7, 8, +125C Vin = Vit (min) 9) liq Input HIGH Current So. Sy 220 E,, E> 350 yA OC to +125C Dna-Dna 340 Vee = -5.7V MR 430 Vin = Vin (max) (Notes 7, 8, So, Si 320 9) E,, Ep 500 uA -55C Dna-Dna 490 MR 630 lee Power Supply Current | -95 -32 mA | -55C to +125C | Inputs Open (Notes 7, 8, 9) condition at cold temperatures. Note 8: Screen tested 100% on each device at -55C, +25C, and +125C Temp., Subgroups 1, 2, 3, 7, and 8. Note 9: Sample tested (Method 5005, Table 7) on each Mfg. lot at +25, +125C, and -55C Temp., Subgroups 1, 2, 3, 7, and 8. Note 10: Guaranteed by applying specified input condition and testing Vou/VoL. Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55'C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case www fairchildsemi.comMilitary Version AC Electrical Characteristics Vee = -4.2V to -5.7V, Veo = Veca = GND Symbol Parameter To = -55C To = +25C Te = +125C | Units | Conditions Notes Min Max Min Max Min Max teLy Propagation Delay teu Dna-Dng to Output 040 2.30] 050 220] 050 260] ns (Transparent Mode) teLy Propagation Delay Figures 1, 2 teu So, $1 to Output 0.60 3.00 | 0.80 270] 080 3.20] ns (Notes 11, 12, (Transparent Mode) 13) teLH Propagation Delay 050 260 | 060 2.30 | 0.70 2.70 ns teu E,, Es to Output teLy Propagation Delay 0.60 2.80 0.70 2.60 0.70 2.90 ns Figures 1,3 | (Notes 11, 12, TeHL MR to Output 13) tty Transition Time 0.40 1.90 0.40 1.90 0.40 1.90 ns Figures 1, 2 (Note 14) tru 20% to 80%, 80% to 20% ts Setup Time Dna-Pna 0.90 0.90 0.90 ns Figure 4 (Note 14) So, $1 2.40 2.40 2.40 MR (Release Time) 1.50 1.50 1.50 Figure 3 ty Hold Time Dna-Pna 0.40 0.40 0.40 ns Figure 4 (Note 14) So, $1 0.00 0.00 0.00 tow (L)_ | Pulse Width LOW E,, E, 2.00 2.00 2.00 ns Figure 2 (Note 14) tow (H) | Pulse Width HIGH MR 2.00 2.00 2.00 ns Figure 3 (Note 14) Note 11: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immedi- ately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 12: Screen tested 100% on each device at +25C, Temperature only, Subgroup AQ. Note 13: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25, Subgroup AQ, and at +125C, and -55C Temp., Subgroups A10 & A11. Note 14: Not tested at +25C, +125C and -55C Temperature (design characterization data). www fairchildsemi.comTest Circuit u ry SCOPE wT CHAN A 24 23 22 21 20 19 L 1 18- = Rt 2 17];- - 43 16 ,[ I, 45 rv PULSE 500 50a tus GENERATOR 5 14 T 50 O = 6 13 = 7 8 9 10 11 12 | L2 on ry SCOPE 50 0 500 i CHAN B Wy L AW = Rr T" uF LL Vec BS010147-6 Notes: Voc. Veca = +2V, Veg = -2.5V L1 and L2 = equal length 50Q impedance lines Ry = 50Q terminator internal to scope Decoupling 0.1 pF from GND to Voc and Vee All unused outputs are loaded with 500 to GND C, = Fixture and stray capacitance < 3 pF Pin numbers shown are for flatpak; for DIP see logic symbol FIGURE 1. AC Test Circuit (Using Quad Cerpak) Switching Waveforms +1.05 V preeccoc rcs \ Vee em eee ee eee Nee a a a ee = = = = 0.31 tow +1.05 V ENABLE TRANSPARENT LATCHED TRANSPARENT +0.31V {PHL 1PLH OUTPUT 20% + < Se ee eee ee ee true, trLH DS010 147-7 FIGURE 2. Enable Timing www fairchildsemi.com 8Switching Waveforms (continued) RESET TIMING DATA ENABLE TRANSPARENT ts (RELEASE TIME) RESET/SET LATCHED TRANSPARENT OUTPUT FIGURE 3. Reset Timing +1.05V So, $1 50% +0.31V ts [~attr +1.05 V DATA 50% +0.31V p-t@_| th ts ~<__ + 1.05 V Ey, Ee 50% +0.31V Notes: ts is the minimum time before the transition of the enable that information must be present at the data input. th is the minimum time after the transition of the enable that information must remain unchanged at the data input. FIGURE 4. Data Setup and Hold Times Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are de- fined as follows: 100355 D C QB Device Type (Basic) Package Code D = Ceramic DIP Package F = Quad Cerpak P = Plastic DIP Q = Plastic Leaded Chip Carrier (PCC) DS0160147-8 DS010147-9 Special Variation QB = Military grade device with environmental and burn-in processing Temperature Range C = Commercial (0C to + 85C) | = Industrial ( 40C to + 85C) (PCC Only) M = Military ( 55C to + 125C) DS010147-14 www fairchildsemi.comPhysical DimensiONS inches (millimeters) unless otherwise noted 4.215 (30.86) ~ 0.025 MAX 0.030 0.055 (0.64) 24 13 (0.76 1.40) RAD Be RAD TYP 0,390 (9.91) MAX > yt ] para aponae en el >| A ata) 0.005 GLASS 0.050 4.060 BY. 0.4000.430 0.180 (0.13) sear \ (1271.52) YP] oan (10.16 10.92) (4.57) MIN TYP {0.38 1.40) MAX ' N | | ) a2 |f | ry (5.72) + MAX TYP 86--94 \ A t 90100 0.008 0.012 TP t TYP ~*~ 0.20 0.30) _ | 0.125 Tye 0.055 0.0900.110 0.0150,021 (3.18) 0.435 -0.535 (7.40) (2.29 2.79) (0.38 0.53) MIN (11.0513.59) MAX TYP TYP TYP TYP BOTH ENDS J24E (REV J) 24-Lead Ceramic Dual-In-Line Package (D) Package Number J24E 1.194-1,214 . [30.33-30.84] 0.202 24 [5.13] 13 (ee ee ee ee eee g 0035-0045 { [0.88-1.14] Db 0.337-0.347 [8.56-8.81] u CICLICI OCI CUCU u 1 12 PIN NO. 1 IDENT 0.125 [3.18] 0.125-0.135 5 0.060 0.039 - 3.18-3.43 0.390-0.410 [ 1 [1.52] YP] Pe To.99] 7] 0.065 [9.91-10.41] [1.65] 44u + 0.145-0.200 4 90-100 [3.68-5.08] B6-94 } 0.380 9.020 0.125-0.140 , 4 L_~ - MIN MIN L_ 9.65 [0.51] [3.18-3.56] 'Y | | IM 0.047-0.057 040 9.050 yp >| i 14.19-1.45] [YP 0.428 015 [1.27] [10.87 *1-02) 0.015-0.021 0.090-0.110 0.009-0.015 ! 29.38] [o.38-0.53] "Y [2.29-2.79] TYP [0.23-0.38] N24E (REV A) 24-Lead Plastic Dual-In-Line Package (P) Package Number N24E www fairchildsemi.com 10Physical DimMeNnSiONS inches (millimeters) unless otherwise noted (Continued) PIN NO. 0.360 0.370 MIN 0.360 > |< 9.007 2s? TYP 0.250 TYP o.oag TYP (MOLDED BODY) fs] m= Oo 0 a oO oO a 0.075 MAX |og 9.050 o.o1g YP 8 PLES > 0.035 0.050 0.005 >| t 0.085 MAX TYP 0.400 MAX TY P GLASS w248 (REV D} 24-Lead Ceramic Flatpak (F) Package Number W24C +0.006 0.450 10-008 [11.43] 72:15 PIN #1 IDENT ase x note [1.14] _ 0,01740.004 yp 4 i 26 0,02920.003 rp [0.4340.10] [0.740.08] . 5 |] 25 + qg a q H 0.4100.020 q a [10.4140.51] q a q a ni] [l19 HAAR AAA | 18 12 SEATING PLANE 1 0.050 qyp | a a [1.27] Je 9-920 win Typ 0.300 typ [0.51] [7.62] |_9.10540.015 age x 0-045 [2.6740,38] [1.14] 0.165-0.180 yyp [4.19-4.57] QQ} 0.004 [0.10] 0.49040.005 rp [12.450.13] 28A (REV K) 28-Lead Plastic Chip Carrier (Q) Package Number V28A aml www fairchildsemi.com100355 Low Power Quad Multiplexer/Latch LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- 2. tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. to the user. Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd. Americas Fax: +49 (0) 1 80-530 85 86 13th Floor, Straight Block, Tel: 81-3-5620-6175 Customer Response Center Email: europe.support@nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-3-5620-6179 Tel: 1-888-522-5372 Deutsch Tel: +49 (0) 8 141-35-0 Tsimshatsui, Kowloon English Tel: +44 (0) 1 793-85-68-56 Hong Kong Italy Tel: +39 (0) 2 57 5631 www fairchildsemi.com Tel: +852 2737-7200 Fax: +852 2314-0061 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.