LTC4007-1
1
40071fa
For more information www.linear.com/LTC4007-1
Typical applicaTion
DescripTion
4A, High Efficiency,
Li-Ion Battery Charger
The LT C
®
4007-1 is a constant-current/constant-voltage
charger controller for 3- or 4-cell lithium-ion batteries.
The PWM controller uses a synchronous, quasi-constant
frequency, constant off-time architecture that will not
generate audible noise even when using ceramic capaci-
tors. Charging current is programmable to ±4% accuracy
using a programming resistor
. Charging current can also be
monitored as a voltage across the programming resistor.
The output float voltage is pin programmed for cell count
(3 cells or 4 cells) and chemistry (4.2V/4.1V). A timer, pro-
grammed by an external resistor, sets the total charge time.
The LTC4007-1 includes a thermistor input, which
suspends charging if an unsafe temperature condition
is detected. If the cell voltage is less than 3.25V, a low-
battery indicator asserts and can be used to program a
trickle charge current to safely charge depleted batteries.
The FAULT pin is also asserted and charging terminates
if the low-battery condition persists for more than 1/4 of
the total charge time.
12.6V, 4A Li-Ion Battery Charger
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
NoRSENSE is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Protected by U.S. Patents including 5723970.
FeaTures
applicaTions
n Charger Controller for 3- or 4-Cell
Lithium-Ion Batteries
n High Conversion Efficiency: Up to 96%
n Output Currents Exceeding 4A
n ±0.8% Charging Voltage Accuracy
n Built-In Charge Termination for Li-Ion Batteries
n AC Adapter Current Limiting Maximizes Charge Rate*
n Thermistor Input for Temperature Qualified Charging
n Wide Input Voltage Range: 6V to 28V
n 0.5V Dropout Voltage; Maximum Duty Cycle: 98%
n Programmable Charge Current: ±4% Accuracy
n Indicator Outputs for Charging, C/10 Current
Detection, AC Adapter Present, Low Battery, Input
Current Limiting and Faults
n Charging Current Monitor Output
n Available in a 24-Pin 4mm × 5mm QFN Package
n Notebook Computers
n Portable Instruments
n Battery-Backup Systems
n Li-Ion Chargers
3C4C
CHEM
LOBAT
ICL
ACP
SHDN
FAULT
CHG
FLAG
NTC
RT
LOBAT
ICL
ACP
SHDN
FAULT
CHG
FLAG
DCIN
INFET
CLP
CLN
TGATE
BGATE
PGND
CSP
BAT
PROG
ITH
GND
LTC4007-1
32.4k
309k
0.47µF
THERMISTOR
10k
NTC TIMING RESISTOR
(~2 HOURS)
100k100k100k
VLOGIC
DCIN
0V TO 28V 0.1µF
INPUT SWITCH
15nF
Q1
Q2
20µF
10µH
4.99k
3.01k
3.01k
0.025Ω
0.025Ω
20µF
Li-Ion
BATTERY
CHARGING
CURRENT
MONITOR
Q1: Si4431BDY
Q2: FDC645N
SYSTEM
LOAD
0.12µF
6.04k
26.7k
0.0047µF
40071 TA01
PART
AUTO
RESTART
LOW BATTERY
THRESHOLD (Per Cell)
(4.2V/4.1V)
LTC4007-1 NO 3.25V/3.173V
LTC4007 YES 2.5V/2.44V
LTC4007-1
2
40071fa
For more information www.linear.com/LTC4007-1
Voltage from DCIN, CLP, CLN to GND ......... +32V/–0.3V
PGND with Respect to GND .................................. ±0.3V
CSP, BAT to GND ......................................... +28V/–0.3V
CHEM, 3C4C, RT to GND ................................ +7V/–0.3V
NTC .............................................................. +10V/–0.3V
ACP, SHDN, CHG, FLAG,
FA U LT, LOBAT, ICL ........................................ +32V/–0.3V
CLP to CLN ............................................................±0.5V
Operating Ambient Temperature Range
(Note 4) ............................................. –40°C to 85°C
Operating Junction Temperature ........... –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
(Note 1)
pin conFiguraTionabsoluTe MaxiMuM raTings
8 9
TOP VIEW
UFD PACKAGE
24-LEAD (4mm × 5mm) PLASTIC QFN
10 11 12
24
25
23 22 21 20
6
5
4
3
2
1
ACP
RT
FAULT
GND
3C4C
LOBAT
NTC
NC
PGND
TGATE
CLN
CLP
FLAG
CHEM
CHG
DCIN
SHDN
INFET
BGATE
ITH
PROG
ICL
CSP
BAT
7
14
15
16
17
18
19
13
TJMAX = 125°C, θJA = 90°C/W
EXPOSED PAD (PIN 25), GND AND PGND SHOULD BE CONNECTED
TOGETHER WITH A LOW OHMIC CONNECTION
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VB AT = 12V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DCIN Operating Range 6 28 V
IQOperating Current Sum of Current from CLP, CLN, DCIN 3 5 mA
VTOL Charge Voltage Accuracy Nominal Values: 12.3V, 12.6V, 16.4V,
16.8V (Note 2)
l
–0.8
–1.0
0.8
1.0
%
%
ITOL Charge Current Accuracy (Note 3) VCSP – VBAT Target = 100mV
VBAT < 6V, VCSP – VBAT Target = 10mV
6V ≤ VBAT ≤ VLOBAT
, VCSP – VBAT
Target = 10mV
l
–4
–5
±60
±35
4
5
%
%
%
%
TSAMPLE Measured Sample Time RRT = 1190k l42 60 ms
Shutdown
Battery Leakage Current DCIN = 0V
SHDN = 3V
l
l
–10
20 35
10
µA
µA
UVLO Undervoltage Lockout Threshold DCIN Rising, VBAT = 0 l4.2 4.7 5.5 V
Shutdown Threshold at SHDN l1 1.6 2.5 V
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4007EUFD-1#PBF LTC4007EUFD-1#TRPBF 40071 24-Lead Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC4007-1#orderinfo
LTC4007-1
3
40071fa
For more information www.linear.com/LTC4007-1
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VB AT = 12V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SHDN Pin Current –10 µA
Operating Current in Shutdown VSHDN = 0V, Sum of Current from CLP,
CLN, DCIN
2 3 mA
Current Sense Amplifier, CA1
Input Bias Current Into BAT Pin 11.67 µA
CMSL CA1/I1 Input Common Mode Low l0 V
CMSH CA1/I1 Input Common Mode High lVCLN – 0.2 V
Current Comparators ICMP and IREV
ITMAX Maximum Current Sense Threshold (VCSP – VBAT) VITH = 2.5V l140 165 200 mV
ITREV Reverse Current Threshold (VCSP – VBAT) –30 mV
Current Sense Amplifier, CA2
Transconductance 1 mmho
Source Current Measured at ITH, VITH = 1.4V –40 µA
Sink Current Measured at ITH, VITH = 1.4V 40 µA
Current Limit Amplifier
Transconductance 1.4 mmho
VCLP Current Limit Threshold l93 100 107 mV
ICLP CLP Input Bias Current 100 nA
Voltage Error Amplifier, EA
Transconductance 1 mmho
Sink Current Measured at ITH, VITH = 1.4V 36 µA
OVSD Overvoltage Shutdown Threshold as a Percent of
Programmed Charger Voltage
l102 107 110 %
Input P-Channel FET Driver (INFET)
DCIN Detection Threshold (VDCIN – VCLN) DCIN Voltage Ramping Up
from VCLN – 0.1V
l0 0.17 0.25 V
Forward Regulation Voltage (VDCIN – VCLN)l25 50 mV
Reverse Voltage Turn-Off Voltage (VDCIN – VCLN) DCIN Voltage Ramping Down l–60 –25 mV
INFET “On” Clamping Voltage (VDCIN – VINFET) IINFET = 1µA l5 5.8 6.5 V
INFET “Off” Clamping Voltage (VDCIN – VINFET) IINFET = –25µA 0.25 V
Thermistor
NTCVR Reference Voltage During Sample Time 4.5 V
High Threshold VNTC Rising lNTCVR
• 0.48
NTCVR
• 0.5
NTCVR
• 0.52
V
Low Threshold VNTC Falling lNTCVR
• 0.115
NTCVR
• 0.125
NTCVR
• 0.135
V
Thermistor Disable Current VNTC ≤ 10V 10 µA
Indicator Outputs (ACP, CHG, FLAG, LOBAT, ICL, FAULT
C10TOL FLAG (C/10) Accuracy Voltage Falling at PROG l0.375 0.397 0.420 V
LBTOL LOBAT Threshold Accuracy 3C4C = 0V, CHEM = 0V
3C4C = 0V, CHEM = Open
3C4C = Open, CHEM = 0V
3C4C = Open, CHEM = Open
l
l
l
l
9.233
9.458
12.311
12.610
9.519
9.750
12.692
13.000
9.805
10.043
13.074
13.390
V
V
V
V
ICL Threshold Accuracy 83 93 1O5 mV
LTC4007-1
4
40071fa
For more information www.linear.com/LTC4007-1
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VB AT = 12V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOL Low Logic Level of ACP, CHG, FLAG, LOBAT,
ICL, FAULT
IOL = 100µA l0.5 V
VOH High Logic Level of CHG, LOBAT, ICL IOH = –1µA l2.7 V
IOFF Off State Leakage Current of ACP, FLAG, FAULT VOH = 3V –1 1 µA
IPO Pull-Up Current on CHG, LOBAT, ICL V = 0V –10 µA
Timer Defeat Threshold at CHG 1 V
Programming Inputs (CHEM and 3C4C)
VIH High Logic Level l3.3 V
VIL Low Logic Level l1 V
IPI Pull-Up Current V = 0V –14 µA
Oscillator
fOSC Regulator Switching Frequency 255 300 345 kHz
fMIN Regulator Switching Frequency in Drop Out Duty Cycle ≥ 98% 20 25 kHz
DCMAX Regulator Maximum Duty Cycle VCSP = VBAT 98 99 %
Gate Drivers (TGATE, BGATE)
VTGATE High (VCLN – VTGATE) ITGATE = –1mA 50 mV
VBGATE High CLOAD = 3000pF 4.5 5.6 10 V
VTGATE Low (VCLN – VTGATE) CLOAD = 3000pF 4.5 5.6 10 V
VBGATE Low IBGATE = 1mA 50 mV
TGTR
TGTF
TGATE Transition Time
TGATE Rise Time
TGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
50
50
110
100
ns
ns
BGTR
BGTF
BGATE Transition Time
BGATE Rise Time
BGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
40
40
90
80
ns
ns
VTGATE at Shutdown (VCLN – VTGATE) ITGATE = –1µA, DCIN = 0V, CLN = 12V 100 mV
VBGATE at Shutdown IBGATE = 1µA, DCIN = 0V, CLN = 12V 100 mV
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor or current
programming resistor.
Note 4: The LTC4007E-1 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
LTC4007-1
5
40071fa
For more information www.linear.com/LTC4007-1
Typical perForMance characTerisTics
PWM Frequency vs Duty Cycle
Disconnect/Reconnect Battery
(Load Dump) 1A Load Step (Battery Present)
1A Load Step
(Battery Not Present)
Battery Leakage Current vs
Battery Voltage
INFET Response Time to
Reverse Current Line Regulation VOUT vs IOUT
TEST PERFORMED ON DEMOBOARD
VIN = 15VDC
CHARGER = ON
ICHARGE = <10mA
Vs OF PFET (5V/DIV)
Id (REVERSE) OF
PFET (5A/DIV)
Vgs OF PFET (2V/DIV)
40071 G01
VCHARGE = 12.6V
PFET = 1/2 Si4925DY
Vgs = 0
Vs = 0V
Id = 0A
1.25µs/DIV
VDCIN (V)
13 15 17 21 25 2919 23 27 31
V
OUT
ERROR (%)
40071 G02
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
C3C4 = GND
C3C4 = OPEN
OUTPUT CURRENT (A)
0 0.5 1.0 2.0 3.0 4.01.5 2.5 3.5 4.5
OUTPUT VOLTAGE ERROR (%)
40071 G03
3C4C = GND
3C4C = OPEN
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
DUTY CYCLE (VOUT/VIN)
0 0.1 0.2 0.4 0.6 0.90.80.3 0.5 0.7 1.0
PWM FREQUENCY (kHz)
40071 G04
PROGRAMMED CURRENT = 10%
DCIN = 15V
DCIN = 20V
DCIN = 24V
350
300
250
200
150
100
50
0
40071 G05
LOAD CURRENT = 1A, 2A, 3A
DCIN = 20V
VFLOAT = 12.6V (3C4C = GND, CHEM = OPEN)
VFLOAT
1V/DIV
LOAD
STATE DISCONNECT
1A STEP
3A STEP
RECONNECT
3A STEP
1A STEP
DCIN = 20V
VFLOAT = 12.6V
OUTPUT VOLTAGE (500mV/DIV)
CHARGER CURRENT (1A/DIV)
40071 G06
DCIN = 20V
VFLOAT = 12.6V
OUTPUT VOLTAGE (5V/DIV)
CHARGER CURRENT (500mA/DIV)
40071 G07
BATTERY VOLTAGE (V)
0 5 10 15 20 25 30
BATTERY LEAKAGE CURRENT (µA)
40071 G08
40
35
30
25
20
15
10
5
0
VDCIN = 0V
LTC4007-1
6
40071fa
For more information www.linear.com/LTC4007-1
Typical perForMance characTerisTics
Efficiency at 19VDC VIN Efficiency at 12.6V with 15VDC VIN
CHARGE CURRENT (A)
1.000.50 1.50 2.00 2.50 3.00
EFFICIENCY (%)
40071 G10
16.8V
12.6V
100
95
90
85
80
75
CHARGE CURRENT (A)
1.000.50 1.50 2.00 2.50 3.00
EFFICIENCY (%)
40071 G11
100
95
90
85
80
75
pin FuncTions
ACP (Pin 1): Open-Drain output to indicate if the AC adapter
voltage is adequate for charging. This pin is pulled low
by an internal N-channel MOSFET if DCIN is below BAT. A
pull-up resistor is required. The pin is capable of sinking
at least 100µA.
RT (Pin 2): Timer Resistor. The timer period is set by placing
a resistor, RRT , to GND. This resistor is always required.
The timer period is tTIMER = (1hour • RRT/154K).
If this resistor is not present, the charger will not start.
FAULT (Pin 3): Active low open-drain output that indicates
charger operation has stopped due to a low-battery condi-
tioning error, or that charger operation is suspended due to
the thermistor exceeding allowed values. A pull-up resistor
is required if this function is used. The pin is capable of
sinking at least 100µA.
GND (Pin 4): Ground for Low Power Circuitry.
3C4C (Pin 5): Select 3-cell or 4-cell float voltage by con-
necting this pin to GND or open, respectively. Internal
14µA pull-up to 5.3V. This pin can also be driven with
open-collector/drain logic levels. High: 4 cell. Low: 3 cell.
LOBAT (Pin 6): Low-Battery Indicator. Active low digital
output. Internal 10µA pull-up to 3.5V. If the battery volt-
age is below 3.25V/cell (or 3.173V/cell for 4.1V chemistry
batteries) LOBAT will be low. The pin is capable of sink-
ing at least 100µA. If VLOGIC is greater than 3.3V, add an
external pull-up.
NTC (Pin 7): A thermistor network is connected from NTC
to GND. This pin determines if the battery temperature is
safe for charging. The charger and timer are suspended
and the FAULT pin is driven low if the thermistor indicates
a temperature that is unsafe for charging. The thermistor
function may be disabled with a 300k to 500k resistor
from DCIN to NTC.
ITH (Pin 8): Control Signal of the Inner Loop of the Current
Mode PWM. Higher ITH voltage corresponds to higher
charging current in normal operation. A 6k resistor, in
series with a capacitor of at least 0.1µF to GND provides
loop compensation. Typical full-scale output current is
40µA. Nominal voltage range for this pin is 0V to 3V.
LTC4007-1
7
40071fa
For more information www.linear.com/LTC4007-1
pin FuncTions
PROG (Pin 9): Current Programming/Monitoring Input/
Output. An external resistor to GND programs the peak
charging current in conjunction with the current sensing
resistor. The voltage at this pin provides a linear indication of
charging current. Peak current is equivalent to 1.19V. Zero
current is approximately 0.3V. A capacitor from PROG to
ground is required to filter higher frequency components.
The maximum resistance to ground is 100k. Values higher
than 100k can cause the charger to shut down.
ICL (Pin 10): Input Current Limit Indicator. Active low digital
output. Internal 10µA pull-up to 3.5V. Pulled low if the
charger current is being reduced by the input current limit-
ing function. The pin is capable of sinking at least 100µA.
If VLOGIC is greater than 3.3V, add an external pull-up.
CSP (Pin 11): Current Amplifier CA1 Input. The CSP and
BAT pins measure the voltage across the sense resistor,
RSENSE, to provide the instantaneous current signals re-
quired for both peak and average current mode operation.
BAT (Pin 12): Battery Sense Input and the Negative Refer-
ence for the Current Sense Resistor. A precision internal
resistor divider sets the final float potential on this pin.
The resistor divider is disconnected during shutdown.
CHEM (Pin 13): Select 4.1V or 4.2V cell chemistry by con-
necting the pin to GND or open, respectively. Internal 14µA
pull-up to 5.3V. Can also be driven with open-collector/
drain logic levels.
FLAG (Pin 14): Active low open-drain output that indicates
when charging current has declined to 10% of maximum
programmed current. A pull-up resistor is required if this
function is used. The pin is capable of sinking at least 100µA.
CLP (Pin 15): Positive input to the supply current limiting
amplifier, CL1. The threshold is set at 100mV above the
voltage at the CLN pin. When used to limit supply current,
a filter is needed to filter out the switching noise. If no
current limit function is desired, connect this pin to CLN.
CLN (Pin 16): Negative Reference for the Input Current
Limit Amplifier, CL1. This pin also serves as the power
supply for the IC. A 10µF to 22µF bypass capacitor should
be connected as close as possible to this pin.
TGATE (Pin 17): Drives the top external P-channel MOSFET
of the battery charger buck converter.
PGND (Pin 18): High Current Ground Return for the
BGATE Driver.
NC (Pin 19): No Connect.
BGATE (Pin 20): Drives the bottom external N-channel
MOSFET of the battery charger buck converter.
INFET (Pin 21): Drives the Gate of the External Input PFET.
SHDN (Pin 22): Charger is shut down and timer is reset
when this pin is HIGH. Internal 10µA pull-up to 3.5V. This
pin can also be used to reset the charger by applying a
positive pulse that is a minimum of 0.1µs long.
DCIN (Pin 23): External DC Power Source Input. Bypass
this pin with at least 0.01µF. See Applications Information.
CHG (Pin 24): Charge Status Output. When the battery is
being charged, the CHG pin is pulled low by an internal
N-channel MOSFET. Internal 10µA pull-up to 3.5V. If VLOGIC
is greater than 3.3V, add an external pull-up. The timer
function can be defeated by forcing this pin below 1V (or
connecting it to GND).
Exposed Pad (Pin 25): The exposed pad, GND and PGND
should be connected together with a low ohmic connection.
LTC4007-1
8
40071fa
For more information www.linear.com/LTC4007-1
block DiagraM
–
+
–
+
5
4
13
9k
1.19V
11.67µA
TBAD
MUX
EA
gm = 1m
Ω
gm = 1m
Ω
gm = 1.4m
Ω
921mV
1.19V
3C4C
FLAG
GND
CHEM
6LOBAT
10
17
ICL
TGATE
BGATE
Q1
Q2
15
CLP
100mV
15nF
20µF
RCL
5k
16
CLN
20
PGND
L1
397mV
CHG
RT
NTC
0.47µF 10k
NTC
RRT
–
+
–
+
CL1
TIMER/CONTROLLER
THERMISTOR
OSCILLATOR
24
2
7
BAT 3.01k
RSENSE
CSP
ITH
8
32.4k
WATCHDOG
DETECT tOFF
CLN
DCIN
OV
OSCILLATOR
1.28V
PWM
LOGIC
S
R
Q
CHARGE
IREV
–
+
ICMP
+
–
÷5 BUFFERED ITH
18
PROG
40071 BD
RPROG
26.7k
0.0047µF
9
14
FAULT 3
SHDN 22
ACP 1
INFET
Q3
DCIN
0.1µF
VIN
21
23
–
+
CLN
5.8V
3.01k
20µF
6K
0.12µF
12
11
–
+
CA1
CA2
–
+
–
+
C/10
35mV
–
+
17mV
LTC4007-1
9
40071fa
For more information www.linear.com/LTC4007-1
TesT circuiT
operaTion
–
+
–
+
EA
LT1055
LTC4007-1
VREF
CHEM
3C4C
BAT
DIVIDER/
MUX
13
5
12
CSP
11 ITH
0.6V
40071 TC
8
Overview
The LTC4007-1 is a synchronous current mode PWM
step-down (buck) switcher battery charger controller. The
charge current is programmed by the combination of a
program resistor (RPROG) from the PROG pin to ground
and a sense resistor (RSENSE) between the CSP and BAT
pins. The final float voltage is programmed to one of four
values (12.3V, 12.6V, 16.4V, 16.8V) with ±1% maximum
accuracy using pins 3C4C and CHEM. Charging begins
when the potential at the DCIN pin rises above the volt-
age at BAT (and the UVLO voltage) and the SHDN pin
is low; the CHG pin is set low. At the beginning of the
charge cycle, if the cell voltage is below 3.25V (3.173V
if CHEM is low), the LOBAT pin will be low. The LOBAT
indicator can be used to reduce the charging current to
a low value, typically 10% of full scale. If the cell voltage
stays below 3.25V for 25% of the total charge time, the
charge sequence will be terminated immediately and the
FAULT pin will be set low.
An external thermistor network is sampled at regular
intervals. If the thermistor value exceeds design limits,
charging is suspended and the FAULT pin is set low. If the
thermistor value returns to an acceptable value, charging
resumes and the FAULT pin is set high. An external resistor
on the RT pin sets the total charge time. The timer can be
defeated by forcing the CHG pin to a low voltage.
As the battery approaches the final float voltage, the charge
current will begin to decrease. When the current drops
to 10% of the full-scale charge current, an internal C/10
comparator will indicate this condition by latching the
FLAG pin low. The charge timer is also reset to 1/4 of the
total charge time when FLAG goes low. If this condition
is caused by an input current limit condition, described
below, then the FLAG indicator will be inhibited. When a
time-out occurs, charging is terminated immediately and
the CHG pin is forced to a high impedance state. To restart
the charge cycle manually, simply remove the input volt-
age and reapply it, or set the SHDN pin high momentarily.
When the input voltage is not present, the charger goes
into a sleep mode, dropping battery current drain to 15µA.
This greatly reduces the current drain on the battery and
increases the standby time. The charger is inhibited any
time the SHDN pin is high.
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLN pin
and provides the logic indicator of AC present on the ACP
pin. It controls the gate of the input FET to keep a low
forward voltage drop when charging and also prevents
reverse current flow through the input FET.
If the input voltage is less than VCLN, it must go at least
170mV higher than VCLN to activate the charger. When
this occurs the ACP pin is released and pulled up with
an external load to indicate that the adapter is present.
LTC4007-1
10
40071fa
For more information www.linear.com/LTC4007-1
Table 1. Truth Table for LTC4007-1 Operation (Supplemental)
NUMBER
FROM
STATE
TO
STATE MODE DCIN
BATTERY
VOLTAGE
PRESENT
C/10
LATCH
NEXT
C/10
LATCH
MAX
BATTERY
CURRENT ACP
TIMER
STATE CHG
1 Any MSD Shut Down by Low
Adapter Voltage
<BAT 0 OFF LOW Reset HIGH
2 MSD SD Charger Shutdown >BAT 0 OFF HIGH Reset HIGH
3 SD,
CONDITION,
CHARGE
SD Shut Down by
Undervoltage Lockout
>BAT
and
<UVL
OFF HIGH Reset HIGH*
4 SD CONDITION Start Conditioning a
Depleted Battery
>BAT <3.25V/Cell 10%
Programmed
Current
HIGH LOW
5 CONDITION CONDITION Input Current Limited
Condition Charging
>BAT <3.25V/Cell <10%
Programmed
Current (Note 2)
HIGH Running LOW
6 CONDITION CONDITION Conditioning a
Depleted Battery
>BAT <3.25V/Cell 10%
Programmed
Current
HIGH Running LOW
7 CONDITION CONDITION Timer Defeated (Low
Battery Conditioning Still
Functional)
>BAT <3.25V/Cell 10%
Programmed
Current
HIGH Ignored Forced
LOW
8 CONDITION SD Charger Paused Due to
Thermistor Out of Range
>BAT <3.25V/Cell OFF HIGH Paused LOW
(Faulted)
9 CONDITION SD Timeout in
CONDITION Mode
>BAT <3.25V/Cell OFF HIGH >T/4 HIGH
(Faulted)
10 CONDITION SD Shut Down by
ACP/SHDN Pin
>BAT <3.25V/Cell 0 OFF Forced
LOW
Reset HIGH
11 CONDITION CHARGE Start Normal Charging >BAT >3.25V/Cell Programmed
Current
HIGH Running
12 CHARGE CHARGE Timer Defeated (Low
Battery Conditioning Still
Functional)
>BAT >3.25V/Cell Programmed
Current
HIGH Ignored Forced
LOW
13 CHARGE CHARGE Top-Off Charging >BAT >3.25V/Cell 0 Programmed
Current
HIGH Running LOW
14 CHARGE CHARGE C/10 Latch is SET
when Battery Current
Is Less than 10% of
Programmed Current
>BAT >3.25V/Cell 1 Programmed
Current
HIGH Reset 25µA
15 CHARGE CHARGE Top-Off Charging >BAT >3.25V/Cell 1 Programmed
Current
HIGH Running 25µA
16 CHARGE CHARGE Input Current
Limited Charging
>BAT >3.25V/Cell <Programmed
Current (Note 2)
HIGH
17 CHARGE SD Charger Paused Due to
Thermistor Out of Range
>BAT >3.25V/Cell OFF HIGH Paused LOW or
25µA
(Faulted)
18 CHARGE SD Shut Down by
ACP/SHDN Pin
>BAT >3.25V/Cell 0 OFF Forced
LOW
Reset HIGH
19 CHARGE SD Terminated by Low-
Battery Fault (Note 1)
>BAT <3.25V/Cell 0 OFF HIGH >T/4 then
Reset
HIGH
(Faulted)
20 CHARGE SD Terminates After T/4 >BAT VFLOAT 1 OFF HIGH >T/4 then
Reset
HIGH
21 CHARGE SD Terminates After T >BAT VFLOAT* 0 OFF HIGH >T then
Reset
HIGH
*Most probable condition
Note 1: If a depleted battery is inserted while the charger is in this state,
the charger must be reset to initiate charging.
Note 2: See section on “Adapter Limiting”.
Note 3: Blank fields indicate no change, not considered, or other states
impact value.
Note 4: Battery voltage thresholds do not include comparator hysterisis.
Thresholds specify the VLH value.
operaTion
LTC4007-1
11
40071fa
For more information www.linear.com/LTC4007-1
operaTion
LTC4007-1: State Diagram
40071 TBL01
MASTER
SHUTDOWN
SHUTDOWN
ANY
1
2
4
11
12, 13, 14, 15, 16
3, 17, 18,
19, 20, 21
3, 8,
9, 10
5, 6, 7 CONDITION
CHARGE
The gate of the input FET is driven to a voltage sufficient
to keep a low forward voltage drop from drain to source.
If the voltage between DCIN and CLN drops to less than
25mV, the input FET is turned off slowly. If the voltage
between DCIN and CLN is ever less than –25mV, then
the input FET is turned off in less than 10µs to prevent
significant reverse current from flowing in the input FET. In
this condition, the ACP pin is driven low and the charger
is disabled.
Battery Charger Controller
The LTC4007-1 charger controller uses a constant off-
time, current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when the
main current comparator ICMP resets the SR latch. While
the top MOSFET is off, the bottom MOSFET is turned on
until either the inductor current trips the current compara-
tor IREV or the beginning of the next cycle. The oscillator
uses the equation:
t
VV
Vf
OFF DCIN BAT
DCIN OSC
=
–
•
to set the bottom MOSFET on time. The result is a nearly
constant switching frequency over a wide input/output
voltage range. This activity is diagrammed in Figure 1.
The peak inductor current, at which ICMP resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative cur-
rent. Error amp CA2 compares this current against the
TGATE
OFF
ON
BGATE
INDUCTOR
CURRENT
tOFF
TRIP POINT SET BY ITH VOLTAGE
ON
OFF
40071 F01
Figure 1
LTC4007-1
12
40071fa
For more information www.linear.com/LTC4007-1
operaTion
desired current programmed by RPROG at the PROG pin
and adjusts ITH until:
V
R
VV Ak
k
REF
PROG
CSP BAT
=+μ Ω
Ω
–.•.
.
11 67 301
301
therefore,
IV
RAk
R
CHARGE MAX REF
PROG SENSE
() –. •.
=μ
⎛
⎝
⎜⎞
⎠
⎟Ω
11 67 301
The voltage at BAT is divided down by an internal resis-
tor divider and is used by error amp EA to decrease ITH
if the divider voltage is above the 1.19V reference. When
the charging current begins to decrease, the voltage at
PROG will decrease in direct proportion. The voltage at
PROG is then given by:
VI RAk
PROG CHARGE SENSE PROG
=+μΩ
•.•. •
11 67 301
VPROG is plotted in Figure 2.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter to a preset level (100mV/
RCL). At input current limit, CL1 will decrease the ITH volt-
age, thereby reducing charging current. The ICL indicator
output will go low when this condition is detected and the
FLAG indicator will be inhibited if it is not already LOW.
If the charging current decreases below 10% to 15%
of programmed current while engaged in input current
limiting, BGATE will be forced low to prevent the charger
from discharging the battery. Audible noise can occur in
this mode of operation.
An overvoltage comparator guards against voltage transient
overshoots (>7% of programmed value). In this case, both
MOSFETs are turned off until the overvoltage condition
is cleared. This feature is useful for batteries which “load
dump” themselves by opening their protection switch
to perform functions such as calibration or pulse mode
charging.
PWM Watchdog Timer
There is a watchdog timer that observes the activity on
the BGATE and TGATE pins. If TGATE stops switching for
more than 40µs, the watchdog activates and turns off the
top MOSFET for about 400ns. The watchdog engages to
prevent very low frequency operation in dropout—a po-
tential source of audible noise when using ceramic input
and output capacitors.
Charger Start-Up
When the charger is enabled, it will not begin switching
until the ITH voltage exceeds a threshold that assures initial
current will be positive. This threshold is 5% to 15% of the
maximum programmed current. After the charger begins
switching, the various loops will control the current at a
level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation, but is typically less than 100µs.
Thermistor Detection
The thermistor detection circuit is shown in Figure 3. It
requires an external resistor and capacitor in order to
function properly.
The thermistor detector performs a sample-and-hold
function. An internal clock, whose frequency is determined
ICHARGE (% OF MAXIMUM CURRENT)
0
0
V
PROG
(V)
0.2
0.4
0.6
0.8
20 40 60 80 100
40071 F02
1.0
1.2 1.19V
0.309V
Figure 2. VPROG vs ICHARGE
LTC4007-1
13
40071fa
For more information www.linear.com/LTC4007-1
operaTion
by the timing resistor connected to RT
, keeps switch S1
closed to sample the thermistor:
tSAMPLE = 127.5 • 20 • RRT • 17.5pF = 13.8ms,
for RRT = 309k
The external RC network is driven to approximately 4.5V
and settles to a final value across the thermistor of:
V
VR
RR
RTH FINAL TH
TH
()
.•
=+
45
9
This voltage is stored by C7. Then the switch is opened
for a short period of time to read the voltage across the
thermistor.
tHOLD = 10 • RRT • 17.5pF = 54µs,
for RRT = 309k
When the tHOLD interval ends the result of the thermistor
testing is stored in the D flip-flop (DFF). If the voltage at
NTC is within the limits provided by the resistor divider
feeding the comparators, then the NOR gate output will
be low and the DFF will set TBAD to zero and charging will
continue. If the voltage at NTC is outside of the resistor
divider limits, then the DFF will set TBAD to one, the charger
will be shut down, FAULT pin is set low and the timer will
be suspended until TBAD returns to zero (see Figure 4).
7
R9
32.4k
C7
0.47µF
RTH
10k
NTC
–
+
–
+
–
+
NTC
LTC4007-1
S1
60k
~4.5V
CLK
45k
15k
TBAD
40071 F03
D
C
Q
CLK
(NOT TO
SCALE)
VNTC
tSAMPLE
VOLTAGE ACROSS THERMISTOR
tHOLD
40071 F04
COMPARATOR HIGH LIMIT
COMPARATOR LOW LIMIT
Figure 3
Figure 4
LTC4007-1
14
40071fa
For more information www.linear.com/LTC4007-1
applicaTions inForMaTion
Battery Detection
It is generally not good practice to connect a battery while
the charger is running. The timer is in an unknown state
and the charger could provide a large surge current into
the battery for a brief time. The Figure 5 circuit keeps the
charger shut down and the timer reset while a battery is
not connected.
23 DCIN
LTC4007-1
ADAPTER
POWER
SWITCH CLOSED
WHEN BATTERY
CONNECTED
22 SHDN
40071 F05
Figure 5
Charger Current Programming
The basic formula for charging current is:
I
VkRV
R
CHARGE MAX REF PROG
SENSE
()
•. /–.
=Ω
3010035
VREF = 1.19V
This leaves two degrees of freedom: RSENSE and RPROG.
The 3.01k input resistors must not be altered since in-
ternal currents and voltages are trimmed for this value.
Pick RSENSE by setting the average voltage between CSP
and BAT to be close to 100mV during maximum charger
current. Then RPROG can be determined by solving the
above equation for RPROG.
R
Vk
RI V
PROG REF
SENSE CHARGE MAX
=Ω
+
•.
•.
()
301
0 035
Table 2. Recommended RSNS and RPROG Resistor Values
IMAX (A) RSENSE (Ω) 1% RSENSE (W) RPROG (kΩ) 1%
1.0 0.100 0.25 26.7
2.0 0.050 0.25 26.7
3.0 0.033 0.5 26.7
4.0 0.025 0.5 26.7
Charging current can be programmed by pulse width
modulating RPROG with a switch Q1 to RPROG at a frequency
higher than a few kHz (Figure 6). CPROG must be increased
to reduce the ripple caused by the RPROG switching. The
compensation capacitor at ITH will probably need to be
increased also to improve stability and prevent large
overshoot currents during start-up conditions. Charging
current will be proportional to the duty cycle of the switch
with full current at 100% duty cycle and zero current when
Q1 is off.
Maintaining C/10 Accuracy
The C/10 comparator threshold that drives the FLAG pin
has a fixed threshold of approximately VPROG = 400mV.
This threshold works well when RPROG is 26.7k, but will
not yield a 10% charging current indication if RPROG is
a different value. There are situations where a standard
value of RSENSE will not allow the desired value of charging
current when using the preferred RPROG value. In these
cases, where the full-scale voltage across RSENSE is within
±20mV of the 100mV full-scale target, the input resistors
connected to CSP and BAT can be adjusted to provide the
desired maximum programming current as well as the
correct FLAG trip point.
For example, the desired max charging current is 2.5A
but the best RSENSE value is 0.033Ω. In this case, the volt-
age across RSENSE at maximum charging current is only
82.5mV, normally RPROG would be 30.1k but the nominal
FLAG trip point is only 5% of maximum charging current.
If the input resistors are reduced by the same amount as
RZ
102k
CPROG
40071 F06
PROG
9
LTC4007-1
Q1
2N7002
RPROG
0V
5V
Figure 6. PWM Current Programming
LTC4007-1
15
40071fa
For more information www.linear.com/LTC4007-1
applicaTions inForMaTion
the full-scale voltage is reduced then, R4 = R5 = 2.49k and
RPROG = 26.7k, the maximum charging current is still 2.5A
but the FLAG trip point is maintained at 10% of full scale.
There are other effects to consider. The voltage across the
current comparator is scaled to obtain the same values as
the 100mV sense voltage target, but the input referred sense
voltage is reduced, causing some careful consideration of
the ripple current. Input referred maximum comparator
threshold is 117mV, which is the same ratio of 1.4x the
DC target. Input referred IREV threshold is scaled back to
–24mV. The current at which the switcher starts will be
reduced as well so there is some risk of boost activity.
These concerns can be addressed by using a slightly larger
inductor to compensate for the reduction of tolerance to
ripple current.
Charger Voltage Programming
Pins CHEM and C3C4 are used to program the charger
final output voltage. The CHEM pin programs Li-Ion bat-
tery chemistry for 4.1V/cell (low) or 4.2V/cell (high). The
C3C4 pin selects either 3 series cells (low) or 4 series
cells (high). It is recommended that these pins be shorted
to ground (logic low) or left open (logic high) to effect
the desired logic level. Use open-collector or open-drain
outputs when interfacing to the CHEM and 3C4C pins from
a logic control circuit.
Table 3. Charger Voltage Programming
VFINAL (V) 3C4C CHEM
12.3 LOW LOW
12.6 LOW HIGH
16.4 HIGH LOW
16.8 HIGH HIGH
Setting the Timer Resistor
The charger termination timer is designed for a range of
1hour to 3 hour with a ±15% uncertainty. The timer is pro-
grammed by the resistor RRT using the following equation:
tTIMER = 10 • 227 • RRT • 17.5pF (seconds)
It is important to keep the parasitic capacitance on the RT
pin to a minimum. The trace connecting RT to RRT should
be as short as possible.
Soft-Start
The LTC4007-1 is soft started by the 0.12µF capacitor on
the ITH pin. On start-up, ITH pin voltage will rise quickly
to 0.5V, then ramp up at a rate set by the internal 40µA
pull-up current and the external capacitor. Battery charg-
ing current starts ramping up when ITH voltage reaches
0.8V and full current is achieved with ITH at 2V. With a
0.12µF capacitor, time to reach full charge current is about
2ms and it is assumed that input voltage to the charger
will reach full value in less than 2ms. The capacitor can
be increased up to 1µF if longer input start-up times are
needed.
Input and Output Capacitors
The input capacitor (C2) is assumed to absorb all input
switching ripple current in the converter, so it must have
adequate ripple current rating. Worst-case RMS ripple
current will be equal to one half of output charging cur-
rent. Actual capacitance value is not critical. Solid tantalum
low ESR capacitors have high ripple current rating in a
RRT (kΩ)
100
0
tTIMER (MINUTES)
50
150
200
250
500
350
300
40071 F07
100
400
450
300
1300500 700 900 1100
Figure 7. tTIMER vs RRT
LTC4007-1
16
40071fa
For more information www.linear.com/LTC4007-1
relatively small surface mount package, but caution must
be used when tantalum capacitors are used for input or
output bypass. High input surge currents can be created
when the adapter is hot-plugged to the charger or when a
battery is connected to the charger. Solid tantalum capaci-
tors have a known failure mechanism when subjected to
very high turn-on surge currents. Only Kemet T495 series
of “Surge Robust” low ESR tantalums are rated for high
surge conditions such as battery to ground.
The relatively high ESR of an aluminum electrolytic for
C1, located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to AN88
for more information.
Highest possible voltage rating on the capacitor will
minimize problems. Consult with the manufacturer before
use. Alternatives include new high capacity ceramic (at
least 20µF) from Tokin, United Chemi-Con/Marcon, et al.
Other alternative capacitors include OS-CON capacitors
from Sanyo.
The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
I
V
V
V
Lf
RMS
BAT BAT
DCIN
=
()
⎛
⎝
⎜⎞
⎠
⎟
()()
0291
1
.–
For example:
VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and
f = 300kHz, IRMS = 0.41A.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or induc-
tors may be added to increase battery impedance at the
300kHz switching frequency. Switching ripple current splits
between the battery and the output capacitor depending
on the ESR of the output capacitor and the battery imped-
applicaTions inForMaTion
ance. If the ESR of C3 is 0.2Ω and the battery impedance
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value
on ripple current and low current operation must also be
considered. The inductor ripple current ∆IL decreases with
higher frequency and increases with higher VIN.
Δ=
()()
⎛
⎝
⎜⎞
⎠
⎟
IfL
V
V
V
L OUT OUT
IN
1
1–
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(IMAX). In no case should
∆IL exceed 0.6(IMAX) due to limits imposed by IREV and
CA1. Remember the maximum ∆IL occurs at the maxi-
mum input voltage. In practice 10µH is the lowest value
recommended for use.
Lower charger currents generally call for larger inductor
values. Use Table 4 as a guide for selecting the correct
inductor value for your application.
Table 4
MAX AVERAGE
CURRENT (A) INPUT VOLTAGE (V)
MINIMUM INDUCTOR
VALUE (µH)
1 ≤20 40 ±20%
1 >20 56 ±20%
2 ≤20 20 ±20%
2 >20 30 ±20%
3 ≤20 15 ±20%
3 >20 20 ±20%
4 ≤20 10 ±20%
4 >20 15 ±20%
LTC4007-1
17
40071fa
For more information www.linear.com/LTC4007-1
applicaTions inForMaTion
Charger Switching Power MOSFET
and Diode Selection
Two external power MOSFETs must be selected for use
with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (syn-
chronous) switch.
The peak-to-peak gate drive levels are set internally. This
voltage is typically 6V. Consequently, logic-level threshold
MOSFETs must be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), total gate capacitance QG, reverse
transfer capacitance CRSS, input voltage and maximum
output current. The charger is operating in continuous
mode at moderate to high currents so the duty cycles for
the top and bottom MOSFETs are given by:
Main Switch Duty Cycle = VOUT/VIN
Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN.
The MOSFET power dissipations at maximum output
current are given by:
PMAIN = VOUT/VIN(IMAX)2(1 + δ∆T)RDS(ON)
+ k(VIN)2(IMAX)(CRSS)(fOSC)
PSYNC = (VIN – VOUT)/VIN(IMAX)2(1 + δ∆T)RDS(ON)
Where δ∆T is the temperature dependency of RDS(ON) and
k is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the PMAIN equation
includes an additional term for transition losses, which
are highest at high input voltages. For VIN < 20V the high
current efficiency generally improves with larger MOSFETs,
while for VIN > 20V the transition losses rapidly increase to
the point that the use of a higher RDS(ON) device with lower
CRSS actually provides higher efficiency. The synchronous
MOSFET losses are greatest at high input voltage or during
a short circuit when the duty cycle in this switch in nearly
100%. The term (1 + δ∆T) is generally given for a MOSFET
in the form of a normalized RDS(ON) vs temperature curve,
but δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. CRSS = QGD/∆VDS is usually specified
in the MOSFET characteristics. The constant k = 2 can be
used to estimate the contributions of the two terms in the
main switch dissipation equation.
If the charger is to operate in low dropout mode or with
a high duty cycle greater than 85%, then the topside P-
channel efficiency generally improves with a larger MOSFET.
Using asymmetrical MOSFETs may achieve cost savings
or efficiency gains.
The Schottky diode D1, shown in the Typical Application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on
and storing charge during the dead-time, which could cost
as much as 1% in efficiency. A 1A Schottky is generally
a good size for 4A regulators due to the relatively small
average current. Larger diodes can result in additional
transition losses due to their larger junction capacitance.
The diode may be omitted if the efficiency loss can be
tolerated.
Calculating IC Power Dissipation
The power dissipation of the LTC4007-1 is dependent upon
the gate charge of the top and bottom MOSFETs (QG1 &
QG2 respectively) The gate charge is determined from the
manufacturer’s data sheet and is dependent upon both
the gate voltage swing and the drain voltage swing of the
MOSFET. Use 6V for the gate voltage swing and VDCIN for
the drain voltage swing.
PD = VDCIN • (fOSC (QG1 + QG2) + IQ)
Example:
VDCIN = 19V, fOSC = 345kHz, QG1 = QG2 = 15nC,
IQ = 5mA
PD = 292mW
LTC4007-1
18
40071fa
For more information www.linear.com/LTC4007-1
applicaTions inForMaTion
Adapter Limiting
An important feature of the LTC4007-1 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the prod-
uct to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.
This feature is created by sensing total adapter output cur-
rent and adjusting charging current downward if a preset
adapter current limit is exceeded. T
rue analog control is
used, with closed-loop feedback ensuring that adapter load
current remains within limits. Amplifier CL1 in Figure 8
senses the voltage across RCL, connected between the
CLP and CLN pins. When this voltage exceeds 100mV,
the amplifier will override programmed charging current
to limit adapter current to 100mV/RCL. A lowpass filter
formed by 5kΩ and 15nF is required to eliminate switch-
ing noise. If the current limit is not used, CLP should be
connected to CLN.
Note that the ICL pin will be asserted when the voltage
across RCL is 93mV, before the adapter limit regulation
threshold.
current limit tolerance and use that current to determine
the resistor value.
RCL = 100mV/ILIM
ILIM = Adapter Min Current –
(Adapter Min Current • 7%)
Table 5. Common RCL Resistor Values
ADAPTER
RATING (A)
RCL VALUE*
(Ω) 1%
RCL POWER
DISSIPATION (W)
RCL POWER
RATING (W)
1.5 0.06 0.135 0.25
1.8 0.05 0.162 0.25
2 0.045 0.18 0.25
2.3 0.039 0.206 0.25
2.5 0.036 0.225 0.5
2.7 0.033 0.241 0.5
3 0.03 0.27 0.5
* Values shown above are rounded to nearest standard value.
As is often the case, the wall adapter will usually have
at least a +10% current limit margin and many times
one can simply set the adapter current limit value to the
actual adapter rating (see Table 5).
Designing the Thermistor Network
There are several networks that will yield the desired func-
tion of voltage vs temperature needed for proper operation
of the thermistor. The simplest of these is the voltage
divider shown in Figure 9. Unfortunately, since the HIGH/
LOW comparator thresholds are fixed internally, there is
only one thermistor type that can be used in this network;
the thermistor must have a HIGH/LOW resistance ratio of
1:7. If this happy circumstance is true for you, then simply
set R9 = RTH(LOW).
100mV
–
+
5k
CLP
LTC4007-1
15
CLN
16
40071 F08
15nF
+
RCL*
CIN
VIN
CL1
AC ADAPTER
INPUT
*RCL = 100mV
ADAPTER CURRENT LIMIT
+
Figure 8. Adapter Current Limiting
Setting Input Current Limit
To set the input current limit, you need to know the mini-
mum wall adapter current rating. Subtract 7% for the input
LTC4007-1
NTC
R9
7
C7 RTH
40071 F09
Figure 9. Voltage Divider Thermistor Network
LTC4007-1
19
40071fa
For more information www.linear.com/LTC4007-1
applicaTions inForMaTion
If you are using a thermistor that doesn’t have a 1:7 HIGH/
LOW ratio, or you wish to set the HIGH/LOW limits to
different temperatures, then the more generic network in
Figure 10 should work.
Once the thermistor, RTH, has been selected and the
thermistor value is known at the temperature limits, then
resistors R9 and R9A are given by:
For NTC thermistors:
R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(LOW) – RTH(HIGH))
R9A = 6 RTH(LOW) • RTH(HIGH)/(RTH(LOW) – 7 •
RTH(HIGH))
Where RTH(LOW) > 7 • RTH(HIGH)
For PTC thermistors:
R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(HIGH) – RTH(LOW))
R9A = 6 RTH(LOW) • RTH(HIGH)/(RTH(HIGH) – 7 •
RTH(LOW))
Where RTH(HIGH) > 7 • RTH(LOW)
Example #1: 10kΩ NTC with custom limits
TLOW = 0°C, THIGH = 50°C
RTH = 10k at 25°C,
RTH(LOW) = 32.582k at 0°C
RTH(HIGH) = 3.635k at 50°C
R9 = 24.55k → 24.3k (nearest 1% value)
R9A = 99.6k → 100k (nearest 1% value)
Example #2: 100kΩ NTC
TLOW = 5°C, THIGH = 50°C
RTH = 100k at 25°C,
RTH(LOW) = 272.05k at 5°C
RTH(HIGH) = 33.195k at 50°C
R9 = 226.9k → 226k (nearest 1% value)
R9A = 1.365M → 1.37M (nearest 1% value)
Example #3: 22kΩ PTC
TLOW = 0°C, THIGH = 50°C
RTH = 22k at 25°C,
RTH(LOW) = 6.53k at 0°C
RTH(HIGH) = 61.4k at 50°C
R9 = 43.9k → 44.2k (nearest 1% value)
R9A = 154k
Sizing the Thermistor Hold Capacitor
During the hold interval, C7 must hold the voltage across
the thermistor relatively constant to avoid false readings.
A reasonable amount of ripple on NTC during the hold
interval is about 10mV to 15mV. Therefore, the value of
C7 is given by:
C7 = tHOLD/(R9/7 • –ln(1 – 8 • 15mV/4.5V))
= 10 • RRT • 17.5pF/(R9/7 • –ln(1 – 8 • 15mV/4.5V)
Example:
R9 = 24.3k
RRT = 309k (~2 hour timer)
C7 = 0.57µF → 0.56µF (nearest value)
Disabling the Thermistor Function
If the thermistor is not needed, connecting a resistor be-
tween DCIN and NTC will disable it. The resistor should be
sized to provide at least 10µA with the minimum voltage
applied to DCIN and 10V at NTC. Do not exceed 30µA.
Generally, a 301k resistor will work for DCIN less than
15V. A 499k resistor is recommended for DCIN between
15V and 24V.
Conditioning Depleted Batteries
Severely depleted batteries, with less than 3.25V/cell,
should be conditioned with a trickle charge to prevent
possible damage. This trickle charge is typically 10% of
the 1C rate of the battery. The LTC4007-1 can automatically
trickle charge depleted batteries using the circuit in Figure
11. If the battery voltage is less than 3.25V/cell (3.173V/
cell if CHEM is low) then the LOBAT indicator will be low
and Q4 is off. This programs the charging current with
RPROG = R6 + R14. Charging current is approximately
LTC4007-1
NTC
R9
7
C7 R9A RTH
40071 F10
Figure 10. General Thermistor Network
LTC4007-1
20
40071fa
For more information www.linear.com/LTC4007-1
applicaTions inForMaTion
300mA. When the cell voltage becomes greater than 3.25V
the LOBAT indicator goes high, Q4 shorts out R13, then
RPROG = R6. Charging current is then equal to 3A.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall times
should be minimized. To prevent magnetic and electrical
field radiation and high frequency resonant problems,
proper layout of the components connected to the IC is
essential. (See Figure 12.) Here is a PCB layout priority list
for proper layout. Layout the PCB using this specific order.
General Rules
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that connect
to the switching FET source pins. The IC can be placed
on the opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
4. Place the output current sense resistor right next to the
inductor output but oriented such that the IC’s current
sense feedback traces going to resistor are not long. The
feedback traces need to be routed together as a single
pair on the same layer at any given time with smallest
trace spacing possible. Locate any filter component on
these traces next to the IC and not at the sense resistor
location.
5. Place output capacitors next to the sense resistor output
and ground.
6. Output capacitor ground connections need to feed into
same copper that connects to the input capacitor ground
before tying back into system ground.
General Rules (Continued)
7. Connection of switching ground to system ground or
internal ground plane should be single point. If the
system has an internal system ground plane, a good
way to do this is to cluster vias into a single star point
to make the connection.
8. Route analog ground as a trace tied back to IC ground
(analog ground pin if present) before connecting to any
other ground. Avoid using the system ground plane.
CAD trick: make analog ground a separate ground net
and use a 0Ω resistor to tie analog ground to system
ground.
9. A good rule of thumb for via count for a given high
current path is to use 0.5A per via. Be consistent.
10. If possible, place all the parts listed above on the same
PCB layer.
11. Copper fills or pours are good for all power con-
nections except as noted above in Rule 3. You can
also use copper planes on multiple layers in parallel
too—this helps with thermal management and lower
trace inductance improving EMI performance further.
12. For best current programming accuracy provide a
Kelvin connection from RSENSE to CSP and BAT. See
Figure 12 as an example.
It is important to keep the parasitic capacitance on the RT,
CSP and BAT pins to a minimum. The traces connecting
these pins to their respective resistors should be as short
as possible.
LTC4007-1
21
40071fa
For more information www.linear.com/LTC4007-1
applicaTions inForMaTion
3C4C
CHEM
LOBAT
ICL
ACP
SHDN
FAULT
CHG
FLAG
NTC
RT
LOBAT
ICL
ACP
SHDN
FAULT
CHG
FLAG
DCIN
INFET
CLP
CLN
TGATE
BGATE
PGND
CSP
BAT
PROG
ITH
GND
LTC4007-1
R9 32.4k 1%
RT
309k
1%
C7
0.47µF
THERMISTOR
TIMING RESISTOR
(~2 HOURS)
R12
100k
R11
100k
R10
100k
VLOGIC *
*
DCIN
0V TO 20V
3A C1
0.1µF
Q3
INPUT SWITCH
C4
15nF
Q1
Q2 D1
C2
20µF
L1
15µH 3A
R1
4.99k
1%
R4
3.01k
1%
R5 3.01k 1%
RSENSE
0.033Ω
1%
RCL
0.033Ω
1%
C3
20µF
*PIN OPEN
D1: MBRM140T3
Q1: Si4431BDY
Q2: FDC645N
Q4: 2N7002 OR BSS138
BAT
MONITOR
(CHARGING
CURRENT
MONITOR)
SYSTEM
LOAD
C6
0.12µF
R7
6.04k
1%
R14
52.3k
1%
C5
0.0047µF
40071 F11
R6
26.7k
1%
Q4
Figure 11. Circuit Application (16.8V/3A) to Automatically Trickle Charge Depleted Batteries
40071 F12
VBAT
L1
VIN
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
SWITCH NODE
C2 C3
D1
Figure 12. High Speed Switching Path Figure 13. Kelvin Sensing of Charging Current
CSP
40071 F13
DIRECTION OF CHARGING CURRENT
RSENSE
BAT
LTC4007-1
22
40071fa
For more information www.linear.com/LTC4007-1
Please refer to http://www.linear.com/product/LTC4007-1#packaging for the most recent package drawings.
package DescripTion
4.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
23 24
1
2
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05 R = 0.115
TYP
R = 0.05 TYP PIN 1 NOTCH
R = 0.20 OR C = 0.35
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD24) QFN 0506 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.65 ±0.05
2.00 REF
3.00 REF
4.10 ±0.05
5.50 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
2.65 ±0.10
2.00 REF
3.00 REF
3.65 ±0.10
3.65 ±0.05
UFD Package
24-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1696 Rev A)
LTC4007-1
23
40071fa
For more information www.linear.com/LTC4007-1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 11/16 Revised package drawing 22
LTC4007-1
24
40071fa
For more information www.linear.com/LTC4007-1
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2005
LT/TP 1116 REV A • PRINTED IN USA
relaTeD parTs
Typical applicaTion
12.6V, 4A Li-Ion Battery Charger
3C4C
CHEM
LOBAT
ICL
ACP
SHDN
FAULT
CHG
FLAG
NTC
RT
LOBAT
ICL
ACP
SHDN
FAULT
CHG
FLAG
DCIN
INFET
CLP
CLN
TGATE
BGATE
PGND
CSP
BAT
PROG
ITH
GND
LTC4007-1
R9 32.4k 1%
RRT
309k
1%
C7
0.47µF
THERMISTOR
10k
NTC
TIMING RESISTOR
(~2 HOURS)
R12
100k *
R11
100k
R10
100k
VLOGIC
DCIN
0V TO 20V
3A C1
0.1µF
Q3
INPUT SWITCH
C4
15nF
Q1
Q2 D1
C2
20µF
L1
10µH 4A
R1
4.99k
1%
R4
3.01k 1%
R5 3.01k 1%
RSENSE
0.025Ω
1%
RCL
0.033Ω
1%
C3
20µF
BAT
CHARGING
CURRENT
MONITOR
SYSTEM
LOAD
C6
0.12µF
R7
6.04k
1% RPROG
26.7k
1%
C5
0.0047µF *PIN OPEN
D1: MBRS130T3
Q1: Si4431BDY
Q2: FDC645N
40071 TA02
PART NUMBER DESCRIPTION COMMENTS
LT
®
1511 Constant-Current/Constant-Voltage 3A Battery
Charger with Input Current Limiting
High Efficiency Current Mode PWM with 4A Internal Switch
LT1513 SEPIC Constant- or Programmable-Current/
Constant-Voltage Battery Charger
Charger Input Voltage May Be Higher, Equal to or Lower Than Battery Voltage;
Charges Any Number of Cells Up to 20V, 500kHz Switching Frequency
LT1571 1.5A Switching Charger 1- or 2-Cell Li-Ion, 500kHz or 200kHz Switching Frequency, Termination Flag
LTC1628-PG 2-Phase, Dual Synchronous Step-Down Controller Minimizes CIN and COUT
, Power Good Output, 3.5V ≤ VIN ≤ 36V
LTC1709 2-Phase, Dual Synchronous Step-Down Controller
with VID
Up to 42A Output, Minimum CIN and COUT
, Uses Smallest Components for
Intel and AMD Processors
LT1769 2A Switching Battery Charger Constant-Current/Constant-Voltage Switching Regulator, Input Current
Limiting Maximizes Charge Current
LTC1778 Wide Operating Range, No RSENSE Synchronous
Step-Down Controller
2% to 90% Duty Cycle at 200kHz, Stable with Ceramic COUT
LTC1960 Dual Battery Charger/Selector with SPI Interface Simultaneous Charge or Discharge of Two Batteries, DAC Programmable
Current and Voltage, Input Current Limiting Maximizes Charge Current
LTC3711 No RSENSE™ Synchronous Step-Down Controller with
VID
3.5V ≤ VIN ≤ 36V, 0.925V ≤ VOUT ≤ 2V, for Transmeta, AMD and Intel
Mobile Processors
LTC4006 Small, High Efficiency, Fixed Voltage, Lithium-Ion
Battery Charger
Constant-Current/Constant-Voltage Switching Regulator with Termination
Timer, AC Adapter Current Limit and Thermistor Sensor in a Small 16-Pin
Package
LTC4007 4A High Efficiency, Standalone Li-Ion Battery Charger Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit and
Thermistor Sensor, 16-Pin Narrow SSOP Package
LTC4008 High Efficiency, Programmable Voltage/Current
Battery Charger
Constant-Current/Constant-Voltage Switching Regulator, Resistor Voltage
Current Programming, AC Adapter Current Limit and Thermistor Sensor
LTC4100 Smart Battery Charger Controller 100% Compliant SMBus 1.1 Support, VIN: 6.4V to 26V, VDROPOUT = 0.5V,
High Efficiency Synchronous Buck Charger
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4007-1