AOZ8005 Ultra-Low Capacitance TVS Diode Array General Description Features The AOZ8005 is a transient voltage suppressor array designed to protect high speed data lines such as HDMI and Gigabit Ethernet from damaging ESD events. ESD protection for high-speed data lines: - IEC 61000-4-2, level 4 (ESD) immunity test - 15kV (air discharge) and 8kV (contact discharge) - Human Body Model (HBM) 15kV Array of surge rated diodes with internal TVS diode Small package saves board space Protects four I/O lines Low capacitance between I/O lines: 0.47pF Low clamping voltage Low operating voltage: 5.0V This device incorporates eight surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. The AOZ8005 provides a typical line to line capacitance of 0.47pF and low insertion loss up to 2GHz providing greater signal integrity making it ideally suited for HDMI 1.3 applications, such as Digital TVs, DVD players, set-top boxes and mobile computing devices. The AOZ8005 comes in RoHS compliant, tiny SOT-23-6 and MSOP-10 packages and is rated -40C to +85C junction temperature range. The MSOP package features a flow through layout design. Applications HDMI ports Monitors and flat panel displays Set-top box USB 2.0 power and data line protection Video graphics cards Digital Video Interface (DVI) 10/100/1000 Ethernet Notebook computers Typical Application AOZ8005 AOZ8005 TX2+ TX2- RX2+ RX2- TX1+ RX1+ RX1- TX1HDMI Transmitter TX0+ TX0- RX0+ RX0- CLK+ CLK- CLK+ CLKConnector HDMI Receiver Connector AOZ8005 AOZ8005 Figure 1. HDMI Ports Rev. 2.3 January 2009 www.aosmd.com Page 1 of 14 AOZ8005 Ordering Information Part Number Ambient Temperature Range Package AOZ8005CI Environmental SOT-23-6 AOZ8005CIL -40C to +85C RoHS Compliant Green Product SOT-23-6 AOZ8005FI MSOP-10 All AOS products are offered in packages with Pb-free plating and compliant to RoHS standards. Parts marked as Green Products (with "L" suffix) use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. Pin Configuration CH1 VN CH2 1 6 2 5 3 4 CH4 VP CH3 CH1 1 10 NC CH2 2 9 NC VN 3 8 VP CH3 4 7 NC CH4 5 6 NC SOT23-6 MSOP-10 (Top View) (Top View) Absolute Maximum Ratings Exceeding the Absolute Maximum ratings may damage the device. Parameter Rating Storage Temperature (TS) -65C to +150C ESD Rating per IEC61000-4-2, contact (1) 8kV ESD Rating per IEC61000-4-2, air(1) ESD Rating per Human Body 15kV Model(2) 15kV Notes: 1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330. 2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5k. Maximum Operating Ratings Parameter Rating Junction Temperature (TJ) Rev. 2.3 January 2009 -40C to +125C www.aosmd.com Page 2 of 14 AOZ8005 Electrical Characteristics TA = 25C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40C to +85C. Symbol VRWM Parameter Reverse Working Voltage Conditions Between VP and VN Min. (4) VBR Reverse Breakdown Voltage IT = 1mA, between VP and VN IR Reverse Leakage Current VRWM = 5V, between VP and VN VF Diode Forward Voltage IF = 15mA VCL Cj Units 5.5 V 6.6 V A 1 V 10.50 -2.00 V V 12.50 -3.50 V V 16.00 -5.50 V V 1.0 1.05 pF 0.47 0.50 pF VP = 3.3V, VR = 1.65V, f = 1MHz, any I/O pin to Ground 0.75 0.85 pF VP = 5.0V, VR = 2.5V, f = 1MHz, any I/O pins to ground 0.75 0.85 pF 0.03 pF 0.70 0.85 (5) Channel Clamp Voltage Positive Transients Negative Transient IPP = 1A, tp = 100ns, any I/O pin to Ground Channel Clamp Voltage Positive Transients Negative Transient IPP = 5A, tp = 100ns, any I/O pin to Ground(5) Channel Clamp Voltage Positive Transients Negative Transient IPP = 12A, tp = 100ns, any I/O pin to Ground(5) Channel Input Capacitance VR = 0V, f = 1MHz, any I/O pin to Ground(6) Channel Input Capacitance Matching Max. 1 VR = 0V, f = 1MHz, between I/O Cj Typ. (3) pins(6) VR = 0V, f = 1MHz, between I/O pins Notes: 3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at the pulse test current IT. 5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system. 6. Measure performed with no external capacitor on VP . Rev. 2.3 January 2009 www.aosmd.com Page 3 of 14 AOZ8005 Typical Operating Characteristics Clamping Voltage vs. Peak Pulse Current Forward Voltage vs. Forward Current (tperiod = 100ns, tr = 1ns) 17 7 16 6 Forward Voltage (V) Clamping Voltage, Vcl (V) (tperiod = 100ns, tr = 1ns) 15 14 13 12 5 4 3 2 1 11 0 10 0 2 4 6 8 Peak Pulse Current (A) 10 12 0 Insertion Loss (dB) Capacitance (pF) VP = Floating 1 VP = 3.3V 0.5 0 0.5 1 2 3 1.5 2.5 3.5 Reverse Volts, Vr (V) 4 4 6 8 Forward Current (A) 10 12 I/O - Gnd Insertion Loss vs. Frequency Capacitance vs. Reverse Voltage 1.5 0 2 4.5 5 21 18 15 12 9 6 3 0 -3 -6 -9 -12 -15 -18 -21 VP = Floating VP = 3.3V 1 10 100 1000 Frequency (MHz) ESD Response (8kV Contact per IEC61000-4-2) Insertion Loss vs. Frequency 3 S21 (dB) 0 VP = Floating -3dB 2,340MHz -3 -6 -9 -12 1 10 100 1,000 10,000 Frequency (MHz) Rev. 2.3 January 2009 www.aosmd.com Page 4 of 14 AOZ8005 Application Information The AOZ8005 TVS is design to protect four high speed data lines from ESD and transient over-voltage by clamping them to a fixed voltage. When the voltages on the protected lines exceed the limit, the internal steering diode are forward bias will conduct the harmful transient away from the sensitive circuitry. As system frequency increase, printed circuit board layout becomes more complex. A successful high speed board must integrate the device and traces while avoiding signal transmission problems associated with HDMI data speed. High Speed HDMI PCB Layout Guidelines Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The AOZ8005 devices should be located as close as possible to the noise source. The placement of the AOZ8005 devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8005 devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8005 device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC's signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS's clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8005 ultra-low capacitance TVS is designed to protect four high speed data transmission lines from Rev. 2.3 January 2009 transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. The AOZ8005 is designed for the ease of PCB layout by allowing the traces to run underneath the device. The pinout of the AOZ8005 is design to simply drop onto the IO lines of a High Definition Multimedia Interface (HDMI) design without having to divert the signal lines that may add more parasitic inductance. Pins 1, 2, 4 and 5 are connected to the internal TVS devices and pins 6, 7, 9 and 10 are no connects. The no connects was done so the package can be securely soldered onto the PCB surface. See Figure 2. CH 1 CH 1 CH 2 CH 2 VN VP CH 3 CH 3 CH 4 CH 4 Figure 2. Flow through Layout for two Line Pair It is crucial that the layout is successful for a HDMI design PCB board. Some of the problems associated with high speed design are matching impedance of the traces and to minimize the crosstalk between parallel traces. This application note is to provide you as much information to successfully design a high speed PCB using Alpha & Omega devices. The HDMI video signals are transmitted on a very high speed pair of traces and any amount of capacitance, inductance or even bends in a trace can cause the impedance of a differential pair to drop as much as 40. This is not desirable because HDMI ports must maintain a 100 15% on each of the four pairs of its differential lines per HDMI Compliance Test Specifications. The HDMI CTS specifies that the impedance on the differential pair of a receiver must be measured using a Time Domain Reflectometry method with a pulse rise time of 200pS. The TDR measurements of the PCB traces allows to locate and model discontinuities cause by the geometrical features of a bend and by the frequencydependant losses of the trace itself. These fast edge rates can contribute to noise and crosstalk, depending on the traces and PCB dielectric construction material. www.aosmd.com Page 5 of 14 AOZ8005 Material selection is another aspect that determines good characteristic impedance in the lines. Different material will give you different results. The dielectric material will have the dielectric constant (r). Where Q1, Q2 = charges, r = distance between charges (m), F = force(N), = permittivity of dielectric (F/m). By solving for Zo you can calculate the differential impedance with the equation below. D - 0.96 ---- h Zdiff = 2 x Zo 1 - 0.48e (4) Zdiff = 100.77 Q1 Q2 F = --------------2 4r (1) Adjust the trace width, height, distance between the traces and FR4 thickness to obtain the desired 100 differential impedance. The general rule of thumb is to route the traces as short as possible, use differential routing strategies whenever feasible and match the length and bends to each of the differential traces. Each PCB substrate has a different relative dielectric constant. The dielectric constant is the permittivity of a relative that of empty space. Where r = dielectric constant, = permittivity, and o = permittivity of empty space. r = ----o (2) The dielectric constant affects the impedance of a transmission line and can propagate faster in materials that have a lower r . The frequency in your design will depend on the material being used. With equation 1 you can determine the type of material to use. If higher frequency is required other board material maybe considered. GETEK is another material that can be used in high speed boards. They have a typical r between 3.6 to 4.0. The most common type of dielectric material used for PCB is FR-4. Typical dielectric constant for FR-4 is between 4.0 to 4.5. Most PCB manufacture will be able to give you the exact value of the FR-4 dielectric constant. Once you determined the dielectric constant of the board material you can start to calculate the impedance of each trace. Below are the formulas for a microstrip layout. This impedance is dependant on the width of the microstrip (W) the thickness (t) of the trace and the height (h) of the FR4 material, and (D) trace edge to edge spacing. W D W The graphs below show the differential impedance with varying trace width without the AOZ8005 MSOP-10 package part on it. Each of the graphs and board layout represent changing trace width from 50 to 80 in increment of 10. Figure 4. 100 Differential Impedance Max 103, Min 97 t Trace r Dielectric Material H Ground Figure 3. Typical value of W = 12.6 mil, h = 10mils, D = 10mils, t = 1.4mils and r = 4.0 with the equation below for a microstrip impedance yields: 87 5.98 x h Zo = -------------------------- = ln ---------------------- 0.8W + t r + 1.41 Figure 5. 120 Differential Impedance Max 110, Min 102 (3) Zo = 61.73 Rev. 2.3 January 2009 www.aosmd.com Page 6 of 14 AOZ8005 X Zo = 61 Zo = 61 C(TVS) Z1 Figure 7. Figure 6. 140 Differential Impedance Max 102, Min 92 Z1 K = -----Z0 (5) Z 0 C TVS K X = --------------------- ---------------- 2 K -1 (6) Z0 is the normal 61 differential impedance on the trace. Z1 is the needed impedance to compensate for the added C(TVS) K is defined as the unloaded impedance of the adjusted trace. X is the length of the trace needed for the compensation. is the propagation delay time required for a signal to travel from one point to another. This value should be less than 200pS. Figure 7. 160 Differential Impedance Max 123, Min 109 Differentail Impedance () 140 120 From the above method the designer should layout the boards with a 50 common mode trace. The result should give you approximately 100 differential impedance. Z1 is the impedance that you choose in order to compensate the TVS capacitance. Based on Z1 value, we can get the length of the segment from the above equations. With the value of Z1 = 80, Zo = 61, C(TVS) = 0.94 and = 180. The X(mils) equates to 580 mils. Max. 100 Min. 80 60 40 20 0 50 55 60 65 70 75 80 Common Mode Impedance () Figure 8. Differential Impedance By adding a TVS onto the traces it can have a large effect on the impedance of the line. This addition of a capacitance added to a 100 differential transmission line without any compensation may decrease the impedance as much as 20 or more. Below is a formula to calculate the length for the compensation of C(TVS). Rev. 2.3 January 2009 Page 8 has a series of graph that represent changing width and length of the trace from 50 to 80 in increment of 10 with a MSOP-10 package solder onto the board. As you can observe from the graphs, a small incremental capacitance that is added to the differential lines can significantly decrease the differential impedance. Thus violated the HDMI specification of 10015%. www.aosmd.com Page 7 of 14 AOZ8005 Figure 10. 100 Differential Impedance with AOZ8007 MSOP-10 Package on it Max. 97, Min. 80 Figure 12. 140 Differential Impedance with AOZ8007 MSOP-10 Package on it Max. 102, Min. 92 Figure 11. 120 Differential Impedance with AOZ8007 MSOP-10 Package on it Max. 99, Min. 86 Figure 13. 160 Differential Impedance with AOZ8007 MSOP-10 Package on it Max. 101, Min. 95 From Figure 13 we are able to get the best result from using all of the equation above. With the value of Z1 = 80, Z0 = 61, C(TVS) = 0.94, = 180 and from Table 1. The X(mils) equates to 580mils to give the best compensated differential impedance on the traces for the added capacitance from the AOZ8005. Rev. 2.3 January 2009 Table 1. AOZ8005 MSOP-10 HDMI Evaluation Board Specification Number of layers 4 Copper Trace Thickness 1.4 mils Dielectric Constant r 4 Overall Board Thickness 62 mils Dielectric thickness between top and ground layer 10 mils www.aosmd.com Page 8 of 14 AOZ8005 Conclusion This application section discusses ESD protection while maintaining the differential impedance of a HMDI sink device. Since the TVS add capacitance we must design the board to meet the HDMI requirements. This application note is a guideline to calculate and layout the PCB. Different board manufacture and process will fluctuate and will cause the final board to vary slightly. You must carefully plan out a successful high speed HDMI PCB. Factor such as PCB stack up, ground bounce, crosstalk and signal reflection can interfere with a signal. The layout, trace routing, board materials and impedance calculation discussed in this application note can help you design a more effective PCB using the AOZ8005 devices. 100 Differential 132 Differential 580 mils Figure 14. Recommend Layout for MSOP-10 Package 100 Differential 132 Differential Table 2. AOZ8005 SOT-23-6 Evaluation Board Specifications 580 mils Total Distance Number of layers 4 Copper Trace Thickness 1.4 mils Dielectric Constant r 4 Overall Board Thickness 62 mils Dielectric thickness between top and ground layer 10 mils Figure 15. Recommended Layout for SOT-23 Package Rev. 2.3 January 2009 www.aosmd.com Page 9 of 14 AOZ8005 Package Dimensions, SOT23-6L Gauge Plane D e1 Seating Plane 0.25mm c L E E1 1 e b A2 A .010mm A1 Dimensions in millimeters RECOMMENDED LAND PATTERN 2.40 0.80 0.95 0.63 UNIT: mm Dimensions in inches Symbols A A1 A2 Min. 0.90 0.00 0.80 Nom. -- -- 1.10 Max. 1.25 0.15 1.20 Symbols A A1 A2 Min. 0.035 0.00 0.031 Nom. -- -- 0.043 Max. 0.049 0.006 0.047 b c D E E1 0.30 0.08 2.70 2.50 1.50 0.40 0.13 2.90 2.80 1.60 0.50 0.20 3.10 3.10 1.70 b c D E E1 0.012 0.003 0.106 0.098 0.059 0.016 0.005 0.114 0.110 0.063 0.020 0.008 0.122 0.122 0.067 e e1 L 1 0.95 BSC 1.90 BSC 0.30 -- 0.60 0 -- 8 e e1 L 1 0.037 BSC 0.075 BSC 0.012 -- 0.024 0 -- 8 Notes: 1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each. 2. Dimension "L" is measured in gauge plane. 3. Tolerance 0.100mm (4 mil) unless otherwise specified. 4. Followed from JEDEC MO-178C & MO-193C. 6. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact. Rev. 2.3 January 2009 www.aosmd.com Page 10 of 14 AOZ8005 Tape and Reel Dimensions, SOT23-6L Tape P1 D1 T P2 E1 E2 E B0 K0 A0 D0 P0 Feeding Direction Unit: mm Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T SOT-23 (8mm) 3.15 0.10 3.20 0.10 1.40 0.10 1.00 Min. 1.50 0.10 8.00 0.30 1.75 0.10 3.50 0.05 4.00 0.10 4.00 0.10 2.00 0.05 0.25 0.05 Reel W1 S G N M K V R H Unit: mm W Tape Size Reel Size M N W W1 H K S G R V 8mm o180 o180.00 0.50 o60.50 9.00 0.30 11.40 1.00 o13.00 10.60 2.00 0.50 o9.00 5.00 18.00 +0.50 / -0.20 Leader/Trailer and Orientation Trailer Tape (300mm min., 75 Empty Pockets) Rev. 2.3 January 2009 Components Tape Orientation in Pocket www.aosmd.com Leader Tape (500mm min., 125 Empty Pockets) Page 11 of 14 AOZ8005 Package Dimensions, MSOP-10L Gauge Plane Seating Plane 0.25 C L E1 E D 12(4x) A2 A b e RECOMMENDED LAND PATTERN 0.76 0.30 4.37 0.50 UNIT: mm A1 Dimensions in millimeters Dimensions in inches Symbols A Min. 0.81 Nom. 1.02 Max. 1.12 Symbols A A1 A2 b C D E E1 e L y 0.05 0.76 0.15 0.13 2.90 4.70 2.90 -- 0.40 -- -- 0.86 0.20 0.15 3.00 4.90 3.00 0.50 0.53 -- 0.15 0.97 0.30 0.23 3.10 5.10 3.10 -- 0.66 0.10 A1 A2 b C D E E1 e L y 0 -- 6 Min. 0.032 Nom. 0.040 Max. 0.044 0.002 -- 0.006 0.030 0.034 0.038 0.006 0.008 0.012 0.005 0.006 0.009 0.114 0.118 0.122 0.185 0.193 0.201 0.114 0.118 0.122 -- 0.0197 -- 0.016 0.021 0.026 -- -- 0.004 0 -- 6 Notes: 1. All dimensions are in millimeters. 2. Tolerance 0.10mm unless otherwise specified. 3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each. 4. Dimension L is measured in gauge plane. 5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. Rev. 2.3 January 2009 www.aosmd.com Page 12 of 14 AOZ8005 Tape and Reel Dimensions, MSOP-10 Carrier Tape P1 P2 D1 T E1 E2 E B0 D0 K0 P0 Section Y-Y' A0 Feeding Direction P0 8.00 0.10 T P2 P1 0.30 2.00 4.00 0.05 0.05 0.05 UNIT: mm Package MSOP-10 (12mm) A0 5.3 0.1 B0 3.4 0.1 K0 1.4 0.1 D0 1.6 0.1 D1 1.5 +0.1/-0 E 12.0 0.3 E1 1.75 0.10 E2 5.50 0.05 Reel W1 S G N M K V R H W UNIT: mm Tape Size Reel Size 12mm o330 M o330 0.5 N o97.0 1.0 W 13.00 W1 17.40 H o13.0 +0.5/-0.2 K 10.60 S 2.0 0.5 G -- R -- V -- Leader/Trailer and Orientation Trailer Tape 300mm min. or 75 empty sockets Rev. 2.3 January 2009 Components Tape Orientation in Pocket www.aosmd.com Leader Tape 500mm min. or 125 empty sockets Page 13 of 14 AOZ8005 Park Marking (SOT-23) ACOW Part Number Code Assembly Lot Code ACOW Part Number Code Underline Denotes Green Code Week & Year Code LT AOZ8005CIL (SOT-23) LT AOZ8005CI Assembly Lot Code Week & Year Code Option & Assembly Location Code Option & Assembly Location Code AOZ8005FI (MSOP-10) 8005 IO76 P 11 Product Name Extension Character Part Number Code Week Code Year Code Assembly Lot Code Option Code Assembly Location Code This datasheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 2.3 January 2009 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 14 of 14