TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Wide Range of Supply Voltages
2 V to 8 V
D
Fully Characterized at 3 V and 5 V
D
Very-Low Supply-Current Drain
240 µA Typ at 3 V
D
Common-Mode Input Voltage Range
Includes Ground
D
High Input Impedance ...10
12 Ω Typ
D
Fast Response Time . . . 200 ns Typ for
TTL-Level Input Step
D
Extremely Low Input Bias Current
5 pA Typ
D
Output Compatible With TTL, MOS, and
CMOS
D
Built-In ESD Protection
description
The TLV2354 consists of four independent,
low-power comparators specifically designed for
single power-supply applications and operateS
with power-supply rails as low as 2 V. When
powered from a 3-V supply, the typical supply
current is only 240 µA.
The TLV2354 is designed using the Texas Instruments LinCMOS technology and, therefore, features an
extremely high input impedance (typically greater than 1012 Ω), which allows direct interfacing with
high-impedance sources. The outputs are N-channel open-drain configurations that require an external pullup
resistor to provide a positive output voltage swing, and they can be connected to achieve positive-logic
wired-AND relationships. The TLV2354I is fully characterized for operation from – 40°C to 85°C. The TLV2354M
is fully characterized for operation from – 55°C to 125°C.
The TLV2354 has internal electrostatic-discharge (ESD)-protection circuits and has been classified with a
1000-V ESD rating using human body model testing. However, care should be exercised in handling this device
as exposure to ESD may result in degradation of the device parametric performance.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
TAVIOmax
at 25°CSMALL
OUTLINE
(D)†
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
TSSOP
(PW)‡
CERAMIC
FLATPACK
(W)
CHIP
FORM
(Y)
–40°C to
85°C5 mV TLV2354ID — — TLV2354IN TLV2354IPW —
TLV2354Y
–55°C to
125°C5 mV — TLV2354MFK TLV2354MJ — — TLV2354MW
TLV2354Y
†The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLV2352IDR).
‡The PW packages are only available left-ended taped and reeled (e.g., TLV2354IPW).
These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
LINCMOS is a trademark of Texas Instruments.
OUT
symbol (each comparator)
IN+
IN–
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TLV2354M
J OR W PACKAGE
(TOP VIEW)
NC – No internal connection
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
VDD–/GND
NC
4IN+
NC
4IN–
VDD+
NC
2IN–
NC
2IN+
2OUT
1OUT
NC
3IN–
3IN + 3OUT
4OUT
1IN–
1IN+
NC
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
2OUT
VDD+
2IN–
2IN+
1IN–
1IN+
3OUT
4OUT
VDD–/GND
4IN+
4IN–
3IN+
3IN–
TLV2354I
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
2OUT
VDD+
2IN–
2IN+
1IN–
1IN+
3OUT
4OUT
VDD–/GND
4IN+
4IN–
3IN+
3IN–
TLV2354I
PW PACKAGE
(TOP VIEW)
TLV2354AM, TL V2354M
FK PACKAGE
3OUT
4OUT
VDD–/GND
4IN+
4IN–
3IN+
3IN–
1OUT
2OUT
VDD+
2IN–
2IN+
1IN–
1IN+
TLV2254, TLV2254Y
SLCS012C – MAY 1992 – REVISED AUGUST 2000
QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORSLinCMOS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•3
equivalent schematic
Common to All Channels
VDD
GND
OUT
IN+ IN–
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354Y chip information
This chip, when properly assembled, displays characteristics similar to the TLV2354. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip may be mounted with
conductive epoxy or a gold-silicon preform.
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
+
–OUT
IN+
IN–
VDD
GND
(10)
(7)
(6)
(11)
(1)
–
+
(13)
IN+
IN–
OUT
(12)
(4)
(5)
–
+
(2)
+
–
(9)
(8) (14) OUT
IN+
IN–
OUT IN+
IN–
(3)
BONDING PAD ASSIGNMENTS
65
90
(13)
(1)
(3) (4) (5) (6)
(7)
(8)
(9)(10)
(11)
(12)
(14)
(2)
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI –0.3 to 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of output short-circuit current to GND (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV2354I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV2354M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package 260°C. . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FK, J, or W package 300°C. . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at the noninverting input terminal with respect to the inverting input terminal.
3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING
FACTOR TA = 85°C
POWER RATING TA = 125°C
POWER RATING
D
FK
J
N
PW
W
950 mW
1375 mW
1375 mW
1150 mW
700 mW
700 mW
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
9.2 mW/°C
5.6 mW/°C
5.5 mW/°C
494 mW
715 mW
715 mW
598 mW
364 mW
370 mW
—
275 mW
275 mW
—
—
150 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD 2 8 V
Common mode in
p
ut voltage VIC
VDD = 3 V 0 1.75
V
Common
-
mode
inp
u
t
v
oltage
,
V
IC VDD = 5 V 0 3.75
V
O
p
erating free-air tem
p
erature TA
TLV2354I –40 85 °
C
O erating
free
-
air
tem erature
,
TA
TLV2354M –55 125
°C
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature†
‡
TLV2354I
PARAMETER TEST CONDITIONS TA
‡
VDD = 3 V VDD = 5 V UNIT
A
MIN TYP MAX MIN TYP MAX
VIO
In
p
ut offset voltage
VIC =V
ICRmin
See Note 4
25°C1 5 1 5
mV
V
IO
Inp
u
t
offset
v
oltage
V
IC =
V
ICR
min
,
See
Note
4
Full range 7 7
mV
IIO
In
p
ut offset current
25°C1 1 pA
I
IO
Inp
u
t
offset
c
u
rrent
85°C1 1 nA
IIB
In
p
ut bias current
25°C5 5 pA
I
IB
Inp
u
t
bias
c
u
rrent
85°C2 2 nA
Common mode in
p
ut
25°C0 to 2 0 to 4
VICR
Common
-
mode
inp
u
t
voltage range Full range 0 to
1.75 0 to
3.75 V
IOH
High-level output
VID =1V
25°C0.1 0.1 nA
I
OH
g
current
V
ID =
1
V
Full range 1 1 µA
VOL
Low-level output
VID =1V
IOL =2mA
25°C115 300 150 400
mA
V
OL voltage
V
ID = –
1
V
,
I
OL =
2
mA
Full range 600 700
mA
IOL Low-level output
current VID = –1 V, VOL = 1.5 V 25°C 6 16 6 16 mA
IDD
Su
pp
ly current
VID =1V
No load
25°C240 500 290 600
µA
I
DD
S
u
ppl
y
c
u
rrent
V
ID =
1
V
,
No
load
Full range 700 800 µ
A
†All characteristics are measured with zero common-mode input voltage unless otherwise noted.
‡Full range is –40°C to 85°C. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The of fset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V, 2 V with VDD = 3 V, or
below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and
checking for the appropriate output state.
switching characteristics, VDD = 3 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLV2354I
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
Res
p
onse time
RL = 5.1 kΩ,CL = 15 pF
§
,
100 mV in
p
ut ste
p
with 5 mV overdrive
640
ns
Response
time
See Note 5
L
100
-
mV
inp
u
t
step
w
ith
5
-
mV
o
v
erdri
v
e
640
ns
§CL includes probe and jig capacitance.
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with
VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.
switching characteristics, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLV2354I
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
Res
p
onse time
RL = 5.1 kΩ,C
L
= 15 pF
§
,100-mV input step with 5-mV overdrive 650
ns
Response
time
L
See Note 5
L,
TTL-level input step 200
ns
§CL includes probe and jig capacitance.
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with
VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature†
‡
TLV2354M
PARAMETER TEST CONDITIONS TA
‡
VDD = 3 V VDD = 5 V UNIT
A
MIN TYP MAX MIN TYP MAX
VIO
In
p
ut offset voltage
VIC =V
ICRmin
See Note 4
25°C1 5 1 5
mV
V
IO
Inp
u
t
offset
v
oltage
V
IC =
V
ICR
min
,
See
Note
4
Full range 10 10
mV
IIO
In
p
ut offset current
25°C1 1 pA
I
IO
Inp
u
t
offset
c
u
rrent
125°C10 10 nA
IIB
In
p
ut bias current
25°C5 5 pA
I
IB
Inp
u
t
bias
c
u
rrent
125°C20 20 nA
Common mode in
p
ut
25°C0 to 2 0 to 4
VICR
Common
-
mode
inp
u
t
voltage range Full range 0 to
1.75 0 to
3.75 V
IOH
High-level output
VID =1V
25°C0.1 0.1 nA
I
OH
g
current
V
ID =
1
V
Full range 1 1 µA
VOL
Low-level output
VID =1V
IOL =2mA
25°C115 300 150 400
mA
V
OL voltage
V
ID = –
1
V
,
I
OL =
2
mA
Full range 600 700
mA
IOL Low-level output
current VID = –1 V, VOL = 1.5 V 25°C 6 16 6 16 mA
IDD
Su
pp
ly current
VID =1V
No load
25°C240 500 290 600
µA
I
DD
S
u
ppl
y
c
u
rrent
V
ID =
1
V
,
No
load
Full range 700 800 µ
A
†All characteristics are measured with zero common-mode input voltage unless otherwise noted.
‡Full range is –55°C to 125°C. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The of fset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V, 2 V with VDD = 3 V, or
below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and
checking for the appropriate output state.
switching characteristics, VDD = 3 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLV2354M
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
Res
p
onse time
RL = 5.1 kΩ,CL = 100 pF
§
,
100 mV in
p
ut ste
p
with 5 mV overdrive
1400
ns
Response
time
See Note 5
L
100
-
mV
inp
u
t
step
w
ith
5
-
mV
o
v
erdri
v
e
1400
ns
§CL includes probe and jig capacitance.
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with
VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.
switching characteristics, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLV2354M
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
Res
p
onse time
RL = 5.1 kΩ,C
L
= 100 pF
§
,100-mV input step with 5-mV overdrive 1300
ns
Response
time
L
See Note 5
L,
TTL-level input step 900
ns
§CL includes probe and jig capacitance.
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with
VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, TA = 25°C†
TLV2354Y
PARAMETER TEST CONDITIONS VDD = 3 V VDD = 5 V UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage VIC = VICRmin, See Note 4 1 5 1 5 mV
IIO Input offset current 1 1 pA
IIB Input bias current 5 5 pA
VICR Common-mode input voltage range 0 to 2 0 to 4 V
IOH High-level output current VID = 1 V 0.1 0.1 nA
VOL Low-level output voltage VID = –1 V, IOL = 2 mA 115 300 150 400 mV
IOL Low-level output current VID = –1 V, VOL = 1.5 V 6 16 6 16 mA
IDD Supply current VID = 1 V, No load 240 500 290 600 µA
†All characteristics are measured with zero common-mode input voltage unless otherwise noted.
NOTE 4: The of fset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V, 2 V with VDD = 3 V, or
below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and
checking for the appropriate output state.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
550
440
220
110
0
990
330
024681012
770
660
880
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1100
14 16
IOL – Low-Level Output Current – mA
VDD = 3 V
TA = 25°C
VOL – Low-Level Output V oltage – mV
Figure 2
300
280
240
220
200
380
260
– 75 – 50 –25 0 25 50 75
340
320
360
100 125
IDD – Supply Current –
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
No Load
VDD = 5 V
VDD = 3 V
Aµ
180
Figure 3
0
– 0.5
– 1
– 75 – 50 – 25 0 25 50
2
2.5
COMMON-MODE INPUT VOLTAGE RANGE
vs
FREE-AIR TEMPERATURE
3
75 100 125
1.5
0.5
TA – Free-Air Temperature – °C
– Common-Mode Input Voltage Range – V
ICR
V
VDD = 3 V
Negative Limit
Positive Limit
1
Figure 4
25
20
10
5
0
45
15
0 102030405060
35
30
40
OUTPUT FALL TIME
vs
CAPACITIVE LOAD
50
70 80 90 100
CL – Capacitive Load – pF
VDD = 3 V
Overdrive = 10 mV
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
t – Output Fall Time – nsf
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
0
100
0
0 100 200 300 400 500 600
3
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS OVERDRIVE VOLTAGES
700 800 9001000
tPHL – High-to-Low-Level Output
Propagation Delay Time – ns
VDD = 3 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
20 mV
10 mV
5 mV
– Differential
Input Voltage – mV – Output
Voltage – V
VO
VID
Figure 6
0
100
0
0 100 200 300 400 500 600
3
700 800 9001000
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS CAPACITIVE LOADS
tPHL – High-to-Low-Level Output
Propagation Delay Time – ns
VDD = 3 V
Overdrive = 10 mV
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
CL = 100 pF
CL = 15 pF
– Differential
Input Voltage – mV – Output
Voltage – V
VO
VID
CL = 50 pF
Figure 7
0
100
0
0 100 200 300 400 500 600
3
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS OVERDRIVE VOLTAGES
700 800 9001000
tPLH – Low-to-High-Level Output
Propagation Delay Time – ns
VDD = 3 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
20 mV
10 mV
5 mV
– Differential
Input Voltage – mV – Output
Voltage – V
VO
VID
Figure 8
0
100
0
0 100 200 300 400 500 600
3
700 800 9001000
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS CAPACITIVE LOADS
tPLH – Low-to-High-Level Output
Propagation Delay Time – ns
VDD = 3 V
Overdrive = 10 mV
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
CL = 100 pF
CL = 50 pF
CL = 15 pF
– Differential
Input Voltage – mV – Output
Voltage – V
VO
VID
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLV2354 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 9(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 9(b) for the VICR test rather than changing the input voltages to provide greater
accuracy.
+
–
5 V
Applied VIO
Limit VO
+
–
1 V
Applied VIO
Limit VO
– 4 V
(a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V
5.1 kΩ5.1 kΩ
Figure 9. Method for Verifying That Input Offset Voltage Is Within Specified Limits
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal but
opposite in polarity to the input offset voltage, the output changes states.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 10 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer , with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage dividers R9 and R10 provide a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter , the socket and board leakage
can be measured with no device in the socket. Subsequently , this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
–
+
DUT
VDD
+
–
–
+
–
+
C2
1 µF
R4
47 kΩ
R5
1.8 kΩ, 1%
C3
0.68 µF
U1c 1/4
TLV2354
U1b 1/4
TLV2354
U1a 1/4
TLV2354
R7
1 MΩ
R8
1.8 kΩ, 1%
R9
10 kΩ, 1%
R1
240 kΩ
R2
10 kΩ
C1
0.1 µF
R3
100 Ω
C4
0.1 µF
Integrator
R10
100 Ω, 1%
Buffer
Triangle
Generator
VIO
(×100)
R6
5.1 kΩ
Figure 10. Circuit for Input Offset Voltage Measurement
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Propagation delay time is defined as the interval between the application of an input step function and the instant when
the output crosses VO = 1 V with VDD = 3 V or when the output crosses VO = 1.4 V with VDD = 5 V . Propagation delay
time, low-to-high-level output, is measured from the leading edge of the input pulse, while propagation delay time,
high-to-low-level output, is measured from the trailing edge of the input pulse. Propagation-delay-time measurement
at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced
by the adjustment at the inverting input (as shown in Figure 11) so that the circuit is just at the transition point. Then
a low signal, for example a 105-mV or 5-mV overdrive, causes the output to change state.
+
–
DUT
VDD
CL
(see Note A)
Pulse
Generator
10 Ω
10 Turn
+ 1 V
– 1 V1 kΩ
50 Ω
1 µF
0.1 µF
TEST CIRCUIT
100 mV
Input
Overdrive
tPLH
100 mVInput
Overdrive
90%
10%
tf
tPHL
Low- to High-
Level Output High- to Low-
Level Output
VOLTAGE WAVEFORMS
5.1 kΩ
Input Offset Voltage
Compensation
Adjustment
90%
10%
tr
VO = 1 V With VDD = 3 V
or
VO = 1.4 V With VDD = 5 V
NOTE A: CL includes probe and jig capacitance.
Figure 11. Propagation Delay, Rise, and Fall Times Test Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9688201Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9688201Q2A
TLV2354
MFKB
5962-9688201QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9688201QC
A
TLV2354MJB
5962-9688201QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9688201QD
A
TLV2354MWB
TLV2354ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLV2354I
TLV2354IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLV2354I
TLV2354IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLV2354I
TLV2354IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLV2354I
TLV2354IN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLV2354IN
TLV2354INE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLV2354IN
TLV2354IPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY2354
TLV2354IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY2354
TLV2354IPWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85
TLV2354IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY2354
TLV2354IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY2354
TLV2354MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9688201Q2A
TLV2354
MFKB
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV2354MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9688201QC
A
TLV2354MJB
TLV2354MWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9688201QD
A
TLV2354MWB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2354IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2354IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2354IDR SOIC D 14 2500 367.0 367.0 38.0
TLV2354IPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
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