NCP1910B65DWR2G - ON Semiconductor L.L.C.

September, 2010 − Rev. 0

1Publication Order Number:

NCP1910/D

NCP1910

High Performance Combo

Controller for ATX Power

Supplies

Housed in a SO−24WB package, the NCP1910 combines a

state−of−the−art circuitry aimed to powering next generation of ATX

or flat TVs converters. With a 65 kHz Continuous Conduction Mode

Power Factor Controller and a LLC controller hosting a high−voltage

driver, the NCP1910 is ready to power 85+ types of offline power

supplies. To satisfy stringent efficiency considerations, the PFC circuit

implements an adjustable frequency fold back to reduce switching

losses as the load is going light. To cope with all the signal sequencing

required by the ATX and flat TVs specifications, the controller

includes several dedicated pins enabling handshake between the

secondary and the primary sides. These signals include a power−good

line but also a control pin which turns the controller on and off via an

opto coupler. Safety−wise, a second OVP input offers the necessary

redundancy in case the main feedback network would drift away.

Finally, a fast fault input immediately reacts in presence of an over

current condition by triggering an auto−recovery soft−start sequence.

Features

•Fixed−Frequency 65 kHz CCM Power Factor Controller

•Average Current−Mode Control for Low Line Distortion

•Dynamic Response Enhancer Reduces Bulk Undershoot

•Independent Over Voltage Protection Sensing Pin with Latch−off

Capability

•Adjustable Frequency Fold Back Improves Light Load Efficiency

•Adjustable Line Brown−out Protection with 50 ms

Delay to Help Meeting Hold−up Time Specifications

•Programmable Over current Threshold Leads to an

Optimized Sensing Resistor

•$1 A peak Current Drive Capability

•LLC Controller Operates from 25 kHz to 500 kHz

•On Board 600 V High−Voltage Drivers

•1 A/0.5 A Sink/Source Capability

•Minimum Frequency Precision Down to $3% Over

Temperature Range

•Internally Fixed Dead−Time Value of 300 ns

•Adjustable Soft−Start Sequence

•Fast Fault Input with Soft−Start Trigger for Immediate

Auto−Recovery Protection

•on/off Control Pin for Secondary−Based Remote

Control

•On−Board 5 V Reference Voltage for Precise

Thresholds/Hysteresis Adjustments

•Power Good Output Management Signal

•A Version with Dual Ground Pinout (No Skip),

B Version with Single Ground and Skip Operation for

the LLC Controller

•20 V Operation

•These are Pb−Free Devices

Typical Applications

•Multi Output ATX Power Supplies (A version)

•Flat TVs Power Supplies (B version)

MARKING DIAGRAM

SO−24WB Less Pin 21

DW SUFFIX

CASE 752AB

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See detailed ordering and shipping information in the package

dimensions section on page 36 of this data sheet.

ORDERING INFORMATION

NCP1910XXX

AWLYYWWG

XXXXX = Specific Device Code

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

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Figure 1. Pin Connections

GND/PGNDOVP2

DRVPG adj.

VCC

Vref

BO adj.

ON/OFF

BridgePG out

MURt

VbootSS

Skip/AGNDFB

CS/FFVCTRL

124

FoldLBO

CSVM

PIN DESCRIPTION

Pin N5Pin Name Function Pin Description

1 SS Soft−start A capacitor to ground sets the LLC soft−start duration

2 Rt The LLC feedback pin A resistive arrangement sets the maximum and minimum

switching frequencies with opto coupler−based feedback

capabilities.

3PG out The open−collector power good signal This pin is low when Vbulk is ok, opens when Vbulk passes

below a level adjusted by PGadj pin.

4 on/off Remote control When pulled low, the circuit operates: the PFC starts first and

once FB is in regulation, the LLC is authorized to work. When

left open, the controller is in idle mode.

5BO adj. Brown−out adjustment This pin sets the on and off levels for the PFC powering the

LLC converter

6 Vref The 5 V reference pin This pin delivers a stable voltage for threshold adjustments

7PG adj. The power good trip level From the Vref pin, a dc level sets the trip point for the PFC

bulk voltage at which the PG out signal is down.

8 OVP2 Redundant OVP A fully latched OVP monitoring the PFC bulk independently

from FB pin.

9 FB PFC feedback Monitors the boost bulk voltage and regulates it. It also serves

as a quick auto−recovery OVP

10 VCTRL PFC Error amplifier output PFC error amplifier compensation pin

11 VMPFC current amplifier output A resistor to ground sets the maximum power level

12 LBO PFC line input voltage sensing Line feed forward and PFC brown−out

13 Fold PFC fold back This pin selects the power level at which the frequency starts

to reduce gradually.

14 CS PFC current sense This pin senses the inductor current and also programs the

maximum sense voltage excursion

15 CS/FF Fast−fault input When pulled above 1 V, the LLC stops and re−starts via a full

soft−start sequence.

16 Skip/AGND Skip (B)/AGND (A) This pin is either used as the analog GND for the signal circuit

(A) or for skip operation (B).

17 GND/PGND GND (B)/PGND (A) The controller ground for the driving loop (A) or the lump

ground pin for all circuits (B)

18 DRV PFC drive signal The driving signal to the PFC power MOSFET

19 VCC The controller supply The power supply pin for the controller, 20 V max.

20 ML Lower−side MOSFET Drive signal for the lower side half−bridge MOSFET

22 Bridge Half−bridge This pin connects to the LLC half−bridge

23 MU Upper−side MOSFET Drive signal for the upper side half−bridge MOSFET

24 Vboot Bootstrapped Vcc The bootstrapped VCC for the floating driver

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*It is recommended to separate the traces of power ground and analog ground. The power ground (pin 17) for driving loop (PFC DRV and LLC ML) is connec-

ted to the PFC MOSFET directly. The analog ground for adjustment components is routed together first and then connected to the analog ground pin (pin

16) and the PFC sense resistor directly.

Figure 2. Typical Application Schematic in A Version

C14

Vout

R11

R30

U2B

R10

R18

R17

R16

Over Current

C15

R29

D12

D11

C13

R28

U100

C12

R22

R12

U2A

U3A

C10

0.1u

Bulk

12 V aux.

on/off

Vcc

R21

Vref

Power

Good

0.1u

R14R15

PG adj.

R13

BO level

R31

0.1

D7 C5

R19

D10

R20

10k

3.5M

1.5M

R32

3.6k

2.2M

3.5M

Input

Line

R23

120k

0.22u

R24

24k

1.5M

2.2M

R26

24k

R25

24k

R27

39k C11

R33

1.2k

Vref

PAD2

V33V32

C16

0.1u

R34

8.4k

C17

(*)

R35

300

C18

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*It is recommended to separate the traces of power ground and analog ground. The analog ground traces for adjustment components are routed together first and then

connected to the ground pin (pin 17). The power ground for driving loop (PFC DRV and LLC ML) is connected from ground pin (pin 17) to the PFC sense resistor directly

and as short as possible.

Figure 3. Typical Application Schematic in B Version

C14

L2 D6

Vout

R11

R30

U2B

R10

R18

R17

R16

Over Current C15

R29

D12

D11

C13

R28

U100

C12

R22

R12

U2A

U3A

C10

0.1u

Bulk

12 V aux.

on/off

Vcc

R21

Vref

Power

Good

0.1u

R14R15

PG adj.

R13

BO level

R31

0.1

D7 C5

R19

D10

R20

10k

3.5M

1.5M

R32

3.6k

2.2M

3.5M

Input

Line

R23

120k

0.22u

R24

24k

1.5M

2.2M

R26

24k

R25

24k

R27

39k C11

R33

1.2k

Vref

PAD2

V33V32

C16

0.1u

R34

8.4k

C17

(*)

R35

300

C18

R36

C19

skip

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−

VOVP

VUVP

105% Vpref

8% Vpref

PFC_OPL

−

OVP2

95% Vpref

−

VLD

Vpref

VCTRL

OTA

Vctrl(min)

Multiplier

LBO

VDD

VLBO^2

“1” BO NOTOK,

“0” BOK

A/B

ICS

Vctrl−Vctrl(min)

ICS x VLBO^2

−

ICS x VLBO > 275 uA

ICS > 200 uA

ICS

SUM 2

PFC_OL

−

“0” / “1”

Vpref / 10%Vpref

−

Vpref

PFC_OVP

PFC_OL

TSD

VLBO^2

VDD

IVLD

Dynamic

Response

Enhancer

“1” = UVP, “0” ok

Closed

if “1”

“1” OVP, “0” = ok

Vfold

ICS

Vdd

Oscillator section

ICt(min)

DRV

Vcc

foldback

PFC drive signal

Onoff

UVLO

Latch

RFB

pull down

“1” = OPL

“1” = OCP

PFC_UVP

The “PFC_OK” toggles high when:

− VLD is low

− PFC issues a driving pulse

The “PFC_OK” toggles low when:

− Vctrl stays out of window [Vctrl,min to

Vctrl,max] > 1 sec

− at this point, the latch is reset and the

“PFC_OK” output goes low.

“1” = below 5% reg

“0” ok

Auto−recovery internal OVP

−

VOVP2

107% Vpref “1” OVP2, “0” = ok

Latched adjustable OVP2

PFC_OVP2

latched

Vctrl

−

Vctrl(min) − 0.1 V

Vctrl

−

1 sec

delay

If PFC issues an abnormal

situation, then latch off

Grand Reset

PFC_OK

Grand Reset

PFC_SKIP

(0.6 V clamp

voltage is

activated.)

VLBO PFC_BO

−

ILBO

VLBOT

20 us filter

Latch

PFC_BO

PFC_SKIP

−

Vctrl(max)

PFCflag

ICt

Vfold(max)

Ict(fold)

PFC_OVP

Grand Reset

PFC_OCP

PFC_OPL

Grand

Reset

“1” open

“0” close

PFC_abnormal

latched

PFC_BO

−

“1” = FB > Vpref

Grand Reset

PFC_BO

Figure 4. Internal PFC Block Diagram

ICS VLBO2

4(Vctrl *Vctrl(min))

BO delay

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Vref

PG adj

PG out

CS/FF

on/off

BO adj

Vcc

management

UVLO

Hi side

Level

shifter

Vrt

Clk

Vboot

Mupper

Bridge

Vcc

Mlower

GND_LLC

delay

Dead time

PFC_FB

"1" BONOT OK

20 ms delay

tdel1

"1" enables LLC

"0" LLC is locked

Grand

Reset

SS_RST

VCS1

VCS2

UVLO

Vdd

Vref

LLC_BO

Grand

Reset

Grand Reset

Onoff

UVLO

PFC_BO

Grand Reset

Grand

Reset

Latch

Vdd

Rpull up

on_off

on/off

"1" controller is off

"0" controller is on

GND

Prop. delay

matching

PFC_UVP

PFC_OK

"1" is ok

"0" notok

5 ms delay

tdel2

"1" after reset

"0" when PG out

drops after 5 ms

PFC_OVP2

LLC_BO

Latch

Pulse

Trigger

CLK

Skip/GND_PFC

Vskip

Skip: B version only

Thermal

Shut Down TSD

TSD

"1" TSD is on

"0" TSD is off

Grand

Reset

"1" PGNOT OK

tBOK

tBONOTOK

LLC_BO

LLC_PG

Grand Reset

Figure 5. Internal LLC Block Diagram

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MAXIMUM RATINGS TABLE

Symbol Rating Value Unit

VBridge Continuous High Voltage bridge pin, pin 22 −1 to 600 V

VBOOT–VBridge Floating supply voltage, pin 24−22 −0.3 to 20 V

VMU, VDRV High side output voltage, pin 23 VBRIDGE − 0.3 to

VBOOT + 0.3

VML Low side output voltage, pin 18, 20 −0.3 to VCC + 0.3 V

dVBridge/dt Allowable output slew rate on the Bridge pin, pin 22 50 V/ns

VCC Power Supply voltage, pin 19 20 V

Pin voltage, all pins (except pin 2, 6, 18 − 24, GND) −0.3 to 10 V

RθJA Thermal Resistance Junction−to−Air

50 mm2, 1 oz

650 mm2, 1 oz

°C/W

Storage Temperature Range −60 to + 150 °C

ESD Capability, Human Body Model (All pins except VCC and HV) 2 kV

ESD Capability, Machine Model 200 V

VCC Power Supply voltage, pin 19 20 V

Pin voltage, all pins (except pin 2, 6, 18 ~ 24, GND) −0.3 to 10 V

VRt Rt pin voltage −0.3 to 5 V

Vref_out Vref pin voltage −0.3 to 7 V

IMAX Pin current on pin 10, 12, and 13 0.5 mA

IPGout Pin current on pin 3 5 mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device(s) contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC Standard JESD22−A114E

Machine Model 200 V per JEDEC Standard JESD22−A115−A

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC

= 12 V unless otherwise noted)

Symbol Rating Pin Min Typ Max Unit

COMMON TO BOTH CONTROLLERS

SUPPLY SECTION

VCC(on) Turn−on threshold level, VCC going up 19 9.4 10.4 11.4 V

VCC(min) Minimum operating voltage after turn−on 19 8 9 10 V

VCC(Hys) Hysteresis between VCC(on) and VCC(min) 19 1.2 − − V

VBoot(on) Startup voltage on the floating section 24,22 7.8 8.8 9.8 V

VBoot(min) Cutoff voltage on the floating section 24,22 7 8 9 V

Istartup Startup current, VCC < VCC(on) 19 − − 100 mA

ICC1 PFC consumption alone, DRV pin unloaded, on/off pin grounded,

LLC off (PFC is 65 kHz)

19 −5.1 6.4 mA

ICC2 PFC consumption, DRV pin loaded by 1 nF, on/off pin grounded, LLC

off (PFC is 65 kHz)

19 −5.9 7.4 mA

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC

= 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

COMMON TO BOTH CONTROLLERS

SUPPLY SECTION

ICC4 IC consumption, both PFC and LLC loaded in no load conditions

(PFC is 65 kHz and Rt = 70 kW (LLC is 25 kHz))

19 −5.9 7.2 mA

ICC5 IC consumption, both PFC and LLC loaded 1 nF load conditions

(PFC is 65 kHz and Rt = 70 kW (LLC is 25 kHz))

19 −6.9 8.6 mA

ICC6 IC consumption in fault mode from Vboot (drivers disabled, Vboot >

Vboot(min))

19 −64 300 mA

ICC7 IC consumption in OFF mode from VCC (on/off pin is open) 19 − − 950 mA

REFERENCE VOLTAGE

Vref−out Reference voltage for external threshold setting @ Iout = 5 mA 6 4.75 5 5.25 V

Vref−out Reference voltage for external threshold setting @ Iout = 5 mA – TJ =

25°C

6 4.9 5 5.1 V

VrefLineReg Vcc rejection capability, Iout = 5 mA − DVCC = 1 V – TJ = 25°C6−0.01 5 mV

VrefLoadReg Reference variation with load changes, 1 mA < Iref < 5 mA – TJ =

25°C

6−1.6 7 mV

Iref−out Maximum output current capability 6 5 − − mA

NOTE: Maximum capacitance directly connected to VREF pin must be under 100 nF.

DELAY

tDEL1 Turn−on LLC delay after PFC OK signal is asserted −10 20 30 ms

tDEL2 Turn−off LLC after power good pin goes low (Note 3) −2 5 8 ms

PROTECTIONS

RPull−up on/off pin pull−up resistor 4−5−kW

ton/off Propagation delay from on to off (ML & MU are off) (Note 4) 4−−1ms

Von Low level input voltage on on/off pin (NCP1910 is enabled) 4−−1 V

Voff High level input voltage on on/off pin (NCP1910 is disabled) 4 3 − − V

Vop Open voltage on on/off pin 4−7−V

IPG Maximum Power good pin sink current capability 3 5 − − mA

VPG Power good saturation voltage for IPG = 5 mA 3− − 350 mV

IPGadj Input bias current, PGadj pin 7−10 −nA

VPGadjH PG comparator hysteresis 7−100 −mV

TSD Temperature shutdown (Note 4) −140 − − °C

TSDhyste Temperature Hysteresis Shutdown − − 30 −°C

POWER FACTOR CORRECTION

GATE DRIVE SECTION

RPOH Source Resistance @ IDRV = −100 mA 18 −9 20 W

RPOL Sink Resistance @ IDRV = 100 mA 18 −6.6 18 W

tPr Gate Drive Voltage Rise Time from 1.5 V to 10.5 V (CL = 1 nF) 18 −60 −ns

tPf Gate Drive Voltage Fall Time from 10.5 V to 1.5 V (CL = 1 nF) 18 −40 −ns

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC

= 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

POWER FACTOR CORRECTION

REGULATION BLOCK

VPREF PFC Voltage reference −2.425 2.5 2.575 V

IEA Error Amplifier Current Capability 10 −$30 −mA

GEA Error Amplifier Gain −100 200 300 mS

IBBias Current @ VFB = VPREF 9 0 −0.3 mA

VCTRL

VCTRL(max)

VCTRL(min)

DVCTRL

Maximum Control Voltage @ VFB = 2 V

Minimum Control Voltage @ VFB = 3 V

DVCTRL = VCTRL(max)−VCTRL(min)

−

2.7

3.6

0.6

−

3.3

VOUTL / VPREF Ratio (VOUT Low Detect Threshold / VPREF) (Note 4) −94 95 96 %

HOUTL / VPREF Ratio (VOUT Low Detect Hysteresis / VPREF)− − 0.5 −%

IVLD + IEA Source Current when (VOUT Low Detect) is activated 10 190 230 260 mA

CURRENT SENSE

VSCurrent Sense Pin Offset Voltage, (ICS = 100 mA) 14 −10 −mV

ICS(OCP) Over−Current Protection Threshold 14 185 200 215 mA

POWER LIMIT

ICSx VLBO Over Power Limitation Threshold −215 275 335 mVA

ICS(OPL1)

ICS(OPL2)

Over−Power Current Threshold (VLBO = 1.8 V, VM = 0 V)

Over−Power Current Threshold (VLBO = 3.6 V, VM = 0 V)

−119

153

187

PULSE WIDTH MODULATION

FPSW PFC Switching Frequency 18 58 65 72 kHz

FPSW(fold) Minimum Switching Frequency (Vfold = 1.5 V, VCTRL = VCTRL(min) +

0.1 V)

18 34 39 43 kHz

DCPmax Maximum PFC Duty Cycle 18 −97 −%

DCPmin Minimum PFC Duty Cycle 18 −−0 %

VCTRL(fold) VCTRL pin voltage to start frequency foldback (Vfold = 1.5 V) 10 1.8 2 2.2 V

VCTRL(foldend) VCTRL pin voltage as frequency foldback reducing to the minimum

(FPSW = FPSW(fold), Vfold = 1.5 V)

10 1.4 1.6 1.8 V

Vfold(max) Maximum internal fold voltage (Note 4) −1.97 2 2.03 V

LINE BROWN−OUT DETECTION

VLBOT Line Brown−Out Voltage Threshold 12 0.96 1.00 1.04 V

ILBOH Line Brown−Out Hysteresis Current Source 12 6 7 8 mA

tLBO(blank) Line Brown−Out Blanking Time −25 50 75 ms

tLBO(window) Line Brown−Out Monitoring Window (Note 4) −25 50 75 ms

VLBO(clamp) LBO Pin clamped voltage if VBO < VLBOT during tLBO(BLANK) (ILBO =

100 mA)

12 −980 −mV

VLBOH Hysteresis (VLBOT – VLBO(clamp)) (Note 4) 12 10 35 60 mV

ILBO(clamp) Current Capability of LBO 12 100 − − mA

VLBO(PNP) LBO pin voltage when clamped by the PNP Transistor (ILBO =

100 mA)

12 0.4 0.7 0.9 V

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC

= 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

POWER FACTOR CORRECTION

LINE BROWN−OUT DETECTION

VLBO(PD) Pull Down VLBO Threshold 12 1.8 2 2.2 V

tLBO(Pdlimit) Pull Down VLBO Time Limitation −4.5 5 6.1 ms

tPFCflag Time Delay to Confirm that VCTRL is the maximum to Pull down VLBO −2.5 5 7.5 ms

tLBO(Pdblank) Pull Down VLBO Blanking Time −55 77 90 ms

CURRENT MODULATION

IM1

IM2

Multiplier Output Current (VCTRL =VCTRL(max) – 0.2 V , VLBO = 3.6 V,

ICS = 50 mA)

Multiplier Output Current (VCTRL =VCTRL(max) – 0.2 V , VLBO = 1.2 V,

ICS = 150 mA)

24.5

OVER−VOLTAGE PROTECTION

VOVP1 Internal Auto Recovery Over Voltage Threshold 9 2.536 2.615 2.694 V

VOVP1H Hysteresis of Internal Auto Recovery Over Voltage Threshold

(Note 4)

9−44 60 mV

tOVP1 Propagation Delay (VFB = 108% VPREF) to Drive Low 9, 18 −500 −ns

VOVP2 External Latched Over Voltage Threshold 8 2.595 2.675 2.755 V

KOVPH The difference between VOVP2 and VOVP1 over VPREF ((VOVP2 −

VOVP1)/VPREF)

− − 2−%

tDELOVP2 External Latched OVP Integrating Filter Time Constant − − 20 −ms

Ib,OVP2 Input bias current, OVP2 8−10 −nA

UNDER−VOLTAGE PROTECTION

VUVP(on)/VPREF UVP Activate Threshold Ratio 9 4 8 12 %

VUVP(off)/VPREF UVP Deactivate Threshold Ratio 9 6 12 18 %

VUVP(H) UVP Lockout Hysteresis 9−4−%

tUVP Propagation Delay (VFB < 8 % VPREF) to Drive Low 9 − 18 −7−ms

PFC ABNORMAL

tPFCabnormal PFC Abnormal Delay Time (VCTRL = VCTRL(max) or VCTRL =

VCTRL(min) – 0.1 V)

−1 1.5 2.1 sec

LLC CONTROL SECTION

OSCILLATOR

FLsw,min Minimum switching frequency, Rt = 70 kW on Rt pin 2 24.25 25 25.75 kHz

FLsw switching frequency, DTL = 300 ns, Rt = 7 kW on Rt pin 2 208 245 282 kHz

FLsw,max Maximum switching frequency, DTL = 300 ns, Rt = 3.5 kW on Rt pin 2 424 500 575 kHz

DCLOperating Duty−Cycle symmetry 23, 20 48 50 52 %

VrefRt Reference voltage for oscillator charging current generation 2 3.33 3.5 3.67 V

RSS Discharge switch resistance 1−70 −W

SSRST Soft−start reset voltage 1−200 −mV

VSkip Skip cycle threshold, B version only 16 350 400 450 mV

Vskip,hyste Hysteresis level on skip cycle comparator, B version only 16 −50 −mV

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC

= 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

LLC CONTROL SECTION

DRIVE OUTPUT

TLr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 23, 20 −40 −ns

TLf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 23, 20 −20 −ns

RLOH Source resistance 23, 20 −12 26 W

RLOL Sink resistance 23, 20 −511 W

DTLDead time, measured between 50% of the rise and fall edge 23, 20 268 327 386 ns

IHV,leak Leakage current on high voltage pins to GND (600 Vdc) 22, 23, 24 −−5mA

PROTECTIONS

IBOadj Input bias current, BOadj pin 5−15 −nA

VBOadjH BO comparator hysteresis 5−100 −mV

tBOK BO comparator Integrating Filter Time Constant from High to Low 5−150 −ms

tBONOTOK BO comparator Integrating Filter Time Constant from Low to High 5−20 −ms

VCS1 Current−sense pin level that resets the soft−start capacitor 15 0.95 1 1.05 V

VCS2 Current−sense pin level that permanently latches off the circuit 15 1.42 1.5 1.58 V

tCS Propagation delay from VCS1/2 activation to respective action 15 − − 500 ns

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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TYPICAL CHARACTERISTICS

8.5

9.5

10.5

−50 −25 0 25 50 75 100 125

VCC(on) AND VCC(min) (V)

Figure 6. VCC(on) and VCC(min) vs. Temperature

TEMPERATURE (°C)

VCC(on)

VCC(min)

7.5

8.5

9.5

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

Vboot(on) AND Vboot(min) (V)

Figure 7. Vboot(on) and Vboot(min) vs.

Temperature

Vboot(on)

Vboot(min)

100

−50 −25 0 25 50 75 100 125

Istartup (mA)

TEMPERATURE (°C)

Figure 8. Istartup vs. Temperature

550

650

750

850

950

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

Figure 9. ICC7 vs. Temperature

ICC7 (mA)

4.75

4.85

4.95

5.05

5.15

5.25

−50 −25 0 25 50 75 100 125

Vref−out (V)

Figure 10. Vref-out vs. Temperature

TEMPERATURE (°C)

4.987

4.988

4.989

4.99

0123456

Vref−out @ 25°C (V)

TEMPERATURE (°C)

Figure 11. Vref-out @ 255C vs. Iref-out

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TYPICAL CHARACTERISTICS

1.5

2.5

−50 −25 0 25 50 75 100 125

Von AND Voff (V)

TEMPERATURE (°C)

Figure 12. Von and Voff vs. Temperature

Von

Voff

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

RPOH AND RPOL (W)

Figure 13. RPOH and RPOL vs. Temperature

RPOH

RPOL

2.4

2.5

2.6

2.7

2.8

−50 −25 0 25 50 75 100 125

VPREF

, VOVP1, AND VOVP2 (V)

TEMPERATURE (°C)

Figure 14. VPREF

, VOVP1, and VOVP2 vs.

Temperature

VOVP2

VOVP1

VPREF

−40

−35

−30

−25

−20

−50 −25 0 25 50 75 100 125

IEA(source) (mA)

TEMPERATURE (°C)

Figure 15. IEA(source) vs. Temperature

−50 −25 0 25 50 75 100 125

IEA(sink) (mA)

TEMPERATURE (°C)

Figure 16. IEA(sink) vs. Temperature

100

150

200

250

300

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

GEA (mS)

Figure 17. GEA vs. Temperature

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TYPICAL CHARACTERISTICS

3.3

3.4

3.5

3.6

3.7

3.8

3.9

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VCTR(max) (V)

Figure 18. VCTRL(max) vs. Temperature

2.7

2.8

2.9

3.1

3.2

3.3

−50 −25 0 25 50 75 100 125

DVCTR (V)

TEMPERATURE (°C)

Figure 19. DVCTRL vs. Temperature

190

200

210

220

230

240

250

260

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

IVLD + IEA (mA)

Figure 20. IVLD+IEA vs. Temperature

185

190

195

200

205

210

215

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

ICS(OCP) (mA)

Figure 21. ICS(OCP) vs. Temperature

120

130

140

150

160

170

180

190

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

ICS(OPL1) (mA)

Figure 22. ICS(OPL1) vs. Temperature

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

ICS(OPL2) (mA)

Figure 23. ICS(OPL2) vs. Temperature

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TYPICAL CHARACTERISTICS

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

FPSW (kHz)

Figure 24. FPSW vs. Temperature

−50 −25 0 25 50 75 100 125

FPSW(fold) (kHz)

TEMPERATURE (°C)

Figure 25. FPSW(fold) vs. Temperature

0.96

0.98

1.02

1.04

−50 −25 0 25 50 75 100 125

VLBOT (V)

TEMPERATURE (°C)

Figure 26. VLBOT vs. Temperature

6.5

7.5

−50 −25 0 25 50 75 100 125

ILBOH (mA)

TEMPERATURE (°C)

Figure 27. ILBOH vs. Temperature

−50 −25 0 25 50 75 100 125

VUV(on) / VPREF AND VUP(off) / VPREF (%)

TEMPERATURE (°C)

Figure 28. VUVP(on)/VPREF and VUVP(off)/VPREF

vs. Temperature

VUVP(on) / VPREF

VUVP(off) / VPREF

24.5

25.5

−50 −25 0 25 50 75 100 125

FLSW,min (kHz)

TEMPERATURE (°C)

Figure 29. FLsw,min vs. Temperature

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TYPICAL CHARACTERISTICS

210

220

230

240

250

260

270

280

−50 −25 0 25 50 75 100 125

FLSW (kHz)

TEMPERATURE (°C)

Figure 30. FLsw vs. Temperature

425

450

475

500

525

−50 −25 0 25 50 75 100 125

FLSW,max (kHz)

TEMPERATURE (°C)

Figure 31. FLsw,max vs. Temperature

−50 −25 0 25 50 75 100 125

3.3

3.4

3.5

3.6

3.7

VrefRT (V)

TEMPERATURE (°C)

Figure 32. VrefRt vs. Temperature

100

150

200

250

300

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

SSRST (mV)

Figure 33. SSRST vs. Temperature

350

375

400

425

450

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

Vskip (mV)

Figure 34. Vskip vs. Temperature

−50 −25 0 25 50 75 100 125

RLOH,ML AND RLOL,ML (W)

TEMPERATURE (°C)

Figure 35. RLOH,ML and RLOL,ML vs.

Temperature

RLOL,ML

RLOH,ML

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TYPICAL CHARACTERISTICS

−50 −25 0 25 50 75 100 125

RLOH,MU AND RLOL,MU (W)

TEMPERATURE (°C)

RLOL,MU

RLOH,MU

Figure 36. RLOH,MU and RLOL,MU vs.

Temperature

300

310

320

330

340

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

DTL (ns)

Figure 37. DTL vs. Temperature

0.95

0.975

1.025

1.05

−50 −25 0 25 50 75 100 125

VCS1 (V)

TEMPERATURE (°C)

Figure 38. VCS1 vs. Temperature

1.4

1.45

1.5

1.55

1.6

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VCS2 (V)

Figure 39. VCS2 vs. Temperature

100

120

140

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

tCS (ns)

Figure 40. tCS vs. Temperature

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APPLICATION INFORMATION

The NCP1910 represents a new generation of control

circuit, associating two individual cores performing the

functions of Continuous Conduction Mode (CCM) Power

Factor Correction (PFC) and LLC resonant control. These

cores interact together and implement handshake functions

in normal operating conditions but also when a fault appears.

Based on the ON Semiconductor proprietary high−voltage

technology, the LLC section can drive the high−side

MOSFET of the LLC half−bridge without the need of a

gate−drive transformer.

Power Factor Correction

•Compactness and Flexibility: the NCP1910 requires a

minimum of external components to perform a CCM

PFC operation. In particular, the circuit scheme

simplifies the PFC stage design. In addition, the circuit

offers some functions like the line brown−out detection

or true power limiting capability that enable the

optimization of the PFC design.

•Low Consumption and Shutdown Capability: the

NCP1910 is optimized to consume a small current in all

operation modes. The consumed current is particularly

reduced during the start−up phase and in shutdown

mode so that the power losses are minimized when the

circuit is disabled. This feature helps meet stringent

stand−by low power specifications. Grounding the

Feed−back pin can force the circuit to enter standby but

the on/off pin can also serve this purpose.

•Maximum Current Limit: the circuit permanently

senses the inductor current and immediately turns off

the power switch if it is higher than the set current

limit. The NCP1910 also prevents any turn on of the

power switch as long as the inductor current is not

below its maximum permissible level. This feature

protects the MOSFET from possible excessive stress

that could result from the switching of a current higher

than the one the power switch is dimensioned for. In

particular, this scheme effectively protects the PFC

stage during the start−up phase when large in−rush

currents charge the bulk capacitor.

•Under−Voltage Protection for Open Loop

Protection: the circuit detects when the feed−back

voltage goes below than about 8% of the regulation

level. In this case, the circuit turns off and its

consumption drops to a very low value. This feature

protects the PFC stage from starting operation in case

of low ac line conditions or in case of a failure in the

feed−back network (i.e. bad connection). In case the

UVP circuitry is activated, the Power Good signal is

disabled and the LLC circuit stops immediately.

•Fast Transient Response: given the low bandwidth of

the regulation block, the output voltage of PFC stages

may exhibit excessive over or under−shoots because of

abrupt load or input voltage variations (e.g. at start up).

If the bulk voltage is too far from the regulation level:

♦Over−Voltage Protection: NCP1910 turns off the

power switch as soon as Vbulk exceeds the OVP

threshold (105% of the regulation level). This is an

auto−recovery function.

♦Dynamic Response Enhancer: NCP1910

drastically speeds up the regulation loop by its

internal 200 mA current source, activated when the

bulk voltage drops below 95% of its regulation level.

•Line Brown−Out Detection: the circuit detects low ac

line conditions and disables the PFC stage in this case.

This protection mainly protects the power switch from

the excessive stress that could damage it in such

conditions.

•Over−Power Limitation: the NCP1910 computes the

maximum permissible current in dependence of the

average input voltage measured by the brown−out

block. It is the second OCP with a threshold that is line

dependent. When the circuit detects an excessive power

transfer, it resets the driver output immediately.

•Redundant Over−Voltage Protection: As a redundant

safety feature, the NCP1910 offers a second latched

OVP whose input is available on OVP2 pin. If the

voltage on this pin is above the maximum allowable

voltage, the PFC and the LCC are latched off.

•PFC Abnormal Protection: When PFC faces an

abnormal situation so that the bulk voltage is under

regulation longer than the allowable timing, the PFC

and LLC are latched off.

•Frequency Foldback: in light output loading

conditions, the user has the ability to program a point

on the VCTRL pin where the oscillator frequency is

gradually reduced. This helps to maintain an adequate

efficiency on the PFC power stage alone.

•Soft−Start: to offer a clean start−up sequence and limit

both the stress on the power MOSFET and the bulk

voltage overshoot, a 30 mA current source charges the

compensation network installed on VCTRL pin and

makes VCTRL raise gradually.

•Output Stage Totem Pole: the NCP1910 incorporates

a $1.0 A gate driver to efficiently drive TO220 or

TO247 power MOSFETs.

LLC Controller

•Wide frequency operation: the part can operate to a

frequency up to 500 kHz by connecting a resistive

network from Rt pin to ground. One resistor sets the

maximum switching frequency whereas a second

resistor set the minimum frequency.

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•On board dead time: to eliminate the shoot−through

on the half−bridge leg, a dead time is included in the

controller (see DTL parameter).

•Soft−start: a dedicated pin discharges a capacitor to

ground upon start−up to offer a smooth output voltage

ramp up. The start−up frequency is the maximum set by

the resistor connected between Rt pin and SS pin. The

capacitor connected from Rt pin to ground fixes the soft

start duration. In fault mode, when the voltage on

CS/FF pin exceeds a typical value of 1 V, the soft−start

pin is immediately discharged and a re−start at high

frequency occurs.

•Skip cycle operation: to avoid any frequency runaway

in light conditions but also to improve the standby

power consumption, the NCP1910B welcomes a skip

input (Skip pin) which permanently observes the

opto−coupler collector. If this pin senses a low voltage,

it cuts the LLC output pulses until the collector goes up

again. The NCP1910A does not offer the skip

capability and routes the analog ground on pin 16

instead.

•High−voltage drivers: capitalizing on

ON Semiconductor technology, the LLC controller

includes a high−voltage section allowing a direct

connection to the high−voltage rail. The MOSFET leg

can therefore be directly driven without using a

gate−drive transformer.

•Fault protection: as explained in the above lines, the

CS/FF pin combines a two−level protection circuit. If

the level crosses the first level (1 V), the LLC converter

immediately increases its switching frequency to the

maximum set by the external resistive divider

connected on Rt pin. This is an auto−recovery

protection mode. In case the fault is more severe, the

signal on the CS/FF pin crosses the second threshold

(1.5 V) and latches off the whole combo controller.

Reset occurs via an UVLO detection on VCC, a reset on

the on/off pin or a brown−out detection on the PFC

stage. This latter confirms that the user has unplugged

and re−plugged the power supply.

Combo Management

•Start−up delay: the PFC start−up sequence often

generates an output overshoot followed by damped

oscillations. To make sure the PFC output voltage is

fully stabilized before starting the LLC converter, a

20 ms delay is inserted after the internal PFC_ok signal

is asserted. This delay is always reset when the combo

is started from a Vcc ULVO, line brown−out condition

or via the on/off pin.

•Power good signal: the power good signal (PG) is

intended to instruct the downstream circuitry installed

on the isolated secondary side that the combo is

working. Once the PFC has started, an internal

“PFC_OK” signal is asserted. 20 ms later, the PG pin is

brought low. This signal can now disappear in two

cases: the bulk voltage decreases to an abnormal level,

programmed by a reference voltage imposed on PGadj

pin. This level is usually above the LLC turn−off

voltage, programmed by BOadj pin. Therefore, in a

normal turn−off sequence, PG first drops and signals

the secondary side that it must be prepared for

shutdown. The second event that can drop the PG

signal is when the PFC experiences a fault: broken

feedback path, severe overload. In this case, the PG

signal is immediately asserted high and a 5 ms timer

starts. Once this timer is elapsed, the LLC converter can

be safely halted.

•Latched event: in the event of a severe operating

condition, the PFC can be latched (OVP2 pin) and/or

the LLC controller also (CS/FF pin). In either case, the

whole combo controller is locked and can only be reset

via a VCC UVLO, line brown−out or a level transition

on pin on/off.

•Thermal Shutdown: an internal thermal circuitry

disables the circuit gate drive and then keeps the power

switch off when the junction temperature exceeds

140°C typically. The circuit resumes operation once the

temperature drops below about 110°C (30°C

hysteresis).

Principle of NCP1910 Scheme

PFC Section

A CCM PFC boost converter is shown in Figure 41. The

input voltage is a rectified 50 Hz or 60 Hz sinusoidal signal.

The MOSFET is switching at a high frequency (typically

65 kHz in NCP1910) so that the inductor current IL basically

consists of high and low−frequency components.

Filter capacitor Cin is an essential and very small value

capacitor in order to eliminate the high−frequency

component of the inductor IL. This filter capacitor cannot be

too bulky because it can pollute the power factor by

distorting the rectified sinusoidal input voltage.

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Cin

RSENSE

LIL

Cbulk

Vin

Iin Bulk voltage (Vbulk)

Figure 41. CCM PFC Boost Converter

PFC Methodology

The NCP1910 uses a proprietary PFC methodology

particularly designed for CCM operation. The PFC

methodology is described in this section.

Figure 42. Inductor Current in CCM

As shown in Figure 42, the inductor current IL in a

switching period T includes a charging phase for duration t1

and a discharging phase for duration t2. The voltage

conversion ratio is obtained in Equation 1.

Vbulk

Vin

+t1)t2

T*t1(eq. 1)

Vin +T*t1

TVbulk

Where:

♦Vbulk is the output voltage of PFC stage,

♦Vin is the rectified input voltage,

♦T is the switching period,

♦t1 is the MOSFET on time, and

♦t2 is the MOSFET off time.

The input filter capacitor Cin and the front−ended EMI

filter absorbs the high−frequency component of inductor

current IL. It makes the input current Iin a low−frequency

signal only of the inductor current.

Iin +IL−50 (eq. 2)

Where:

♦Iin is the input AC current.

♦IL is the inductor current.

♦IL−50 supposes a 50 Hz operation. The suffix 50

means it is with a 50 Hz bandwidth of the original

IL.

From Equations 1 and 2, the input impedance Zin is

formulated.

Zin +Vin

Iin

+T*t1

Vbulk

IL*50

(eq. 3)

where: Zin is input impedance.

Power factor is corrected when the input impedance Zin in

Equation 3 is constant or varies slowly in the 50 or 60 Hz

bandwidth.

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Figure 43. PFC Duty Modulation and Timing Diagram

VPREF

The PFC modulation and timing diagram is shown in

Figure 43. The MOSFET on time t1 is generated by the

intersection of reference voltage VPREF and ramp voltage

Vramp. A relationship in Equation 4 is obtained.

Vramp +VM)

Icht1

Cramp

+VPREF (eq. 4)

Where:

♦Vramp is the internal ramp voltage, the positive input

of the PFC modulation comparator,

♦VM is the multiplier voltage appearing on VM pin,

♦Ich is the internal charging current,

♦Cramp is the internal ramp capacitor, and

♦VPREF is the internal reference voltage, the negative

input of the PFC modulation comparator.

Ich, Cramp, and VPREF also act as the ramp signal of

switching frequency. Hence the charging current Ich is

specially designed as in Equation 5. The multiplier voltage

VM is therefore expressed in terms of t1 in Equation 6.

Ich +

CrampVPREF

T(eq. 5)

VM+VPREF *t1

Cramp

CrampVPREF

T+VPREF

T*t1

T(eq. 6)

From Equation 3 and Equation 6, the input impedance Zin

is re−formulated in Equation 7.

Zin +VM

VPREF

Vbulk

IL−50

(eq. 7)

Because VPREF and Vbulk are roughly constant versus

time, the multiplier voltage VM is designed to be

proportional to the IL−50 in order to have a constant Zin for

PFC purpose. It is illustrated in Figure 44.

Figure 44. Multiplier Voltage Timing Diagram

It can be seen in the timing diagram in Figure 43 that VM

originally consists of a switching frequency ripple coming

from the inductor current IL. The duty ratio can be

inaccurately generated due to this ripple. This modulation is

the so−called “peak current mode”. Hence, an external

capacitor CM connected to the multiplier voltage VM pin is

essential to bypass the high−frequency component of VM.

The modulation becomes the so−called “average current

mode” with a better accuracy for PFC.

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PFC Duty

Modulation

RMCM

Figure 45. The Multiplier Voltage Pin Configuration

VM+

RMICSǒVLBOǓ2

4ǒVCTRL *VCTRLǒminǓǓ

The multiplier voltage VM is generated according to

Equation 8.

VM+

RMICSǒVLBOǓ2

4ǒVCTRL *VCTRL(min)Ǔ(eq. 8)

Where:

♦RM is the external multiplier resistor connected to

VM pin, which is constant.

♦VLBO is the input voltage signal appearing on the

LBO pin, which is proportional to the rms input

voltage,

♦ICS is the sense current proportional to the inductor

current IL as described in Equation 13.

♦VCTRL is the control voltage signal, the output

voltage of Operational Trans−conductance Amplifier

(OTA), as described in Equation 17.

♦VCTRL(min) is not only the minimum operating

voltage of VCTRL but also the offset voltage for the

PFC current modulation.

RM directly limits the maximum input power capability.

Also, due to the Vin2 feed−forward feature, where the VLBO

is squared, the transfer function and the power delivery is

independent from the ac line level. The relationship between

VCTRL and power delivery will be depicted later on.

Line Brown−Out Protection

EMI

Filter

Ac line

reset reset

reset

Vdd

Vin

RLBOU

RLBOL

Cin

RSENSE CLBO

PFC_BO

VLBOT

ILBOH

LBO comp.

VLBOcomp

tLBO(blank) tLBO(window)

VLBO(clamp)

LBO

Figure 46. The Line Brown−Out Configuration

As shown in Figure 46, the Line Brown−Out pin

(represented LBO pin) as receives a portion of the input

voltage (Vin). As Vin is a rectified sinusoid, a capacitor must

integrate the ac line ripple so that a voltage proportional to

the average value of Vin is applied to the brown−out pin.

The main function of the LBO block is to detect too low

input voltage conditions. A 7 mA current source lowers the

LBO pin voltage when a brown−out condition is detected.

This is for hysteresis purpose as required by this function.

In nominal operation, the voltage applied to LBO pin must

be above the internal reference voltage, VLBOT (1 V

typically). In this case, the output of the LBO comparator

VLBOcomp is low.

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Conversely, if VLBO goes below 1 V, VLBOcomp turns high

and a 980 mV voltage source, VLBO(clamp), is connected to

the LBO pin to maintain the pin level near 1 V. Then a 50 ms

blanking delay, tLBO(blank), is activated during which no

fault is detected. The main goal of the 50 ms lag is to help

meet the hold−up requirements. In case of a short mains

interruption, no fault is detected and hence, both PFC and

LLC keep operating. In addition, LBO pin being kept at

980 mV, there is almost no extra delay between the line

recovery and the occurrence of a proper voltage applied to

LBO pin, that otherwise would exist because of the large

capacitor typically placed between LBO pin and ground to

filter the input voltage ripple. As a result, the NCP1910

effectively “blanks” any mains interruption that is shorter

than 25 ms (minimum guaranteed value of the 50 ms timer).

At the end of this blanking delay (tLBO(blank)), another

timer is activated that sets a 50 ms window during which a

fault can be detected. This is the role of the tLBO(window) in

Figure 46:

•If VLBOcomp is high during the second 50 ms delay

(tLBO(window)), a line brown−out condition is confirmed

and PFC_BO signal is asserted high.

•If VLBOcomp remains low for the duration of the

tLBO(window), no fault is detected.

When the PFC_BO signal is high:

•The PFC driver is disabled, and the VCTRL pin is

grounded to recover operation with a soft−start when

the fault has gone.

•The VLBO(clamp) voltage source is removed from LBO

pin.

•The ILBOH current source (7 mA typically) is enabled

that lowers the LBO pin voltage for hysteresis purpose.

At startup, a pnp transistor ensures that the LBO pin

voltage remains below when: VCC < UVLO or ON/OFF pin

is released open or UVP or Thermal Shutdown. This is to

guarantee that the circuit starts operation in the right state,

which is “PFC_BO” high. When the NCP1910 is ready to

work, the pnp transistor turns off and the circuit enables the

ILBOH.

Also, ILBOH is enabled whenever the part is in off mode,

but at startup, ILBOH is disabled until VCC reaches VCC(on).

Line Brown−Out Network Calculation

If the line brown−out network is connected to the voltage

after bridge diode, the monitored voltage can be very

different depending on the phase:

•Before operation, the PFC stage is off and the input

bridge acts as a peak detector. As a consequence, the

input voltage is approximately flat and nearly equates

the ac line amplitude: <Vin> = √2 Vac,rms, where Vac,rms

is the rms voltage of the line. As depicted in previous

section, the ILBOH turns on before PFC operates for the

purpose of adjustable line brown−out hysteresis; hence,

the average voltage applied to LBO pin is:

VLBO +2

ǸVac,rms

RLBOL

RLBOU )RLBOL

*ILBOH

(eq. 9)

RLBOU @RLBOL

RLBOU )RLBOL

VLBO ]2

ǸVac,rms

RLBOL

RLBOU )RLBOL

*ILBOHRLBOL

If RLBOL << RLBOU,

•After the PFC stage has started operation, the input

voltage becomes a rectified sinusoid and the average

voltage becomes <Vin> = (2/p) √2 Vac,rms, which

decays 2/π of the peak value of rms input voltage.

Hence, the average voltage applied to LBO pin is:

<VLBO> = (2/p) √2 Vac,rms RLBOL/(RLBOU + RLBOL).

And because of the ripple on the LBO pin, the

minimum value of VLBO is around:

VLBO +2

ǸVac,rms

RLBOL

RLBOU )RLBOL (eq. 10)

ǒ1*

fLBO

3flineǓ

Where:

♦fLBO is the sensing network pole frequency.

fLBO +

RLBOU )RLBOL

2pRLBOURLBOLCLBO

♦fline is the line frequency.

♦RLBOL is low side resistor of the dividing resistors

between LBO pin and ground.

♦RLBOU is upper side resistor of the dividing resistors

between Vin and LBO pin.

The term 1*fLBO

3fline

of Equation 10 enables to take into

account the LBO pin voltage ripple (first approximation).

If as a rule of the thumb, we will assume that

fLBO +

fline

Re−arranging the Equation 9 and 10, the network connected

to LBO pin can be calculated with the following equations:

RLBOL +ȧ

1*fLBO

3fline

2@Vac,on

Vac,off

Ȥ@

VLBOT

ILBOH

(eq. 11)

^ǒ1

0.967 @p

2@Vac,on

Vac,off

*1Ǔ@

VLBOT

ILBOH

RLBOU +ǒ2

Ǹ@Vac,on

ILBOHRLBOL )VLBOT

*1ǓRLBOL

(eq. 12)

Where:

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♦Vac,on is the rms ac voltage to starts PFC operating.

♦Vac,off the rms ac voltage for line brown−out

detection.

PFC Current Sense

GND

CS NCP1910

ICS

RCS

RSENSE IL

−

VCS

Figure 47. PFC Current Sensing Configuration

The device senses the inductor current IL by the current

sense scheme in Figure 47. The device maintains the voltage

at CS pin to be zero voltage, i.e. VCS = 0 V, so that

ICS +

RSENSE

RCS

IL(eq. 13)

Where:

♦RSENSE is the sense resistor to sense IL.

♦RCS is the offset resistor between CS pin and

RSENSE.

This scheme has the advantage of the minimum number

of components for current sensing. The sense current ICS

represents the inductor current IL and will be used in the PFC

duty modulation to generate the multiplier voltage VM,

Over−Power Limitation (OPL), and Over−Current

Protection. Equation 13 would insist in the fact that it

provides the flexibility in the RSENSE choice and that it

allows to detect in−rush currents.

PFC Over−Current Protection (OCP)

PFC Over−Current Protection is reached when ICS is

larger than IS(OCP) (200 mA typical). The offset voltage of

the CS pin is typical 10 mV and it is neglected in the

calculation. Hence, the maximum OCP inductor current

threshold IL(OCP) is obtained in Equation 14.

ILǒOCPǓ+

RCSISǒOCPǓ

RSENSE

+RCS

RSENSE

200 mA(eq. 14)

When over−current protection threshold is reached, the

PFC drive goes low. The device automatically resumes

operation when the inductor current goes below the

threshold.

PFC Over−Power Limitation (OPL)

This is a second OCP with a threshold that is line

dependent. Sense current ICS represents the inductor current

IL and hence represents the input current approximately.

Input voltage signal VLBO represents the rms input voltage.

The product (ICS x VLBO) represents an approximated input

power (IL x Vac). It is illustrated in Figure 48.

Current

mirror

OPL

Vin

RSENSE

RCS

LBO

RLBOU

RLBOL CLBO

ICS

Figure 48. PFC Over−Power Limitation Configuration

> 275 mVA?

When the product (ICS x VLBO) is greater than a

permissible level 275 mVA, the device turns off the PFC

driver so that the input power is limited. The OPL is

automatically deactivated when the product (ICS x VLBO) is

lower than the 275 mVA level. This 275 mVA level

corresponds to the approximated input power (IL x Vac) to

be smaller than the particular expression in Equation 15.

ICSVLBO t275 mVA

(eq. 15)

ǒIL

RSENSE

RCS Ǔ ǒ22

ǸKLBO

p@VacǓt275 mVA

IL@Vac t

RCS @p

E@KLB

@97 mVA

Where

KLBO +

RLBOL

RLBOU )RLBOL

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PFC Reference Section

The internal reference voltage (VPREF) is trimmed to be

$2% accurate over the temperature range (the typical value

is 2.5 V). VPREF is the reference used for the regulation of

PFC section.

PFC Feedback and Compensation

OTA

Vbulk

Vin

RFBU

RFBL

VCTRL(min)

To Multiplier of VM pin

VCTRL

VPREF

Figure 49. VCTRL Type−2 Compensation

The output voltage Vbulk of the PFC circuits is sensed at

FB pin via the resistor divider (RFBL and RFBU) as shown in

Figure 49. Vbulk is regulated as described in Equation 16.

Vbulk +VPREF

RFBU )RFBL

RFBL

(eq. 16)

The feedback signal VFB represents the output voltage

Vbulk and will be used in the output voltage regulation,

Over−voltage protection (OVP), fast transient response, and

under−voltage protection (UVP)

The Operational Trans−conductance Amplifier (OTA)

constructs a control voltage, VCTRL, depending on the

output power and hence Vbulk. The operating range of

VCTRL is from VCTRL(min) to VCTRL(max). The signal used

for PFC duty modulation is after decreasing a offset voltage,

VCTRL(min), i.e. VCTRL−VCTRL(min).

This control voltage VCTRL is a roughly constant voltage

that comes from the PFC output voltage Vbulk that is a slowly

varying signal. The bandwidth of VCTRL can be additionally

limited by inserting the external type−2 compensation

components (that are RZ, CZ, and CP as shown in Figure 49).

It is recommended to limit cross over frequency of open loop

system below 20 Hz typically if the input ac voltage is 50 Hz

to achieve power factor correction purpose.

The transformer of Vbulk to VCTRL is as described in

Equation 16 if CZ >> CP

. GEA is the error amplifier gain.

VCTRL

Vbulk

+RFBL @GEARZ

RFBL )RFBU

@1)sRZCZ

sRZCZǒ1)sRZCPǓ(eq. 17)

PFC Power Analysis and Vin2 Feed−Forward

From Equation 7 through 13, the input impedance Zin is

re−formulated in Equation 18.

Zin +

2RMRSENSE @KLBO 2@Vac 2@VbulkIL

p2RCS @ǒVCTRL *VCTRLǒminǓǓ@VPREFIL−50

(eq. 18)

When IL is equal to IL−50, Equation 18 is re−formulated in

Equation 19.

Zin +

2RMRSENSE @KLBO 2@Vac 2@Vbulk

p2RCS @ǒVCTRL *VCTRLǒminǓǓ@VPREF

(eq. 19)

The multiplier capacitor CM is the one to filter the

high−frequency component of the multiplier voltage VM.

The high−frequency component is basically coming from

the inductor current IL. On the other hand, the input filter

capacitor Cin similarly removes the high−frequency

component of inductor current IL. If the capacitors CM and

Cin match with each other in terms of filtering capability, IL

becomes IL−50. Input impedance Zin is roughly constant over

the bandwidth of 50 or 60 Hz and power factor is corrected.

Input and output power (Pin and Pout) are derived in

Equations 20 and 21 when the circuit efficiency η is

obtained or assumed. The variable Vac stands for the rms

input voltage.

Pin +Vac 2

Zin

p2@RCS @ǒVCTRL *VCTRLǒminǓǓ@VPREF

2RMRSENSEKLBO 2@Vbulk

(eq. 20)

TǒVCTRL *VCTRLǒminǓǓ

Vbulk

Pin +hPin +h

p2@RCS @ǒVCTRL *VCTRLǒminǓǓ@VPREF

2RMRSENSEKLBO 2@Vbulk

(eq. 21)

TǒVCTRL *VCTRLǒminǓǓ

Vbulk

Because of the Vin2 feed−forward, the power delivery is

independent from input voltage. Hence the transfer function

of power stage is independent from input voltage, which

easies the compensation loop design.

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PFC Frequency Foldback

NCP1910 implements frequency foldback feature on PFC

section to improve the efficiency at light load. Thanks to

Vin2 feed−forward feature, the output power is proportional

to the (VCTRL − VCTRL(min)). The PFC frequency foldback

is hence done by comparing (VCTRL − VCTRL(min)) with

Vfold, the voltage on Fold pin.

The simplified block diagram of PFC frequency foldback

feature is depicted in Figure 50.

Figure 50. The PFC Frequency Foldback Block

−

“0” / ”1”

VPREF / 10%VPREF

Oscillator section

Vref

Ict(min)

Ict

Vfold

Vfold(max)

PFC OK

Grand Reset

PFCOSC

Vdd

Ict(fold)

PFC BO

Vctrl

Vctrl(min)

Where:

♦ICt(min) limits the minimum operating frequency.

♦ICt and ICt(min) provide the charging current for

oscillator and hence control the nominal operating

frequency.

♦Vfold determines the power level at which the

frequency foldback starts.

♦ICt(fold) steals the ICt and hence reduces the

operating frequency according to the error

information between Vfold and (VCTRL −

VCTRL(min)).

♦The transient slope of frequency foldback vs. VCTRL

is fixed inside.

♦Vfold(max) is to limit the maximum power level of

frequency foldback, which is around 2 V typically.

The frequency foldback is disabled at startup, i.e. before

the PFCok signal in Figure 50 is asserted high.

The user can adjust the power level at which the frequency

foldback starts by adjust the resistor divider between VREF

pin and fold pin. Also, the frequency foldback can be

disabled by grounding fold pin.

The relationship between operating frequency and VCTRL

is depicted in Figure 51.

VCTRL−VCTRL(min) T Power

Fsw(fold)

Fsw

Vfold

Vfold – 0.4

The slope is fixed internally.

The power level at which fre-

quency starts reducing is ad-

justable by modifying Vfold.

Figure 51. The Relationship between Frequency and VCTRL

FREQUENCY

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PFC Power Boost

As depicted in previous section, thanks to the Vin2

feed-forward, the power delivery is independent from input

voltage. It brings benefit of good power factor and a direct

control on the frequency foldback. However, in some special

case such as when the ac input voltage drops sharply from

high line to low line, the power will be limited because the

filter on LBO pin slows down the reaction speed to follow

up the change on input voltage. In the end, the bulk voltage

might drop too low and stop the LLC converter.

Hence, NCP1910 builds a so-called PFC power boost

function inside. The idea is to pull down LBO pin to 2 V

typically, VLBO(PD), when

•VLBO is above 2 V, VLBO(PD), i.e. the input is at high

line, and

•VCTRL is at maximum for more than timer defined by

tPFCflag, and,

•Vbulk is under 95% of nominal output, i.e. VLD is

triggered.

The maximum pulling-down duration is defined by

tLBO(PDlimit), which is 5 ms typically. A blanking timer,

tLBO(PDblank), is to avoid this power boost function reacting

too soon, which is about 77 ms typically. The PFC power

boost function is inhibited at start-up until bulk voltage is

above 95% of nominal output.

PFC Skip Mode

In order to ensure a proper regulation in no load

conditions, the circuit skips cycles when VCTRL is at its

minimum level. VCTRL is maintained between about 0.6 V

and 3.6 V due to the internal active clamps. A skip sequence

occurs as long as the 0.6 V clamp circuitry is triggered and

switching operations is recovered when the clamp is

inactive.

Fast Transient Response

Given the low bandwidth of the regulation block, the

output voltage of PFC stages may exhibit excessive over or

under−shoots because of abrupt load or input voltage

variations (such as start−up duration). As shown in

Figure 52, if the output voltage is out of regulation,

NCP1910 has 2 functions to maintain the output voltage

regulation.

−

VCTRL

RFBU

RFBL

CFB

105% VPREF

VLD

PFC_OVP

95% VPREF

PFC_OK PFC_OPL Vdd

IVLD

Vbulk

OTA

VPREF

$30 mA

200 mA

Figure 52. PFC OVP and VLD

•Over−Voltage Protection (OVP): When VFB is higher

than 105% of VPREF (i.e. Vbulk > 105% of nominal

bulk voltage), the PFC driver output goes low for

protection. The circuit automatically resumes operation

when VFB becomes lower than 103.2% of VPREF, i.e.

around 44 mV hysteresis in the OVP comparator. If the

nominal Vbulk is set at 390 V, then the maximum bulk

voltage is 105% of 390 V = 410 V. Hence a cost and

size effective bulk capacitor of lower voltage rating is

suitable for this application,

•Voltage−Low Detection (VLD): NCP1910 drastically

speeds up the regulation loop by its internal 200 mA

enhanced current source when the bulk voltage is below

95% of its regulation level. Under normal condition, the

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maximum sink and source of output current capability

of OTA is around 30 mA. Due to the “Vout Low Detect”

block (VLD), when the VFB is below 95% VPREF, an

extra 200 mA current source (IVLD in Figure 52) will

raise VCTRL rapidly. Hence prevent the PFC output

from dropping too low and improve the transient

response performance. The relationship between

current flowing in/out VCTRL pin and VFB is as shown

in Figure 53.

It is recommended to add a typical 100 pF capacitor CFB

decoupling capacitor next to feedback pin to prevent from

noise impact.

−250

−200

−150

−100

−50

2 2.2 2.4 2.6 2.8 3

VFB

VCTRL pin current (mA)

230 mA raises VCTRL rapidly

when VFB is below 95%

VPREF

No DRV when VFB is

above 105% VPREF

Figure 53. VFB vs. Current Flowing in/out From VCTRL Pin

PFCok Signal

The PFC provides a “PFCok” signal to:

•enable the dynamic response enhancer (IVLD) if Vbulk is

below 95%, finish of the PFC soft−start,

•enable the PFC frequency foldback,

•enable the timer (tDEL1), which is to start the LLC−HB

converter,

•enable the timer (tDEL2), which is to stop LLC−HB

converter once “PFCok” is asserted low or Vbulk is

lower than PG level after LLC−HB has started.

This “PFCok” signal is high when the PFC stage is in

normal operation, i.e. its output is above 95% of normal

output, and low otherwise.

Refer to Figure 54. “PFCok” signal is low when

•the PFC stage start−up, or

•any latch off signal arrives, or

•line brown−out activates.

“PFCok” signal is high when

•DRV starts operating and the PFC stage is above 95%

of target, i.e. the VLD comparator output is high, or

•the PFC stage is above 100% target, i.e. PFCREG

comparator output is high.

Grand Reset

PFC_OK

Latch

PFC_BO

−

VPREF

95% VPREF

VLD

PFCREG

DRV

Figure 54. PFCok Signal Block Diagram

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PFC Soft−Start

Refer to Figure 52 and 54. The device provides no PFC

driver output when the VCTRL is lower than VCTRL(min).

VCTRL is pulled low by:

•VCC Under−Voltage Lockout, or

•Off signal from on/off pin, or

•Thermal Shut−down (TSD), or

•Line Brown−out, or

•PFC Under−Voltage Protection

At one of these situations, NCP1910 grounds the VCTRL

pin and turns off the 200 mA current source in regulation

block.

When the IC turns on again:

•VCTRL will be pulled low and PFC DRV output keeps

off until VCTRL is below VCTRL(min) to make PFC

starts with lowest duty cycle.

•The 200 mA current source block keeps off. Only the

Operating Transconductance Amplifier (OTA) raises

the VCTRL slowly.

This is to obtain a slow increasing duty cycle and hence

reduce the voltage and current stress on the MOSFET. A

soft−start operation is obtained.

PFC Under−Voltage Protection (UVP) for Open Loop

Protection

ICC7

ICC2

8% VPREF 12% VPREF

VFB

Operating

Shutdown

Figure 55. PFC Under−Voltage Protection

As shown in Figure 55, when VFB is less than 8% of

VPREF, the device is shut down. The device automatically

starts operation when the output voltage goes above 12% of

VPREF. In normal situation of boost converter configuration,

the bulk voltage Vbulk is always greater than the input

voltage Vin and the feedback signal VFB has to be always

greater than 8% and 12% of VPREF to enable NCP1910 to

operate.

The main purpose of this Under−Voltage Protection

function is to protect the power stage from damage at

feedback loop abnormal, such as VFB is grounded or the

feedback resistor RFBU is open.

Redundant Over−Voltage Protection (OVP2 pin)

Except the Over−Voltage Protection in FB pin, NCP1910

also reserve one dedicated pin, OVP2 pin, for the redundant

over voltage protection on bulk voltage. The purpose of this

feature is to protect the power components from damage in

case of any drift on the feedback resistor. As shown in

Figure 56, the OVP2 has 3 differences compared to the OVP

in FB pin:

•The protection mode provided by OVP2 pin is

latch−off. When OVP2 is triggered, the NCP1910 stays

at latch off mode, i.e. both PFC and LLC stop.

•A 20 ms filter is built−in after the OVP2 comparator for

better noise immunity.

•The reference voltage for this OVP2 comparator is

107% of VPREF.

The resistance value of ROVPU and ROVPL could be the

same as RFBU and RFBL depending on the requirement of

OVP2 level. In this case, the level of the OVP in FB pin

would be 105% of normal bulk voltage and OVP2 will be

107% of normal bulk voltage. Or if one would need a higher

level for the OVP2, then it is flexible to change the value.

If someone doesn’t need this OVP2 feature, then OVP2

function could be disable by grounding the OVP2 pin.

ROVPU

ROVPL

COVP

107% VPREF

PFC_OVP2

Vbulk

20 ms filter

OVP2

to SR-latch

Figure 56. PFC 2nd Over−Voltage Protection

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PFC Abnormal

The PFC abnormal is detected by sensing VCTRL level.

When VCTRL stays at VCTRL(max), or lower than VCTRL(min)

– 0.1 V, for more than tPFCabnormal, PFC turns off first. After

tDEL2, LLC shuts down. It is latches off protection.

The main purpose of this feature is to avoid LLC from

operating without correct operation of PFC stage.

LLC Section

Current Controlled Oscillator (CCO)

The current controlled oscillator features a high−speed

circuitry allowing operation from 50 kHz up to 1 MHz.

However, as a D−flip−flop that creates division−by−two

internally provides two outputs (A and B in Figure 57), the

final effective signal on LLC driver outputs (ML and MU)

switches between 25 kHz and 500 kHz. The CCO is

configured in such a way that if the current that flows out

from the Rt pin increases, the switching frequency also goes

up.

VDD

Clk

Grand Reset

Latch

LLCenable

for ML

for MU

Grand Reset

LLC_PG

Grand Reset

Disable LLC ML and MU

Rmin

Rmax RSS

CSS

Feedback

opto-coupler

IDT

CS/FF > VCS1 LLC_BO

tDEL2 elapsed

VSS_RST

Figure 57. The Current Controlled Oscillator Architecture and Configuration

VRt

VCtmax

The internal timing capacitor Ct is charged by current

which is proportional to the current flowing out from the

Rt pin. The discharging current iDT is applied when voltage

on this capacitor reaches VCtmax. The output drivers are

disabled during discharge period so the dead time length is

given by the discharge current sink capability. Discharge

sink is disabled when voltage on the timing capacitor

reaches zero and charging cycle starts again. Ct is grounded

to disable the oscillator when either of “turn−off LLC”

signals arrives.

For the resonant applications, it is necessary to adjust

minimum operating frequency with high accuracy. The

designer also needs to limit maximum operating and startup

frequency. All these parameters can be adjusted by using

external components connected to the Rt pin as shown in

Figure 57.

The following approximate relationships hold for the

minimum, maximum and startup frequency respectively:

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•The minimum switching frequency is given by the Rmin

resistor value. This frequency is reached if there is no

feedback action and soft start period has already

elapsed.

Rmin +

490 106VRt

Fmin

(eq. 22)

•The maximum switching frequency excursion is limited

by the Rmax selection. Note that the maximum

frequency is influenced by the opto−coupler saturation

voltage value.

Rmax +

490 106VRt

Fmax *Fmin

(eq. 23)

•Resistor RSS together with capacitor CSS prepares the

soft start period for the resonant converter.

RSS +

490 106VRt

FSS *Fmin

(eq. 24)

Where:

♦VRt = 3.5 V

♦Fmin is the minimal frequency

♦Fmax is the maximal frequency

♦FSS is the maximal soft start switching frequency

LLC Power Good Signal and Brown−out (PGadj, PGout

and BOadj Pin)

As shown in Figure 22, the NCP1910 provides the

Brown−Out circuitry (BO) that offer a way to protect the

resonant converter from operating at too low Vbulk. In the

mean time, NCP1910 provides a Power Good signal (PGout)

to inform the isolated secondary side that the NCP1910 is in

order of match.

Once the PFC has started and raises Vbulk above 95% of

its regulated voltage, an internal “PFC_OK” signal is

asserted. 20 ms later (tDEL1), the PGout pin is brought low.

The PGout signal can now disappear, which will release

PGout pin open, in two cases:

•Vbulk decreases to the level, programmed by a reference

voltage imposed on PGadj pin. This level is usually

above the LLC turn−off voltage, programmed by BOadj

pin. Therefore, in a normal turn−off sequence, PG first

drops and informs the secondary side that it must be

prepared for shutdown.

•The second event that can drop the PG signal is when

the PFC experiences a fault: broken feedback path

(PFC UVP), PFC abnormal, or input line brown−out. In

either case, the internal PFCok signal will drop and

then assert the PGout signal high, and starts a 5 ms timer

(tDEL2). Once this timer is elapsed, the LLC converter

can be safely halted.

The definition of start−up, shut−off and these 2 delay

timers (tDEL1 and tDEL2) will be depicted later in “combo

management section”.

There are the other 2 delay timers are built−in after the

brown−out comparator:

•tBOK is the delay timer after Vbulk is rising above the

BO level.

•tBONOTOK is the delay timer after Vbulk is falling down

the BO level.

NCP1910 gets the information of Vbulk from the PFC FB

pin, which minimizes the losses of the high voltage sensing

circuit. As depicted in Figure 22, 3 resistors (R1, R2, and R3)

among VREF, PGadj, BOadj pin, and ground determine the

levels of PGout signal and LLC brown−out as the following

formulas:

VPG +R2)R3

R1)R2)R3

@VREF

(eq. 25)

+Vbulk,PG @RFBL

RFBU )RFBL

+Vbulk,PG @VPREF

Vbulk,nom

VBO +R3

R1)R2)R3

@VREF

(eq. 26)

+Vbulk,BO @RFBL

RFBU )RFBL

+Vbulk,BO @VPREF

Vbulk,nom

Where:

♦VPG is the voltage on PGadj pin

♦VBO is the voltage on BOadj pin

♦VREF is the reference voltage (5 V typically).

♦VPREF is the internal reference voltage for PFC

feedback OTA (2.5 V typically)

♦Vbulk,PG is the bulk voltage when PGout pin is

released open.

♦Vbulk,BO is the bulk voltage when brown−out

function of LLC activates.

♦Vbulk,nom is the normal bulk voltage, e.g. 390 V.

Divide Equation 25 by 26, we can get the relationship

between R2 and R3 in Equation 27:

Vbulk,PG

Vbulk,BO

*1(eq. 27)

Hence, by given Vbulk,PG and Vbulk,BO, and choose the

value R3 as the 1st step, we can get the R2 by Equation 27 and

R1 by Equation 26.

For example, Vbulk,nom is 390 V, Vbulk,PG is 340 V, and

Vbulk,BO is 330 V. Choose 10 kW resistor as R3. Then R2 is

303 W. Choose 300 W as it is the closet standard resistor.

Then we can get the R1 is 13.3 kW.

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PFC_FB

”1” BONOTOK

”1” enables LLC

”0” LLC is locked

Grand

Reset

LLC_BO

PFC_OK

”1” is ok

”0” notok

”1” after reset

”0” when PG out

drops after 5 ms

LLC_BO

”1” PGNOTOK

−

LLC_PG

LLCenable

VREF

BOadj

PGadj

PGout

R1R2

VCC

VSB

PGI for

supervisory

tBOK

tBONOTOK

tDEL1

tDEL2

20 ms

5 ms To close switch

at SS pin

SS is reset

Figure 58. The PG and BO Block Diagram for LLC

LLC Fast Fault Input (CS/FF Pin)

As shown in Figure 59, the NCP1910 offers a dedicated

input (CS/FF pin) to detect the primary over−current

conditions and protect the power stage from damage.

Once the voltage on the CS/FF pin exceeds the threshold

of VCS1 (1 V typically), the internal switch at SS pin will be

closed to discharge CSS until VSS is below VSS_RST

(150 mV typically). Hence the switching frequency of LLC

(ML and MU) is shifted up to keep the primary current under

acceptable level.

In case of heavy overload, like transformer short circuit,

the primary current grows very fast and thus could reach

danger level. The NCP1910 therefore features additional

comparator VCS2 (1.5 V typically) at the CS/FF pin to

permanently latch the device (both PFC and LLC) and

protect against destruction.

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−S

Grand Reset

Latch

”1” to disable LLC and PFC driver,

and pull down PFCok

−

”1” to set the SR−latch to

pull low SS pin

PFC_BO

CS/FF

VCS1

VCS2

PFC_OVP2

Figure 59. The Fast Fault Input at CS/FF pin

LLC Soft−Start (SS Pin)

In resonant converter, a soft−start is needed to avoid

suddenly applying the full current into the resonating circuit.

NCP1910 reserves SS pin to fully discharge soft−start

capacitor before re−start and in case of fault conditions:

•LLC brown−out actives,

•tDEL2 is elapsed, where tDEL2 timer could be activated

by line brown−out or power good comparator,

•CS/FF pin is above VCS1, the fast fault input for LLC,

•VCC UVLO,

•PFC UVP,

•Off signal from on/off pin, or

•Thermal Shut−Down (TSD)

When the switch inside SS pin is activated to discharge the

soft−start capacitor, it keeps close until VSS is below

VSS_RST (150 mV typically). It ensures the full discharge of

soft−start capacitor before re−start, and hence the fresh

soft−start is confirmed.

Once the LLC part starts operation, the internal switch at

SS pin is released open and the empty soft−start capacitor

withdraws current from Rt pin through soft−start resistor,

RSS. This current charges up and soft−start capacitor and

increases the operating frequency of LLC. As the soft−start

capacitor is charged, the LLC driver output frequency

smoothly decreases down to Fmin. Of course, practically, the

feedback loop is supposed to take over the CCO lead as soon

as the output voltage has reached the target.

LLC Skip (Skip Pin, B Version Only)

To avoid any frequency runaway in light conditions but

also to improve the standby power consumption, the

NCP1910B welcomes a skip mode operation (Skip pin)

which permanently observes the opto−coupler collector as

depicted in Figure 60. If skip pin senses a low voltage, it cuts

the LLC output pulses (ML and MU pins) until the collector

goes up again.

−

Rmin

Rmax RSS

CSS

Feedback

opto−coupler

Skip

VSkip

Disable ML and

Figure 60. The LLC Skip Mode Configuration

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LLC High−Voltage Driver

The NCP1910 includes a high−voltage driver allowing a

direct connection to the upper side MOSFET of LLC

converter. This device also incorporates an upper UVLO

circuitry that makes sure enough gate voltage is available for

the upper side MOSFET. The bias of the floating driver

section is provided by Cboot capacitor between Vboot pin and

HB pin that is refilled by external booststrap diode. The

floating portion can go up to 600 Vdc and makes the IC

perfectly suitable for offline applications featuring a 400 V

PFC front−end stage.

Combo Management Section

Start−up and Stop Delay of LLC and Pgout signal

(tDEL1 and tDEL2)

To ensure the proper operation of LLC, LLC cannot start

if the PFC is not ready.

As depicted in the “PFCok signal” section, the internal

PFCok signal is asserted high when Vbulk is above 95% of

normal bulk voltage. After PFCok signal is high, a timer

(tDEL1) starts to ensure PFC stage is fully stable before LLC

starts. When tDEL1 is elapsed, PGout pin is grounded and

LLC starts its driver outputs (ML and MU pins).

In case of shutdown by unplugging ac input or line brown

out situation, PGout signal is released open. And then

another timer (tDEL2) starts. Once the tDEL2 is elapsed, LLC

stops its drivers (ML and MU pins).

Figure 61 depicts the start−up and stop delay of LLC and

PGout.

Once the PFC is ready (PFCok is asserted high), tDEL1

(20 ms typically) is started. Once this delay is elapsed:

•PGout pin is asserted low

•LLC drivers (ML and MU pins) can start to operate.

As shutdown by unplug ac input, Vbulk decreases:

•When it reaches the PG signal, which is adjusted by

PGadj pin, PGout pin is released open.

•If Vbulk reaches the LLC stop level (BO level adjusted

by BOadj pin), the LLC stops; or if Vbulk drops slowly,

e.g. light load, LLC drivers (ML and MU pins) will

stop 5 ms after PGout pin is released (tDEL2).

As shutdown by line brown−out situation, PFCok signal will

be pulled down:

•PGout pin is released open once this internal PFCok

signal is low.

•LLC drivers (ML and MU pins) will stop 5 ms after

PGout pin is released open (tDEL2).

Vbulk

time

95%

LLC works

off

tDEL1

tDEL2

5 ms

PG level

20 ms

PGout

BO level

Figure 61. The Timing for tDEL1 and tDEL2

Remote on/off (on/off pin)

NCP1910 reserves one dedicated pin for remote control

feature at on/off pin:

•When the on/off pin is pulled below 1 V, the PFC starts

operation. 20 ms after Vbulk is above 95% of target

level, LLC starts.

•When the on/off pin is above 3 V, the device stops both

PFC and LLC immediately and keeps low

consumption. Figure 62 depicts the relationship

between the operation mode and on/off pin.

NCP1910

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On/off pin

State

Von Voff On/off pin

ICC

TBD

< 600 mA

OFF

Figure 62. Remote on/off (on/off Pin)

VCC Under−Voltage LockOut (UVLO)

The device incorporates an Under−Voltage Lockout block

to prevent the circuit from operating when VCC is too low in

order to ensure a proper operation. An UVLO comparator

monitors VCC pin voltage to allow the NCP1910 to operate

when VCC exceeds VCC(on). The comparator incorporates

some hysteresis (VCC(Hys)) to prevent erratic operation as

the VCC crosses the threshold. When VCC goes below the

UVLO comparator lower threshold (VCC(min)), the circuit

turns off. It is illustrated in Figure 63. After startup, the

operating range is between 9 V and 20 V.

VCC

State

VCC(min) VCC(on)

ICC

TBD

< 100mA

OFF

Figure 63. VCC Under−Voltage LockOut (UVLO)

VCC

Bias the Controller

It is recommended to add a typical 1 nF to 100 nF

decoupling capacitor next to the VCC pin for proper

operation. The hysteresis between VCC(on) and VCC(min) is

small because the NCP1910 is supposed to be biased by

external power source. Therefore it is recommended to

make a low−voltage source to bias NCP1910, e.g. the

standby power supply.

Thermal Shutdown

An internal thermal circuitry disables the circuit gate drive

and then keeps the power switch off when the junction

temperature exceeds TSD level. The output stage is then

enabled once the temperature drops below typically 110°C

(i.e. TSD − TSDhyste). The thermal shutdown is provided to

prevent possible device failures that could result from an

accidental over−heating.

5 V Reference

The VREF pin provides an accurate ($ 2% typically) 5 V

reference voltage. The Power−Good and Brown−Out of

LLC converter, and the frequency foldback level (fold pin)

of PFC can hence can get an accurate reference voltage by

resistor dividers.

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Latched Protections and Reset

As depicated in the above sections, there are 3 fault modes

that latch off both PFC and LLC:

•PFC abnormal

•PFC OVP2

•LLC CS/FF pin is above VCS2

To release from the latch−off mode, NCP1910 offers 3

ways:

•Recycle VCC so that VCC is below VCC(min) and back

to above VCC(on) again.

•Recycle the remote on/off function, which toggles

on/off pin high and low again.

•Recycle the line brown−out function, which could be

done by unplug and re−plug the ac input.

ORDERING INFORMATION

Device Version Marking Package Shipping†

NCP1910A65DWR2G 65 kHz − A NCP1910A65 SOIC 24WB Less Pin 21

(Pb−Free)

1000 / Tape & Reel

NCP1910B65DWR2G 65 kHz − B NCP1910B65 SOIC 24WB Less Pin 21

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NCP1910

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PACKAGE DIMENSIONS

SOIC−24 WB LESS PIN 21

CASE 752AB−01

ISSUE O

0.25 C

SEATING

PLANE

A1 e

DETAIL A

END VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL

BE 0.10 mm TOTAL IN EXCESS OF ’b’ AT MAXIM-

UM MATERIAL CONDITION.

4. DIMENSIONS b AND c APPLY TO THE FLAT SEC-

TION OF THE LEAD AND ARE MEASURED

BETWEEN 0.10 AND 0.25 FROM THE LEAD TIP.

5. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS. MOLD

FLASH, PROTRUSIONS OR GATE BURRS SHALL

NOT EXCEED 0.15 mm PER SIDE. INTERLEAD

FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 PER SIDE. DIMENSIONS D AND E1 ARE

DETERMINED AT DATUM H.

6. DIMENSIONS D AND E1 ARE DETERMINED AT

THE OUTERMOST EXTREMES OF THE PLASTIC

BODY EXCLUSIVE OF MOLD FLASH,

PROTRUSIONS, TIE BAR BURRS, OR GATE

BURRS BUT INCLUSIVE OF ANY MOLD

MISMATCH BETWEEN THE TOP AND BOTTOM OF

THE PLASTIC BODY.

7. DIMENSIONS A AND B ARE TO BE DETERMINED

AT DATUM H.

8. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

9. THIS CHAMFER IS OPTIONAL. IF IT IS NOT

PRESENT, THEN A PIN 1 IDENTIFIER MUST BE

LOCATED IN THE INDICATED AREA.

NOTES 3 & 4

PIN 1

24 13

TOP VIEW

DIM MIN MAX

MILLIMETERS

A2.35 2.65

b0.31 0.51

e1.27 BSC

h0.25 0.75

J0.20 0.33

A1 0.10 0.29

L0.40 1.27

M0 8

SIDE VIEW

11.00

23X

0.52

23X

1.62

1.27

DIMENSIONS: MILLIMETERS

PITCH

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

D15.40 BSC

E10.30 BSC

E1 7.50 BSC

L2 0.25 BSC

RECOMMENDED

INDICATOR

A-B D

NOTE 7

0.10 C D

0.33 C

0.20 C A-B

NOTES 5 & 6

24X

NOTE 7

0.10 C

NOTE 8

0.10 C x 45

NOTE 9

DETAIL A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

NCP1910/D

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